1. A method of reducing sense current in an array of fuses by encoding a bit stream representing a state for each of the fuses in the array of fuses, comprising:
counting a number of fuses to be blown in the array of fuses through a first counter receiving the bit stream;
contemporaneously counting a number of fuses to remain unblown in the array of fuses through a second counter receiving the bit stream, each counting operation performed according to a common clock cycle;
comparing the number of fuses to be blown and the number of fuses to remain unblown in the array of fuses through a comparator receiving output from both the first and the second comparators;
inverting each bit of the bit stream based on a result of the comparing; and
storing a bit value for use as a selection logic signal for all logic decoding circuits that decode the bit stream, each of the logic decoding circuits coupled to a corresponding fuse storing a bit of the bit stream.
2. The method of claim 1, further comprising:
decoding the bit stream by selecting one of a plurality of inputs to the logic decoding circuits.
3. The method of claim 2, wherein the logic decoding circuits are multiplexers and the bit value is supplied as a select signal to each of the multiplexers.
4. The method of claim 1, further comprising:
coupling the array of fuses to at least one other array of fuses.
5. The method of claim 1, wherein a blown fuse consumes less sense current than an unblown fuse.
6. The method of claim 1, further comprising;
selecting one of an output or an inverted output from each of the fuses based on the bit value, the bit value being a result of the comparing.
7. The method of claim 2, further comprising:
transferring the decoded bit stream to a Joint Test Action Group (JTAG) interface.
8. A machine-readable medium including machine-readable instructions that, if executed by a machine, cause the machine to perform operations of:
recording a number of occurrences of a first value in a bit stream, wherein the first value represents a number of fuses to be blown in an array of fuses;
recording a number of occurrences of a second value in the bit stream, wherein the second value represents a number of fuses to remain unblown in the array of fuses;
comparing the number of occurrences of the first value with the number of occurrences of the second value;
inverting each of the first and second values when the number of occurrences of the second value is greater than the number of occurrences of the first value; and
storing a bit value for use as a selection logic signal for all logic decoding circuits that decode the bit stream, each of the logic decoding circuits coupled to a corresponding fuse storing a bit of the bit stream.
9. The machine readable medium of claim 8 further comprising: decoding the bit stream by selecting one of a plurality of inputs to the logic decoding circuits based on the selection logic signal.
10. The machine readable medium of claim 9, wherein the logic decoding circuits are multiplexers and the bit value is supplied as a select signal to each of the multiplexers.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A signal processing circuit applied to a headset, wherein the headset comprises a left earphone, a right earphone and a microphone, and the signal processing circuit receives a sound signal from the microphone, and generates audio signals to the left earphone and the right earphone, respectively; the signal processing circuit comprising:
an analog-to-digital converter, arranged for receiving the sound signal from the microphone, and converting the sound signal into a digital input signal;
an audio processing circuit, arranged for generating a left channel signal and a right channel signal, wherein the left channel signal and the right channel signal are utilized to generate the audio signals;
a first gain and phase adjuster, coupled to the audio processing circuit, wherein the first gain and phase adjuster is arranged to adjust gains and phases of the left channel signal and the right channel signal to generate a first adjusted signal; and
a first adder, coupled to the analog-to-digital converter, the first gain and phase adjuster, and the audio processing circuit, wherein the first adder is arranged to combine the digital input signal and the first adjusted signal to generate an adjusted digital input signal, and provide the adjusted digital input signal to the audio processing circuit.
2. The signal processing circuit of claim 1, wherein the signal processing circuit is configured in a chip, the chip is connected to an audio jack, the headset further comprises an audio plug arranged for connecting to the audio jack, and a grounding point on the audio jack is connected to a grounding point in the chip through a layout trace; a part of the audio signal is mixed to the sound signal, and the first adder is utilized to cancel the part of the audio signal in the digital input signal to generate the adjusted digital input signal.
3. The signal processing circuit of claim 1, further comprising:
a second gain and phase adjuster, coupled to the audio processing circuit, wherein the second gain and phase adjuster is arranged to adjust a gain and a phase of the right channel signal to generate a second adjusted signal;
a second adder, coupled to the second gain and phase adjuster and the audio processing circuit, wherein the second adder is arranged to combine the left channel signal and the second adjusted signal to generate an adjusted left channel signal;
a first digital-to-analog converter, coupled to the second adder, wherein the first digital-to-analog converter is arranged to perform a digital-to-analog conversion upon the adjusted left channel signal to generate a left channel audio signal in the audio signals;
a third gain and phase adjuster, coupled to the audio processing circuit, wherein the third gain and phase adjuster is arranged to adjust a gain and a phase of the left channel to generate a third adjusted signal;
a third adder, coupled to the third gain and phase adjuster and the audio processing circuit, wherein the third adder is arranged to combine the right channel signal and the third adjusted signal so as to generate an adjusted right channel signal; and
a second digital-to-analog converter, coupled to the third adder, wherein the second digital-to-analog converter is arranged to perform a digital-to-analog conversion upon the adjusted right channel signal to generate a right channel audio signal in the audio signal.
4. The signal processing circuit of claim 3, wherein the signal processing circuit is configured in a chip, the chip is connected to an audio jack, the headset further comprises an audio plug arranged for connecting to the audio jack, and a grounding point on the audio jack is connected to a grounding point in the chip through a layout trace; apart of the right channel audio signal is mixed to the left channel audio signal when the right channel audio signal is transmitted to the right earphone, apart of the left channel audio signal is mixed to the right channel audio signal when the left channel audio signal is transmitted to the left earphone, the second adder is utilized to adjust the left channel signal in advance to reduce interference resulting from the right channel audio signal, and the third adder is utilized to adjust the right channel signal in advance to reduce interference resulting from the left channel audio signal.
5. A signal processing circuit applied to a headset, wherein the headset comprises a left earphone, a right earphone and a microphone, and the signal processing circuit receives a sound signal from the microphone, and generates audio signals to the left earphone and the right earphone, respectively; the signal processing circuit comprising:
an audio processing circuit, arranged for generating a left channel signal and a right channel signal;
a first gain and phase adjuster, coupled to the audio processing circuit, the first gain and phase adjuster arranged to adjust a gain and a phase of the right channel signal to generate a first adjusted signal;
a first adder, coupled to the first gain and phase adjuster and the audio processing circuit, the first adder arranged to combine the left channel signal and the first adjusted signal to generate an adjusted left channel signal;
a first analog-to-digital converter, coupled to the first adder, the first analog-to-digital converter arranged to perform an analog-to-digital conversion upon the adjusted left channel signal to generate a left channel audio signal in the audio signals;
a second gain and phase adjuster, coupled to the audio processing circuit, the second gain and phase adjuster arranged to adjust a gain and a phase of the left channel signal to generate a second adjusted signal;
a second adder, coupled to the second gain and phase adjuster and the audio processing circuit, the second adder arranged to combine the right channel signal and the second adjusted signal to generate an adjusted right channel signal; and
a second analog-to-digital converter, coupled to the second adder, the second analog-to-digital converter arranged to perform an analog-to-digital conversion upon the adjusted right channel signal to generate a right channel audio signal in the audio signals.
6. The signal processing circuit of claim 5, wherein the signal processing circuit is configured in a chip, the chip is connected to an audio jack, the headset further comprises an audio plug arranged for connecting to the audio jack, and a grounding point on the audio jack is connected to a grounding point in the chip through a layout trace; a part of the right channel audio signal is mixed to the left channel audio signal when the right channel audio signal is transmitted to the right earphone, a part of the left channel audio signal is mixed to the right channel audio signal when the left channel audio signal is transmitted to the left earphone, the first adder is utilized to adjust the left channel signal in advance to reduce interference resulting from the right channel audio signal, and the second adder is utilized to adjust the right channel signal in advance to reduce interference resulting from the left channel audio signal.
7. A signal processing method applied to a headset, wherein the headset comprises a left earphone, a right earphone and a microphone, the signal processing method comprising:
receiving a sound signal from the microphone, and converting the sound signal into a digital input signal;
generating a left channel signal and a right channel signal, wherein the left channel signal and the right channel signal are utilized to generate audio signals outputted to the left earphone and the right earphone, respectively;
adjusting gains and phases of the left channel signal and the right channel signal, to generate a first adjusted signal; and
combining the digital input signal and the first adjusted signal, to generate an adjusted digital input signal.
8. The signal processing method of claim 7, wherein the signal processing method of is performed by a circuit configured in a chip, the chip is connected to an audio jack, the headset further comprises an audio plug arranged for connecting to the audio jack, and a grounding point on the audio jack is connected to a grounding point in the chip through a layout trace; a part of the audio signal is mixed to the sound signal, and the adjusted digital input signal is utilized to cancel the part of the digital input signal.
9. The signal processing method of claim 7, further comprising:
adjusting a gain and a phase of the right channel signal, to generate a second adjusted signal;
combining the left channel signal and the second adjusted signal, to generate an adjusted left channel signal;
performing a digital-to-analog conversion upon the adjusted left channel signal, to generate a left channel audio signal in the audio signals;
adjusting a gain and a phase of the left channel, to generate a third adjusted signal;
combining the right channel signal and the third adjusted signal, to generate an adjusted right channel signal; and
performing a digital-to-analog conversion upon the adjusted right channel signal, to generate a right channel audio signal in the audio signal.
10. The signal processing method of claim 9, wherein the signal processing method is performed by a circuit configured in a chip, the chip is connected to an audio jack, the headset further comprises an audio plug arranged for connecting to the audio jack, and a grounding point on the audio jack is connected to a grounding point in the chip through a layout trace; a part of the right channel audio signal is mixed to the left channel audio signal when the right channel audio signal is transmitted to the right earphone, a part of the left channel audio signal is mixed to the right channel audio signal when the left channel audio signal is transmitted to the left earphone, and the step of generating the adjusted left channel signal is utilized to avoid interference resulting from the right channel audio signal in advance, and the step of generating the adjusted right channel signal is utilized to avoid interference resulting from the left channel audio signal in advance.
11. A signal processing method applied to a headset, wherein the headset comprises a left earphone, a right earphone and a microphone, the signal processing method comprising:
generating a left channel signal and a right channel signal;
adjusting a gain and a phase of the right channel signal, to generate a first adjusted signal;
combining the left channel signal and the first adjusted signal, to generate an adjusted left channel signal;
performing an analog-to-digital conversion upon the left channel signal, to generate a left channel audio signal to the left earphone;
adjusting a gain and a phase of the left channel signal, to generate a second adjusted signal;
combining the right channel signal and the second adjusted signal, to generate an adjusted right channel signal; and
performing an analog-to-digital conversion upon the right channel signal, to generate a right channel audio signal to the right earphone.
12. The signal processing method of claim 11, wherein the signal processing method performed by a circuit in a chip, the chip is connected to an audio jack, the headset further comprises an audio plug arranged for coupling to the audio jack, and a grounding point on the audio jack is connected to a grounding point in the chip through a layout trace; a part of the right channel audio signal is mixed to the left channel audio signal when the right channel audio signal is transmitted to the right earphone, a part of the left channel audio signal is mixed to the right channel audio signal when the left channel audio signal is transmitted to the left earphone, the step of generating the adjusted left channel signal is utilized to avoid interference resulting from of the right channel audio signal in advance, and the step of generating the adjusted right channel signal is utilized to avoid interference resulting from the left channel audio signal in advance.