1. A process for the industrial synthesis of a compound of formula (I)
wherein 7-methoxy-1-tetralone of formula (III):
is reacted with cyanoacetic acid of formula (IV):
under conditions wherein the water formed is removed, in the presence of a catalytic amount of a compound of formula (V):
wherein R and R\u2032, which may be the same or different, each represents linear or branched (C3-C10)alkyl, unsubstituted or substituted aryl, or unsubstituted or substituted linear or branched aryl (C1-C6)alkyl,
to yield, after filtration and washing with a basic solution, (7-methoxy-3,4-dihydro-1-naphthalenyl)acetonitrile of formula (VI):
the compound of formula (VI) thus obtained is reacted with a hydrogenation catalyst in the presence of an allyl compound to yield a compound of formula (VII):
the compound of formula (VII) thus obtained is then subjected to reduction with hydrogen in the presence of Raney nickel in an ammoniacal ethanol medium, and subsequently converted to a salt using hydrochloric acid to yield a compound of formula (VIII):
the compound of formula (VIII) thus obtained is subjected successively to the action of sodium acetate and then acetic anhydride to yield the compound of formula (I), which is isolated in the form of a solid,
it being understood that:
aryl may be phenyl, naphthyl or biphenyl,
the term \u201csubstituted\u201d associated with the terms \u201caryl\u201d and \u201carylalkyl\u201d denotes that the aromatic moiety of those groups may be substituted by one or more, identical or different, groups selected from linear or branched (C1-C6)alkyl, hydroxy and linear or branched (C1-C6)alkoxy, and
\u201callyl compound\u201d may be any molecule containing from 3 to 10 carbon atoms, which may additionally contain 1 to 5 oxygen atoms, and containing at least one \u2014CH2\u2014CH\u2550CH2 group.
2. The process of claim 1, wherein the conversion of the compound of formula (III) to the compound of formula (VI) is carried out in refluxing toluene.
3. The process of claim 1, wherein R represents hexyl.
4. The process of claim 1, wherein R\u2032 represents benzyl.
5. The process of claim 1, wherein the compound of formula (V) is selected from those of formula (Va):
wherein R\u2032a represents phenyl unsubstituted or substituted by one or more linear or branched (C1-C6)alkyl groups, n is 0 or 1, and Ra represents linear (C3-C10)alkyl.
6. The process of claim 1, wherein the compound of formula (V) is benzylammonium heptanoate of formula (IX):
7. The process of claim 1, wherein the conversion of the compound of formula (VI) to the compound of formula (VII) is carried out in refluxing toluene.
8. The process of claim 1, wherein the hydrogenation catalyst used in the conversion of the compound of formula (VI) to the compound of formula (VII) is palladium.
9. The process of claim 1, wherein the hydrogenation catalyst used in the conversion of the compound of formula (VI) to the compound of formula (VII) is 5% palladium-on-carbon.
10. The process of claim 1, wherein the amount of hydrogenation catalyst used in the conversion of the compound of formula (VI) to the compound of formula (VII) is 5% by weight of catalyst in relation to the weight of substrate.
11. The process of claim 1, wherein the conversion of the compound of formula (VII) to the compound of formula (VIII) is carried out at 40\xb0 C.
12. The process of claim 1, wherein the conversion of the compound of formula (VIII) to the compound of formula (I) is carried out in ethanol.
13. A process for the synthesis of agomelatine starting from the compound of formula (VI), wherein the compound of formula (VI) is obtained by the process of claim 1, and is subjected to aromatisation followed by reduction and then to coupling with acetic anhydride.
14. A process for the synthesis of agomelatine starting from the compound of formula (VII), wherein the compound of formula (VII) is obtained by the process of claim 1, and is subjected to reduction and then to coupling with acetic anhydride.
15. A process for the synthesis of agomelatine starting from the compound of formula (VIII), wherein the compound of formula (VIII) is obtained by the process of claim 1, and is subjected to coupling with acetic anhydride.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A method for executing a locked-memory instruction, the method comprising:
obtaining exclusive ownership of a cacheline for a load-lock operation;
setting a bit to indicate the load-lock operation’s ownership of the cacheline;
storing a modified version of a load data value;
determining that the cacheline is still exclusively owned;
storing the load data value;
determining that the cacheline is unsnooped;
merging the modified version of the load data value with the stored load data value; and
releasing the locked-memory instruction to be retired.
2. The method of claim 1 further comprising:
decoding the locked-memory instruction; and
breaking the locked-memory instruction into the load-lock operation, a modify operation; and a store-unlock operation.
3. The method of claim 1 further comprising
allocating a write combining buffer entry; and
setting a lock register by storing an address in the lock register of a store-unlock operation that reserved the write combining buffer entry.
4. The method of claim 3 further comprising:
delaying a snoop checking process during a critical sequence in the execution of the locked-memory instruction.
5. The method of claim 4 wherein said delaying the snoop checking process during a critical sequence in the execution of the locked-memory instruction comprises:
delaying the snoop checking process while
allocating the write combining buffer entry in an exclusive state,
checking to determine whether a snoop of the executing instruction occurred, and
updating the write combining buffer entry with the stored load data value.
6. The method of claim 1 further comprising:
requesting the load data value be returned in an exclusive state, if the cacheline is in a non-exclusive state; and
determining that the cacheline is still exclusively owned.
7. The method of claim 1 further comprising:
flushing the locked-memory instruction and all younger dependent instructions, if the cacheline has been snooped; and
restarting the method by re-executing said obtaining exclusive ownership of the cacheline for the load-lock operation.
8. A machine-readable medium having stored thereon a locked-memory instruction, said locked memory instruction executable to perform a method comprising:
obtaining exclusive ownership of a cacheline for a load-lock operation;
setting a bit to indicate the load-lock operation’s ownership of the cacheline;
storing a modified version of a load data value;
determining that the cacheline is still exclusively owned;
storing the load data value;
determining that the cacheline is unsnooped;
merging the modified version of the load data value with the stored load data value; and
releasing the locked-memory instruction to be retired.
9. The machine-readable medium of claim 8, said method further comprising:
decoding the locked-memory instruction; and
breaking the locked-memory instruction into the load-lock operation, a modify operation, and a store-unlock operation.
10. The machine-readable medium of claim 8, said method further comprising:
allocating a write combining buffer entry; and
setting a lock register by storing an address in the lock register of a store-unlock operation that reserved the write combining buffer entry.
11. The machine-readable medium of claim 10, said method further comprising:
delaying a snoop checking process during a critical sequence in the execution of the locked-memory instruction.
12. The machine-readable medium of claim 111 wherein said delaying the snoop checking process during a critical sequence in the execution of the locked-memory instruction comprises:
delaying the snoop checking process while
allocating the write combining buffer entry in an exclusive state,
checking to determine whether a snoop of the executing instruction occurred, and
updating the write combining buffer entry with the stored load data value.
13. The machine-readable medium of claim 8, said method further comprising:
requesting the load data value be returned in an exclusive state, if the cacheline is in a non-exclusive state; and
determining that the cacheline is still exclusively owned.
14. The machine-readable medium of claim 8, said method further comprising:
flushing the locked-memory instruction and all younger dependent instructions, if the cacheline has been snooped; and
restarting the method by re-executing said obtaining exclusive ownership of the cacheline for the load-lock operation.
15. A processor comprising:
a first cache;
a load buffer coupled to the first cache;
a control logic component coupled to the load buffer;
a store buffer;
a pause queue coupled to the store buffer;
a write combining buffer coupled to the pause queue and the first cache; and
a lock register coupled to the pause queue and the load buffer.
16. The processor of claim 15 further comprising:
a second cache coupled to the first cache.
17. The processor of claim 15 wherein said processor is implemented as a plurality of processors in a multi-processor system such that each of said plurality of processors includes a separate set of hardware resources.
18. A processor comprising:
a first cache to store a local copy of a cacheline and to maintain exclusivity information associated with the local copy of the cacheline for use by a locked-memory instruction;
a load buffer coupled to the first cache, the load buffer to receive and queue a load-lock operation and an associated load data value;
a control logic component coupled to the load buffer, the control logic component to control retirement of the locked-memory instruction;
a store buffer to receive and queue a store-unlock operation and the load data value;
a pause queue coupled to the store buffer, the pause queue to store a modified version of the load data value and execute a store-unlock operation received from the store buffer;
a lock register coupled to the pause queue and the load buffer, the lock register to receive and store an address of the store-unlock operation; and
a write combining buffer coupled to the pause queue and the first cache, the write combining buffer to receive the modified version of the load data value from the pause queue and merge the modified version of the load data value with the load data value.
19. The processor of claim 18 further comprising:
a second cache coupled to the first cache to store an original version of the cacheline.
20. The processor of claim 18 wherein said processor is implemented as a plurality of processors in a multi-processor system such that each of said plurality of processors includes a separate set of hardware resources.