1. A computer-implemented system for assigning sequence numbers, comprising:
(a) a computer system; and
(b) sequence number assignment logic, performed by the computer system, for generating a recoverable, unique sequence number for assignment to an application, wherein the sequence number is contained in a control page stored in a database on a data storage device coupled to the computer system and shared with other computer systems, and updates to the control page are serialized across all of the computer systems.
2. The system of claim 1, wherein the control page includes one or more attributes selected from a group of attributes comprising an identifier, the sequence number (SN), a range value (N), and a starting sequence number (Starting SN).
3. The system of claim 2, wherein the identifier is a user-defined value that identifies a user for the sequence number.
4. The system of claim 2, wherein a value stored in N identifies a range of sequence number assignments.
5. The system of claim 1, wherein one or more attributes from the control page are stored in a data structure that is stored in the computer system.
6. The system of claim 5, wherein the data structure includes one or more attributes selected from a group of attributes comprising a sequence number (SN_MEM) and a \u201cnumber remaining\u201d value (N_REM).
7. The system of claim 6, wherein a value stored in N_REM indicates when a range of sequence numbers should be obtained from the control page.
8. The system of claim 1, wherein the control page is periodically saved to the data storage device, in order to effect a hardening of the control page.
9. The system of claim 1, wherein the sequence number assignment logic further comprises logic for latching the sequence number to serialize generation of the sequence number within the computer system.
10. The system of claim 1, wherein the sequence number assignment logic further comprises logic for physically locking the control page to serialize updates to the control page across multiple computer systems.
11. The system of claim 10, wherein the physical lock is not maintained when the computer system fails, so that other computer systems are not prevented from continuing to generate new sequence numbers.
12. A method of assigning sequence numbers in a computer-implemented system, comprising:
(a) generating a recoverable, unique sequence number using sequence number assignment logic performed by a computer system for assignment to an application; and
(b) storing the sequence number in a control page, wherein the control page is stored in a database on a data storage device coupled to the computer system and shared with other computer systems, and updates to the control page are serialized across all of the computer systems.
13. The method of claim 12, wherein the control page includes one or more attributes selected from a group of attributes comprising an identifier, the sequence number (SN), a range value (N), and a starting sequence number (Starting SN).
14. The method of claim 13, wherein the identifier is a user-defined value that identifies a use for the sequence number.
15. The method of claim 13, wherein a value stored in N identifies a range of sequence number assignments.
16. The method of claim 12, wherein one or more attributes from the control page are stored in a data structure that is stored in the computer system.
17. The method of claim 16, wherein the data structure includes one or more attributes selected from a group of attributes comprising a sequence number (SN_MEM) and a \u201cnumber remaining\u201d value (N_REM).
18. The method of claim 17, wherein a value stored in N_REM indicates when a range of sequence numbers should be obtained from the control page.
19. The method of claim 12, wherein the control page is periodically saved to the data storage device, in order to effect a hardening of the control page.
20. The method of claim 12, wherein the sequence number assignment step further comprises latching the sequence number to serialize generation of the sequence number within the computer system.
21. The method of claim 12, wherein the sequence number assignment step further comprises physically locking the control page to serialize updates to the control page across multiple computer systems.
22. The method of claim 21, wherein the physical lock is not maintained when the computer system fails, so that other computer systems are not prevented from continuing to generate new sequence numbers.
23. An article of manufacture embodying logic for performing a method of assigning sequence numbers in a computer-implemented system, the method comprising:
(a) generating a recoverable, unique sequence number using sequence number assignment logic performed by a computer system for assignment to an application; and
(b) storing the sequence number in a control page, wherein the control page is stored in a database on a data storage device coupled to the computer system and shared with other computer systems, and updates to the control page are serialized across all of the computer systems.
24. The of manufacture of claim 23, wherein the control page includes one or more attributes selected from a group of attributes comprising an identifier, the sequence number (SN), a range value (N), and a starting sequence (Starting SN).
25. The article of manufacture of claim 24, wherein the identifier is a user-defined value that identifies a use for the sequence number.
26. The article of manufacture of claim 24, wherein a value stored in N identifies a range of sequence number assignments.
27. The article of manufacture of claim 23, wherein one or more attributes from the control page are stored in a data structure that is stored in the computer system.
28. The article of manufacture of claim 27, wherein the data structure includes one or more attributes selected from a group of attributes comprising a sequence number (SN_MEM) and a \u201cnumber remaining\u201d value (N_REM).
29. The article of manufacture of claim 28, wherein a value stored in N_REM indicates when a range of sequence numbers should be obtained from the control page.
30. The article of manufacture of claim 23, wherein the control page is periodically saved to the data storage device, in order to effect a hardening of the control page.
31. The article of manufacture of claim 23, wherein the sequence number assignment step further comprises latching the sequence number to serialize generation of the sequence number within the computer system.
32. The article of manufacture of claim 23, wherein the sequence number assignment step further comprises physically locking the control page to serialize updated to the control page across multiple computer systems.
33. The article of manufacture of claim 32, wherein the physical lock is not maintained when the computer system fails, so that other computer systems are not prevented from continuing to generate new sequence numbers.
34. A data structure by a sequence number assignment logic performed by a computer system, the data structure comprising:
a control page that contains a sequence number that has no restrictions on its size, an identifier that is a user-defined value that identifies a use for the sequence number, a range value (N) that identifies a range of sequence number assignments, and a starting sequence number (Starting SN) that comprises an initial value for the sequence number, wherein the control page is stored in a database on a data storage device coupled to the computer system and shared with other computer systems, and update to the control page are serialized across all of the computer systems.
35. The data structure of claim 34, wherein one or more attributes from the control page are stored in an in-memory data structure in the computer system.
36. The data structure of claim 35, wherein the in-memory data structure includes one or more attributes selected from a group of attributes comprising a sequence number (SN_MEM) and a \u201cnumber remaining\u201d value (N_REM).
37. The data structure of claim 36, wherein a value stored in N_REM indicates when a range of sequence numbers should be obtained from the control page.
38. The data structure of claim 35, wherein the control page is periodically saved to a data storage device, in order to effect a hardening of the control page.
39. The data structure of claim 35, wherein the sequence number is latched to serialized generation of the sequence number within the computer system.
40. The data structure of claim 35, wherein the control page is physically locked by a computer system to serialize updates to the control page across multiple computer systems.
41. The data structure of claim 40, wherein the physical lock is not maintained when the computer system fails, so that other computer systems are not prevented from continuing to generate new sequence numbers.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A fin semiconductor device, comprising:
a fin including a semiconductor layer formed on a substrate;
an insulating material layer formed over the substrate and surrounding the fin, the insulating material layer having a thickness less than the thickness of the semiconductor layer;
a source region portion and a drain region portion formed on the insulating material layer; and
a first channel control region, a second channel control region and a channel region between the source region portion and the drain region portion,
wherein the first channel control region is at a center of the semiconductor layer away from the edge and has a first conductivity type,
wherein the second channel control region is formed along an edge of the semiconductor layer in a portion of the semiconductor layer that is not covered by the insulating material layer, the second channel control region having the first conductivity type,
wherein the channel region is between the first channel control region and the second channel control region, adjoining the source region portion and the drain region portion, wherein the channel region, the source region portion and the drain region portion have a second conductivity type which is opposite to the first conductivity type.
2. The semiconductor device of claim 1 further comprising:
a gate for the fin, the gate adjoining the second channel control region, wherein the gate is formed on the insulating material layer.
3. The semiconductor device of claim 1, wherein the first channel control region has a lower portion and an upper portion extending from the lower portion, wherein the lower portion is below the upper surface of the insulating material layer.
4. The semiconductor device of claim 1, wherein the fin further comprises a hard mask on the semiconductor layer.
5. The semiconductor device of claim 1, wherein a ratio of the thickness T of the insulating material layer to the difference between the height Hsemi of the semiconductor layer and the thickness T, that is, T(Hsemi\u2212T), is about 3-5.
6. The semiconductor device of claim 1, wherein the second channel control region extends below the upper surface of the insulating material layer.
7. The semiconductor device of claim 1, wherein the substrate further has a region adjoining the first channel control region and having a conductivity type opposite to that of the channel region, so as to provide power for the first channel control region.
8. The semiconductor device of claim 1 further comprises:
gate spacers located on two sides of the gate that are adjacent to the source region portion and the drain region portion.
9. The semiconductor device of claim 1, further comprising two or more of the fins, wherein the two or more of the fins comprise a first fin and a second fin, and wherein the conductivity type of the channel region included in the first fin is the same as or opposite to the conductivity type of the channel region included in the second fin.
10. A method of manufacturing a semiconductor device, comprising:
providing a substrate with a fin formed thereon, wherein the fin has a semiconductor layer formed of a semiconductor material having a first conductivity type;
forming, over the substrate, a first insulating material layer surrounding the fin, wherein the first insulating material layer has a thickness less than the thickness of the semiconductor layer;
introducing, into an exposed surface of the semiconductor layer, a first dopant that can impart a second conductivity type which is opposite to the first conductivity type, such that a first region having the second conductivity type is formed at least in the exposed surface of the semiconductor layer in a portion of the fin that is not covered by the first insulating material layer, wherein, the portion of the semiconductor layer other than the first region serves as a second region, the second region having the first conductivity type;
forming a dummy gate for the fin to enclose a portion of the fin that corresponds to a channel region to be formed, wherein the dummy gate is formed above the first insulating material layer;
forming a second insulating material layer on the substrate to cover a portion of the fin other than the top surface of the dummy gate;
removing the dummy gate to expose a portion of the first region in the fin that is enclosed by the dummy gate; and
forming a third region having the first conductivity type in the first region by introducing into the first region a second dopant that can impart the first conductivity type,
wherein, the portion of the first region other than the third region is the channel region, the channel region separating the second region from the third region and having the second conductivity type, and
wherein, the second region is used for providing a first channel control region for controlling the channel region, and the third region functions as a second channel control region for controlling the channel region.
11. The method of claim 10, further comprising forming a hard mask on the semiconductor layer.
12. The method of claim 10 further comprising:
after forming the dummy gate but before forming the second insulating material layer, forming a spacer for the dummy gate,
wherein, the formed second insulating material layer also substantially covers the spacer.
13. The method of claim 12 further comprising:
after forming the spacer but before forming the second insulating material layer, implanting to form a source region portion and a drain region portion in the semiconductor layer that adjoin the channel region, the source region portion and the drain region portion has a conductivity type as same as that of the channel region,
wherein, the first channel control region in the second region is adjacent to said source region portion and the drain region portion and is between the source region and the drain region.
14. The method of claim 10 further comprising:
after introducing the second dopant, forming a gate for the fin, the gate adjoins the second channel control region from an outer side of the second channel control region, wherein the gate is formed above the first insulating material layer.
15. The method of claim 30 further comprising
after forming the gate, forming a spacer for the gate.
16. The method of claim 15 further comprising:
after forming the spacer, epitaxially growing a semiconductor material from the exposed surface of the semiconductor layer.
17. The method of claim 15 further comprising:
implanting to form a source region portion and a drain region portion in the semiconductor layer that adjoin the channel region, the source region portion and the drain region portion having a conductivity type that is the same as that of the channel region, and
wherein, the first channel control region in the second region is adjacent to the source region portion and the drain region portion and is between the source region portion and the drain region portion.
18. The method of claim 10, wherein a ratio of the thickness, T, of the insulating material layer to the difference between the height, Hsemi, of the semiconductor layer and the thickness T, that is, T(Hsemi\u2212T), is 3-5.
19. The method of claim 10, wherein the substrate has two or more of the fins formed thereon, wherein the two or more of the fins comprise a first fin and a second fin, and wherein the conductivity type of the channel region in the first fin is same as or opposite to the conductivity type of the channel region in the second fin.
20. The method of claim 19, wherein the conductivity type of the channel region of the first fin is opposite to the conductivity type of the channel region of the second fin, further comprising:
introducing the firstsecond dopant by:
covering the first fin with a first mask and exposing the second fin, introducing a corresponding dopant into the second fin;
removing the first mask; and
covering the second fin with a second mask and exposing the first fin, and introducing a corresponding dopant into the first fin.