1. A semiconductor memory device comprising:
n pairs, n being an integer of two or more, of bit lines;
m word lines, m being an integer of two or more;
n\xd7m memory cells provided at intersections of the n pairs of bit lines and the m word lines; and
a control circuit,
wherein
each of the n\xd7m memory cells includes
a first access transistor coupled between one of the pair of bit lines corresponding to the memory cell and a first memory node of the memory cell,
a second access transistor coupled between the other of the pair of bit lines corresponding to the memory cell and a second memory node of the memory cell,
a first load transistor and a second load transistor coupled between a power supply node of the memory cell to which a memory cell power supply voltage is applied, and the first and second memory nodes of the memory cell, respectively, and
a first drive transistor and a second drive transistor coupled between a ground node of the memory cell to which a memory cell ground voltage is applied, and the first and second memory nodes of the memory cell, respectively,
in each of the n\xd7m memory cells, the first and second access transistors each have a gate coupled to one of the m word lines which corresponds to the memory cell, the first load transistor and the first drive transistor each have a gate coupled to the second memory node of the memory cell, and the second load transistor and the second drive transistor each have a gate coupled to the first memory node of the memory cell, and
the control circuit supplies a word line drive voltage to one of the m word lines which corresponds to one or more of the n\xd7m memory cells to which data is to be written during a word line drive period including a first period and a second period following the first period, to decrease current capabilities of the first and second load transistors included in the memory cell during the first period, and increase the current capabilities of the first and second load transistors during the second period.
2. The semiconductor memory device of claim 1, wherein
the word line drive voltage is lower than a memory cell power supply voltage applied to one or more to which data is not to be written of some of the n\xd7m memory cells which correspond to one of the m word lines to which the word line drive voltage is supplied.
3. The semiconductor memory device of claim 1, wherein
the control circuit does not change the current capabilities of the first and second load transistors included in one or more of the n\xd7m memory cells to which data is not to be written and which corresponds to the same word line as that of one or more of the n\xd7m memory cells to which data is to be written, during the first and second periods.
4. The semiconductor memory device of claim 1, wherein
the control circuit decreases a memory cell power supply voltage applied to the power supply node of one or more of the n\xd7m memory cells to which data is to be written during the first period, and increases the memory cell power supply voltage during the second period.
5. The semiconductor memory device of claim 1, wherein
the control circuit increases a substrate voltage applied to substrates of the first and second load transistors included in one or more of the n\xd7m memory cells to which data is to be written during the first period, and decreases the substrate voltage during the second period.
6. The semiconductor memory device of claim 1, wherein
the control circuit decreases a memory cell ground voltage applied to the ground node of one or more of the n\xd7m memory cells to which data is to be written during the first period, and decreases the memory cell ground voltage during the second period.
7. The semiconductor memory device of claim 1, wherein
the control circuit sets the pair of bit lines corresponding to one or more of the n\xd7m memory cells to which data is to be written to have a potential corresponding to write data during the first period, and cancels the potential setting of the pair of bit lines during the second period.
8. The semiconductor memory device of claim 1, wherein
the control circuit sets the pair of bit lines corresponding to one or more of the n\xd7m memory cells to which data is to be written to have a potential corresponding to write data during the first and second periods, and cancels the potential setting of the pair of bit lines after the second period has elapsed.
9. The semiconductor memory device of claim 1, wherein
at least one of the first and second periods have a variable length.
10. The semiconductor memory device of claim 1, wherein
the first and second periods each have a length which is set, depending on a difference between the current capabilities of the first and second load transistors during the first period and the current capabilities of the first and second load transistors during the second period.
11. The semiconductor memory device of claim 1, wherein
the first and second periods each have a length which is set, depending on threshold voltages of the first and second load transistors.
12. A semiconductor memory device comprising:
a plurality of memory cells each including a flip-flop circuit; and
a control circuit configured to decrease a data holding capability of the flip-flop circuit included in one or more of the plurality of memory cells to which data is to be written during start of write operation, and increase the data holding capability of the flip-flop circuit during a predetermined period prior to the end of the write operation.
13. The semiconductor memory device of claim 12, further comprising:
a plurality of pairs of bit lines; and
a plurality of word lines,
wherein
the plurality of memory cells are arranged at intersections of the plurality of pairs of bit lines and the plurality of word lines,
each of the plurality of memory cells includes
a first access transistor coupled between one of the pair of bit lines corresponding to the memory cell and a first memory node of the flip-flop circuit, and having a gate coupled to one of the plurality of word lines corresponding to the memory cell, and
a second access transistor coupled between the other of the pair of bit lines corresponding to the memory cell and a second memory node of the flip-flop circuit, and having a gate coupled to one of the plurality of word lines corresponding to the memory cell, and
the control circuit activates one of the plurality of word lines corresponding to one or more of the plurality of memory cells to which data is to be written, to perform the write operation.
14. The semiconductor memory device of claim 13, wherein
the word line has a high-level potential which is lower than a memory cell power supply voltage applied to one or more of the plurality of memory cells which performs data holding operation during the write operation.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A compound of formula 1
in which
A is S, S(O) or S(O)2,
R1 is 1-4C-alkoxy or 1-4C-alkoxy which is completely or predominantly substituted by fluorine,
R2 is 1-4C-alkoxy or 1-4C-alkoxy which is completely or predominantly substituted by fluorine,
R3 is a phenyl radical which is substituted by R4 and R5, wherein
R4 is hydrogen, hydroxyl, halogen, nitro, 1-4C-alkyl, trifluoromethyl or 1-4C-alkoxy,
R5 is CO\u2014R6 or CO\u2014R7, wherein
R6 is hydroxyl, 1-8C-alkoxy, 3-7C-cycloalkoxy or 3-7C-cycloalkylmethoxy and
R7 is N(R71)R72, wherein R71 and R72 independently of one another are hydrogen, 1-7C-alkyl, 3-7C-cycloalkyl or 3-7C-cycloalkylmethyl, or wherein R71 and R72, together and including the nitrogen atom to which both are bonded, are a 1-pyrrolidinyl, 1-piperidyl, 1-hexahydroazepinyl or 4-morpholinyl radical,
or a salt thereof, an N-oxide thereof, or a salt of an N-oxide thereof.
2. A compound of formula 1 according to claim 1 in which
A is S or S(O),
R1 is 1-2C-alkoxy or 1-2C-alkoxy which is completely or predominantly substituted by fluorine,
R2 is 1-2C-alkoxy or 1-2C-alkoxy which is completely or predominantly substituted by fluorine,
R3 is a phenyl radical which is substituted by R4 and R5, wherein
R4 is hydrogen,
R5 is CO\u2014R6 or CO\u2014R7, wherein
R6 is hydroxyl, 1-8C-alkoxy, 3-7C-cycloalkoxy or 3-7C-cycloalkylmethoxy and
R7 is N(R71)R72, wherein R71 and R72 independently of one another are hydrogen, 1-7C-alkyl, 3-7C-cycloalkyl or 3-7C-cycloalkylmethyl, or wherein R71 and R72, together and including the nitrogen atom to which both are bonded, are a 1-pyrrolidinyl, 1-piperidyl, 1-hexahydroazepinyl or 4-morpholinyl radical,
or a salt thereof.
3. A compound of formula 1 according to claim 1 in which
A is S or S(O),
R1 is methoxy or ethoxy,
R2 is methoxy or ethoxy,
R3 is a phenyl radical which is substituted by R4 and R5, wherein
R4 is hydrogen,
R5 is CO\u2014R6 or CO\u2014R7, wherein
R6 is hydroxyl or 1-4C-alkoxy and
R7 is N(R71)R72, wherein R71 and R72 independently of one another are hydrogen or 1-4C-alkyl, or wherein R71 and R72, together and including the nitrogen atom to which both are bonded, are a 1-piperidyl, 1-hexahydroazepinyl or 4-morpholinyl radical,
or a salt thereof.
4. A compound of formula 1 according to claim 1 in which
A is S or S(O),
R1 is methoxy or ethoxy,
R2 is methoxy or ethoxy,
R3 is a phenyl radical which is substituted by R4 and R5, where
R4 is hydrogen,
R5 is CO\u2014R6 or CO\u2014R7, wherein
R6 is 1-2C-alkoxy and
R7 is N(R71)R72, wherein R71 and R72 independently of one another are 1-4C-alkyl,
or a salt thereof.
5. A compound of formula 1 according to claim 1 in which
A is S or S(O),
R1 is methoxy or ethoxy,
R2 is methoxy or ethoxy,
R3 is a phenyl radical which is substituted by R4 and R5, wherein
R4 is hydrogen,
R5 is CO\u2014R7, wherein
R7 is N(R71)R72, wherein R71 and R72 are isopropyl,
or a salt thereof.
6. A compound of formula 1 according to claim 1 in which
A is S(O)2,
R1 is 1-4C-alkoxy or 1-4C-alkoxy which is completely or predominantly substituted by fluorine,
R2 is 1-4C-alkoxy or 1-4C-alkoxy which is completely or predominantly substituted by fluorine,
R3 is a phenyl radical which is substituted by R4 and R5, where
R4 is hydrogen, hydroxyl, halogen, nitro, 1-4C-alkyl, trifluoromethyl or 1-4C-alkoxy,
R5 is CO\u2014R6 or CO\u2014R7, where
R6 is hydroxyl, 1-8C-alkoxy, 3-7C-cycloalkoxy or 3-7C-cycloalkylmethoxy and
R7 is N(R71)R72, where R71 and R72 independently of one another are hydrogen, 1-7C-alkyl, 3-7C-cycloalkyl or 3-7C-cycloalkylmethyl, or where R71 and R72, together and including the nitrogen atom to which both are bonded, are a 1-pyrrolidinyl, 1-piperidyl, 1-hexahydroazepinyl or 4-morpholinyl radical,
or a salt thereof, an N-oxide thereof, or a salt, of an N-oxide thereof.
7. A compound of formula 1 according to claim 1 in which
A is S(O)2,
R1 is 1-2C-alkoxy or 1-2C-alkoxy which is completely or predominantly substituted by fluorine,
R2 is 1-2C-alkoxy or 1-2C-alkoxy which is completely or predominantly substituted by fluorine,
R3 is a phenyl radical which is substituted by R4 and R5, where
R4 is hydrogen,
R5 is CO\u2014R6 or CO\u2014R7, where
R6 is hydroxyl, 1-8C-alkoxy, 3-7C-cycloalkoxy or 3-7C-cycloalkylmethoxy and
R7 is N(R71)R72, where R71 and R72 independently of one another are hydrogen, 1-7C-alkyl, 3-7C-cycloalkyl or 3-7C-cycloalkylmethyl, or where R71 and R72, together and including the nitrogen atom to which both are bonded, are a 1-pyrrolidinyl, 1-piperidyl, 1-hexahydroazepinyl or 4-morpholinyl radical,
or a salt thereof, an N-oxide thereof, or a salt, of an N-oxide thereof.
8. A compound of formula 1 according to claim 1 in which
A is S(O)2,
R1 is methoxy or ethoxy,
R2 is methoxy or ethoxy,
R3 is a phenyl radical which is substituted by R4 and R5, where
R4 is hydrogen,
R5 is CO\u2014R6 or CO\u2014R7, where
R6 is hydroxyl or 1-4C-alkoxy and
R7 is N(R71)R72, where R71 and R72 independently of one another are hydrogen or 1-4C-alkyl, or where R71 and R72, together and including the nitrogen atom to which both are bonded, are a 1-piperidyl, 1-hexahydroazepinyl or 4-morpholinyl radical,
or a salt thereof, an N-oxide thereof, or a salt, of an N-oxide thereof.
9. A compound of formula 1 according to claim 1 in which
A is S(O)2,
R1 is methoxy or ethoxy,
R2 is methoxy or ethoxy,
R3 is a phenyl radical which is substituted by R4 and R5, where
R4 is hydrogen,
R5 is CO\u2014R6 or CO\u2014R7, where
R6 is 1-2C-alkoxy and
R7 is N(R71)R72, where R71 and R72 independently of one another are 1-4C-alkyl,
or a salt thereof, an N-oxide thereof, or a salt, of an N-oxide thereof.
10. A compound of formula 1 according to claim 1 in which
A is S(O)2,
R1 is methoxy or ethoxy,
R2 is methoxy or ethoxy,
R3 is a phenyl radical which is substituted by R4 and R5, where
R4 is hydrogen,
R5 is CO\u2014R7, where
R7 is N(R71)R72, where R71 and R72 are isopropyl,
or a salt thereof.
11. A compound of formula 1 according to claim 1, in which the hydrogen atoms in positions 4a and 10a are in the cis position relative to one another, or a salt thereof, an N-oxide thereof, or a salt, of an N-oxide thereof.
12. A compound of formula 1 according to claim 2, in which the hydrogen atoms in positions 4a and 10a are in the cis position relative to one another, or a salt thereof.
13. A compound of formula 1 according to claim 1, which has with respect to the positions 4a and 10a the configuration shown in formula (1*):
or a salt thereof, an N-oxide thereof, or a salt, of an N-oxide thereof.
14. A compound of formula 1 according to claim 2, which has with respect to the positions 4a and 10a the configuration shown in formula (1*):
or a salt thereof.
15. A pharmaceutical composition comprising one or more compounds of formula 1 according to claim 1, or a pharmaceutically acceptable salt thereof, an N-oxide thereof, or a salt an N-oxide thereof, together with one or more pharmaceutical auxiliaries andor excipients.
16. A pharmaceutical composition comprising one or more compounds of formula 1 according to claim 2, or a pharmaceutically acceptable salt thereof together with one or more pharmaceutical auxiliaries andor excipients.