1. A method for manufacturing a semiconductor device, comprising the steps of:
(a) implanting boron (B) ions into a semiconductor substrate;
(b) implanting fluorine (F) or nitrogen (N) ions into said semiconductor device;
(c) after said steps (a) and (b) are performed, executing first annealing with a heating time of 100 msec or shorter relative to a region of said semiconductor substrate into which ions were implanted; and
(d) after said step (c) is performed, executing second annealing with a heating time longer than the heating time of said first annealing, relative to the region of said semiconductor substrate into which ions were implanted.
2. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of:
(e) before said steps (a) and (b), forming an insulated gate structure on a surface of said semiconductor substrate.
3. The method for manufacturing a semiconductor device according to claim 2, wherein:
said semiconductor substrate includes an n-type active region;
said step (e) forms said insulated gate structure on said n-type active region; and
said step (a) forms p-type extension regions of sourcedrain regions of a p-channel transistor in said n-type active region on both sides of said insulated gate structure.
4. The method for manufacturing a semiconductor device according to claim 3, further comprising the step of:
(f) after said step (e), implanting n-type impurity ions into said n-type active region deeper than said extension regions to form n-type pocket regions.
5. The method for manufacturing a semiconductor device according to claim 2, wherein:
said semiconductor substrate includes a p-type active region;
said step (e) forms said insulated gate structure on said p-type active region; and
said step (a) forms p-type pocket regions of an n-channel transistor in said p-type active region on both sides of said insulated gate structure.
6. The method for manufacturing a semiconductor device according to claim 1, wherein said steps (a) and (b) are executed at a same time by implanting BF or BF2 ions.
7. A method for manufacturing a semiconductor device comprising the steps of:
(a) implanting impurity ions into a semiconductor substrate;
(b) after said step (a) is performed, executing first annealing with a heating time of 100 msec or shorter relative to a region of said semiconductor substrate into which ions were implanted; and
(c) after said step (b) is performed, executing second annealing with a heating time longer than the heating time of said first annealing, relative to the region of said semiconductor substrate into which ions were implanted, before other annealing processes are executed.
8. A semiconductor device comprising:
a semiconductor substrate; and
a p-type region formed on said semiconductor substrate and containing boron (B) and fluorine (F) or nitrogen (N), wherein a B concentration rapidly lowers from a surface of said semiconductor substrate as a depth becomes deeper, then gradually lowers forming a kink, and a B concentration at a depth of the kink is 2\xd71020 cm\u22123 or higher.
9. The semiconductor device according to claim 8, wherein said semiconductor substrate includes an n-type active region; further comprising:
an insulated gate electrode formed on a surface of said n-type active region; and
wherein said p-type region is extension regions of sourcedrain regions formed on both sides of said insulated gate electrode.
10. The semiconductor device according to claim 9, further comprising:
n-type pocket regions covering said extension regions.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method, comprising:
attaching a partially processed CMOS wafer to a second wafer to produce a combined wafer, wherein the second wafer comprises a first region including a material different from silicon; and
forming devices in the first region or in a second region of the combined wafer having a material different from silicon.
2. The method of claim 1, wherein the partially processed CMOS wafer comprises a device layer including transistors.
3. The method of claim 2, wherein the device layer comprises silicon and the transistors are formed in a CMOS process.
4. The method of claim 1, wherein attaching the partially processed CMOS wafer to the second wafer comprises wafer bonding the partially processed CMOS wafer to the second wafer.
5. The method of claim 1, wherein the devices are formed in the second region, wherein the second wafer is a template wafer, and wherein the first region comprises a template material including a non group IV semiconductor material.
6. The method of claim 5, wherein the non group IV semiconductor material includes a group III-V semiconductor material.
7. The method of claim 6, wherein the group III-V semiconductor material comprises an AlInAs material.
8. The method of claim 1, further comprising receiving the partially processed CMOS wafer from a CMOS foundry.
9. The method of claim 1, wherein forming the devices comprises forming electronic andor optoelectronic devices.
10. The method of claim 1, wherein the second wafer is a template wafer, and wherein the first region comprises a template material, wherein the method further comprises:
forming the second region over the template material as a device layer, wherein the devices are formed in the device layer.
11. The method of claim 10, wherein the second region is formed after attaching the partially processed CMOS wafer to the second wafer.
12. The method of claim 10, wherein the second region includes a non group IV semiconductor material.
13. The method of claim 12, wherein the non group IV semiconductor material includes a group III-V semiconductor material.
14. The method of claim 13, wherein the group III-V semiconductor material comprises an InGaAs material andor an AlInGaAs material.
15. The method of claim 1, wherein the devices are formed in the first region.
16. The method of claim 15, wherein the devices are formed in the first region prior to attaching the partially processed CMOS wafer to the second wafer.
17. The method of claim 15, wherein the first region comprises a GaN material.
18. The method of claim 1, further comprising performing a portion of a CMOS process on the combined wafer after forming the devices.
19. The method of claim 18, wherein performing the portion of a CMOS process on the combined wafer comprises performing at least a portion of a back end CMOS process on the combined wafer.
20. The method of claim 1, further comprising forming the partially processed CMOS wafer in a front end CMOS process.
21. A method, comprising:
performing partial CMOS processing on a semiconductor wafer using a CMOS process to produce a partially processed CMOS wafer having transistors formed therein;
removing the partially processed CMOS wafer from the CMOS process;
receiving a combined wafer comprising at least a portion of the partially processed CMOS wafer having the transistors and a device region having a material different from silicon in which devices are formed; and
performing further CMOS processing on the combined wafer.
22. The method of claim 21, wherein the partially processed CMOS wafer comprises a silicon device layer in which the transistors are formed.
23. The method of claim 21, wherein the material different from silicon comprises a group III-V semiconductor material.