WHAT IS CLAIMED
1. A dielectric electronic component comprising:
a dielectric ceramic block;
a plurality of resonators arranged in a row in the dielectric ceramic block, each of said resonators comprising an internal conductor disposed on a wall surface of a through-hole formed in the dielectric ceramic block;
an external conductor disposed on a side surface of the dielectric ceramic block;
at least one terminal pad formed on the side surface of the dielectric ceramic block in spaced relation to the external conductor and coupled with a predetermined resonator of said plurality of resonators; and
an attenuation adjustment electrode provided on an end face of the dielectric ceramic block, said end face providing an open circuit end for said resonators, and said attenuation adjustment resonator being disposed in spaced relation to one end of said predetermined resonator, the attenuation adjustment electrode including a base conductor portion connected to and extending from the terminal pad and having an edge facing said end of said predetermined resonator, and at least one adjustment conductor portion projecting from the base conductor portion substantially laterally thereof.
2. A dielectric electronic component according to claim 1, wherein the attenuation adjustment electrode comprises first and second adjustment conductor portions projecting substantially laterally from the base conductor portion in opposite directions in such a manner that the first adjustment conductor portion extends toward a center part of said end face of the block, and the second adjustment conductor portion extends toward an outside part of said end face of the block.
3. A dielectric electronic component according to claim 1, wherein the predetermined resonator includes a circular extension conductor provided at said end of the predetermined resonator and connected thereto, and wherein the base conductor portion of the attenuation adjustment electrode has an arcuate edge concentric with said circular extension conductor.
4. A method for adjusting attenuation characteristics of a dielectric electronic component comprising a dielectric ceramic block; a plurality of resonators arranged in a row in the dielectric ceramic block, each of said resonators comprises an internal conductor disposed on a wall surface of a through-hole formed in the dielectric ceramic block; and an external conductor disposed on a side surface of the dielectric ceramic block; at least one terminal pad formed on the side surface of the dielectric ceramic block in spaced relation to the external conductor and coupled with a selected resonator of said plurality of resonators, said method comprising the steps of:
forming an attenuation adjustment electrode on an end face of the dielectric ceramic block that provides an open circuit end for the resonators in such a manner that the attenuation adjustment electrode is located in spaced relation to one end of the selected resonator, and comprises a base conductor portion extending from the terminal pad and having an edge that faces the end of the selected resonator, and at least one adjustment conductor portion projecting from the base conductor portion substantially laterally thereof; and
selectively removing part of the adjustment conductor portion of the attenuation adjustment electrode to thereby adjust attenuation characteristics of the dielectric electronic component.
5. A method according to claim 4 wherein the step of selectively removing part of said adjustment conductor portion comprises grinding away said part.
6. A method of adjusting attenuation characteristics of a dielectric electronic component according to claim 5, wherein
the forming step comprises forming first and second adjustment conductor portions projecting substantially laterally from the base conductor portion in opposite directions in such a manner that the first adjustment conductor portion extends toward a center part of said end face of the block, and the second adjustment conductor portion extends toward an outside part of said end face of the block; and
the grinding away step comprises grinding away at least part of the first adjustment conductor portion in order to shift an attenuation peak toward the lower frequency side, and grinding away at least part of the second adjustment conductor portion in order to shift the attenuation peak toward the higher frequency side.
7. A method of adjusting attenuation characteristics of a dielectric electronic component according to claim 4, wherein the selected resonator has a circular extension conductor connected to one end of the selected resonator; and the attenuation adjustment electrode is formed in such a manner that the base conductor portion of the attenuation adjustment electrode has an arcuate edge concentric with said circular extension conductor.
8. A dielectric duplexer comprising:
a dielectric ceramic block;
a plurality of resonators arranged in a row in the dielectric ceramic block, the resonators each comprising an internal conductor disposed on a wall surface of a through-hole formed in the dielectric ceramic block, and being divided into first and second groups such that said first group serves as a transmission section and said second group serves as a reception section;
an external conductor disposed on a side surface of the dielectric ceramic block;
an input terminal pad formed on said side surface of the dielectric ceramic block in spaced relation to the external conductor and so as to be coupled with the transmission section;
an output terminal pad formed on said side surface of the dielectric ceramic block in spaced relation to the external conductor and so as to be coupled with the reception section;
an antenna terminal pad formed on said side surface of the dielectric ceramic block in spaced relation to the external conductor and so as to be coupled with an innermost resonator-of the transmission section and an innermost resonator of the reception section; and
an attenuation adjustment electrode provided on an end face of the dielectric ceramic block, said end face providing an open circuit end for the resonators of the reception section, and attenuation adjustment electrode being disposed in spaced relation to one end of an outermost resonator of the reception section, the attenuation adjustment electrode including a base conductor portion extending from the output terminal pad and having an edge that faces said one end of the outermost resonator, and at least one adjustment conductor portion projecting from the base conductor portion substantially laterally thereof.
9. A dielectric duplexer according to claim 8, wherein the attenuation adjustment electrode comprises first and second adjustment conductor portions projecting substantially laterally from the base conductor portion in opposite directions in such a manner that the first adjustment conductor portion extends toward a center part of said end face of the block, and the second adjustment conductor portion extends toward an outside part of said end face of the block.
10. A dielectric duplexer according to claim 8, wherein the outermost resonator of the reception section includes a circular extension conductor provided at the one end of the outermost resonator and connected thereto and wherein the base conductor portion of the attenuation adjustment electrode has an arcuate edge concentric with said circular extension conductor.
11. A method of adjusting attenuation characteristics of a dielectric duplexer comprising a dielectric ceramic block; a plurality of resonators arranged in a row in the dielectric ceramic block, the resonators each comprising an internal conductor disposed on a wall surface of a through-hole formed in the dielectric ceramic block, and being divided into first and second groups such said first group serves as a transmission section and said second group serves as a reception section; an external conductor covering a side surface of the dielectric ceramic block; an input terminal pad disposed on said side surface of the dielectric ceramic block in spaced relation to the external conductor and so as to be coupled with the transmission section; an output terminal pad formed on said side surface of the dielectric ceramic block in spaced relation to the external conductor and so as to be coupled with the reception section; and an antenna terminal pad formed on said side surface of the dielectric ceramic block in spaced relation to the external conductor and so as to be coupled with an innermost resonator of the transmission section and an innermost resonator of the reception section, the method comprising the steps of:
forming an attenuation adjustment electrode on an end face of the dielectric ceramic block that provides an open circuit end for the resonators of the reception section in such a manner that the attenuation adjustment electrode is located in spaced relation to one end of an outermost resonator of the reception section, and has a base conductor portion extending from the output terminal pad and having an edge that faces the end of the outermost resonator, and at least one adjustment conductor portion projecting from the base conductor portion substantially laterally thereof; and
selectively removing the adjustment conductor portion of the attenuation adjustment electrode to thereby adjust attenuation characteristics of the dielectric duplexer.
12. A method according to claim 11 wherein the step of selectively removing part of said adjustment conductor portion comprises removing said part in a grinding step.
13. A method of adjusting attenuation characteristics of a dielectric duplexer according to claim 11, wherein
the forming step comprises forming first and second adjustment conductor portions projecting substantially laterally from the base conductor portion in opposite directions in such a manner that the first adjustment conductor portion extends toward a center part of said end face of the block, and the second adjustment conductor portion extends toward an outside part of said end face of the block; and
the grinding step comprises grinding away at least part of the first adjustment conductor portion in order to shift an attenuation peak toward the lower frequency side, and grinding away at least part of the second adjustment conductor portion in order to shift the attenuation peak toward the higher frequency side.
14. A method of adjusting attenuation characteristics of a dielectric duplexer according to claim 11, wherein the outermost resonator of the reception section has a circular extension conductor provided at one end of the outermost resonator and connected thereto; and the attenuation adjustment electrode is formed in such a manner that the base conductor portion of the attenuation adjustment electrode has an arcuate edge concentric with said circular extension conductor.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1-19. (canceled)
20. A dimming circuit for LEDs which obtains a DC voltage from an external AC power supply by using a TRIAC, an electronic transformer, and a rectifier bridge sequentially, comprising:
a first power stage circuit having an input terminal configured to receive said DC voltage;
a second power stage having an input terminal coupled to an output terminal of said first power stage and an output terminal coupled to an LED load;
a first control circuit configured to generate a first control signal in accordance with a first output voltage generated at said output terminal of said first power stage circuit, a first reference voltage and an upper threshold voltage to maintain an average value of said first output voltage to be consistent with said first reference voltage; and
a second control circuit configured to generate a dimming signal and control an operation of said second power stage circuit in accordance with said dimming signal to maintain an output current of said second power stage circuit to be consistent with an expected driving current represented by said dimming signal,
wherein said dimming circuit operates in one of a first operating mode and a second operating mode,
in said first operating mode, an input current of said first power stage circuit is maintained to be a first current which is no less than a holding current of said electronic transformer, when said first output voltage is in a continuously increasing state and is less than said upper threshold voltage, in a time period during which said TRIAC is turned on, in each half-sinusoidal wave period of said AC power supply, and said second control circuit generates said dimming signal in accordance with said first current,
in said second operating mode, said input current is maintained to be said first current when said first output voltage is in a continuously increasing state and is less than said upper threshold voltage, and said input current is maintained to a second current after said first output voltage reaches said upper threshold voltage and then decreases continuously, after said TRIAC is turned on, in each half-sinusoidal wave period of said AC power supply, and said second control circuit generates said dimming signal in accordance with said first current and said first output voltage.
21. The dimming circuit according to claim 20, wherein said first control circuit comprises:
a turn-on signal generating circuit comprising a clock signal generating circuit for generating a clock signal;
a turn-off signal generating circuit comprising a first voltage comparison circuit configured to compare said first output voltage with said upper threshold voltage to generate a first turn-off signal, and a feedback control circuit configured to receive said first output voltage, said first reference voltage and a ramp signal containing information of a peak value of inductor current, to generate a second turn-off signal; and
a first logic circuit coupled to said turn-on signal generating circuit and said turn-off signal generating circuit, to generate said first control signal for controlling a switching state of a first main power switch in said first power stage circuit.
22. The dimming circuit according to claim 21, wherein said feedback control circuit comprises:
a voltage error calculation circuit comprising an operating amplifier, a first input terminal of which receives said first output voltage and a second input terminal of which receives said first reference voltage, to generate a voltage error signal at an output terminal thereof;
a compensation circuit configured to receive said voltage error signal and to perform a compensation operation on said voltage error signal to obtain a compensation signal; and
a clamp circuit with a clamp voltage coupled to an output terminal of said compensation circuit, and said compensation signal being clamped to said clamp voltage when said compensation signal is less than said clamp voltage which is determined in accordance with said holding current of said electronic transformer; and
a square wave signal generating circuit comprising a comparator, a first input terminal of which receives said compensation signal, and a second input terminal of which receives said ramp signal, to generate a second turn-off signal at an output terminal thereof.
23. The dimming circuit according to claim 22, wherein said first logic circuit comprises:
a first OR-gate with two input terminals respectively coupled to said first voltage comparison circuit and said feedback control circuit to receive said first turn-off signal and said second turn-off signal,
a first RS trigger with a set terminal for receiving said clock signal, a reset terminal coupled to said output terminal of said OR-gate, and an output terminal for providing an output signal as said first control signal;
wherein said first main power switch is turned off until said TRIAC is turned on again, when said first output voltage is greater than said upper threshold voltage after said TRIAC is turned on, in each half-sinusoidal wave period of said AC power supply; and
wherein said first main power switch is turned on when said first output voltage is less than said upper threshold voltage and said clock signal is active, and is turned off when said ramp signal is greater than said compensation signal.
24. The dimming circuit according to claim 22, wherein said clamp circuit comprises:
a diode with a cathode coupled to said output terminal of said compensation circuit;
a clamping voltage source coupled to an anode of said diode.
25. The dimming circuit according to claim 20, wherein said second control circuit comprises:
a dimming signal generating circuit configured to generate said dimming signal in accordance with a duration of said first current, when said first output voltage is less than said upper threshold voltage, in a time period during which said TRIAC is turned on, in each half-sinusoidal wave period of said AC power supply, and to generate said dimming signal in accordance with a time period from a starting time point of said first current to a time point when said first output voltage reaches a lower threshold voltage, when said first output voltage is greater than said upper threshold voltage; and
an output current control circuit configured to generate a second control signal in accordance with an error between said output current of said second power stage circuit and said expected driving current, to control said second power stage circuit.
26. The dimming circuit according to claim 25, wherein said dimming signal generating circuit comprises:
a second voltage comparison circuit configured to compare said first output voltage with said lower threshold voltage;
an input current comparison circuit configured to compare said input current with a current threshold;
a second logic circuit comprising a second OR-gate which has two input terminals for receiving an output signal of said second voltage comparison circuit and an output signal of said input current comparison circuit, respectively, and an output terminal for providing a square wave signal; and
an averaging circuit configured to perform an averaging operation on said square wave signal and a reference voltage, to obtain said dimming signal.
27. The dimming circuit according to claim 25, wherein said output current control circuit is one selected from a group consisting of a peak current control circuit, an average current control circuit, and an a linear control circuit.
28. The dimming circuit according to claim 21, wherein said first voltage comparison circuit and said second voltage comparison circuit share a hysteresis comparator which provides an upper limit threshold voltage as said upper threshold voltage, and a lower limit threshold voltage as said lower threshold voltage.
29. The dimming circuit according to claim 20, wherein said second current has a value equal to zero.
30. The dimming circuit according to claim 20, wherein said first power stage circuit has a boost converter topology, and said second power stage circuit has a buck converter topology or a buck-boost converter topology.
31. A dimming method for LEDs, comprising:
receiving an external AC power supply;
generating a lack-phase DC voltage from said AC power supply by using a TRIAC, an electronic transformer and a rectifier bridge sequentially and by adjusting a conduction angle of said TRIAC;
providing said DC voltage to a first power stage circuit to enable said first power stage circuit after said TRIAC is triggered to be conducted in each half-sinusoidal wave period of said AC power supply;
comparing a first output voltage at said output terminal of said first power stage circuit with an upper threshold voltage;
controlling an operation of said first power stage circuit to maintain an input current to be consistent with a first current which is greater than a holding current of said electronic transformer when said first output voltage is in a continuously increasing state and is less than said upper threshold voltage, in a time period during which said TRIAC is turned on;
generating said dimming signal in accordance with said first current;
maintaining said input current to be said first current when said first output voltage is in a continuously increasing state and is less than said upper threshold voltage, and maintaining said input current to a second current after said first output voltage reaches said upper threshold voltage and then decreases continuously, in a time period during which said TRIAC is turned on;
generating said dimming signal in accordance with said first current and said first output voltage;
decreasing said first output voltage continuously and maintaining said input current to be consistent with a second current after said first output voltage reaches said upper threshold voltage;
receiving said first output voltage by a second power stage circuit;
generating a dimming signal in accordance with said first current and said first output voltage; and
controlling an operation of said second power stage circuit in accordance with said dimming signal and an output current of said second power stage circuit to maintain said output current to be consistent with an expected driving current represented by said dimming signal.
32. The dimming method for LEDs according to claim 31, wherein generating said dimming signal comprises:
comparing said first output voltage with said upper threshold voltage in each half-sinusoidal wave period of said AC power supply;
generating said dimming signal in accordance with a duration of said first current, when said first output voltage is less than said upper threshold voltage; and
generating said dimming signal in accordance with a time period from said starting time point of said first current to said time point when said first output voltage reaches a lower threshold voltage, when said first output voltage is greater than said upper threshold voltage.
33. The dimming method for LEDs according to claim 32, wherein generating said dimming signal comprises:
comparing said input current with a current threshold to generate a first square wave signal which is active when said input current is greater than said current threshold;
comparing said first output voltage with said lower threshold voltage to generate a second square wave signal which is active when said first output voltage is less than said upper threshold voltage and greater than said lower threshold voltage;
generating a square wave signal in accordance with said first square wave signal and said second square wave signal, wherein said square wave signal is active when said first square wave signal or said second square wave signal is active; and
performing an averaging operation on said square wave signal to generate said dimming signal.
34. The dimming method for LEDs according to claim 31, wherein controlling said output current of said second power stage circuit comprises:
controlling a switching state of a power switch in said second power stage circuit in accordance with an error between said output current and said expected driving current to maintain said output current of said second power stage circuit to be consistent with said expected driving current.
35. The dimming method for LEDs according to claim 31, wherein controlling said first power stage circuit comprises:
comparing said first output voltage with said upper threshold voltage;
controlling a switching state of a first main power switch of said first power stage circuit by using a peak current controlling method when said first output voltage is less than said upper threshold voltage; and
turning off said first main power switch when said first output voltage is greater than said upper threshold voltage.
36. The dimming method for LEDs according to claim 35, wherein said peak current controlling method comprises:
generating an error signal based on an error between said first output voltage and a first reference voltage;
generating a compensation signal by a compensation operation on said error signal;
comparing said compensation signal with a clamp signal which is determined by said holding current;
maintaining said compensation signal when said compensation signal is greater than said clamp signal;
clamping said compensation signal to said clamp signal when said compensation signal is less than said clamp signal;
comparing said compensation signal with a ramp signal which represents a peak value of inductor current of said first power stage circuit;
turning on said first main power switch when a clock signal is active and said ramp signal is less than said compensation signal so that both said input current and said first output voltage increases continuously; and
turning off said first main power switch when said ramp signal is greater than said compensation signal so that said input current decreases until said clock signal becomes active again.
37. The dimming method for LEDs according to claim 31, wherein said second current has a value equal to zero.
38. The dimming method for LEDs according to claim 31, wherein said first power stage circuit has a boost converter topology, and said second power stage circuit has a buck converter topology or a buck-boost converter topology.