1. A projector comprising:
a light source section that outputs light;
a first light modulation section that modulates first color component light out of the light outputted from the light source section based on a first image signal;
a second light modulation section that modulates second color component light out of the light outputted from the light source section based on a second image signal;
a projection section that projects a first image corresponding to the light modulated by the first light modulation section and a second image corresponding to the light modulated by the second light modulation section;
a display control section that superimposes the first image and the second image on each other and projects a superimposed image to show position misregistration of the second image relative to the first image;
an accepting section that accepts shift instruction to shift the second image relative to the first image; and
an alignment adjustment section that determines correction information for correcting the position misregistration based on the shift instruction accepted by the accepting section and corrects the second image signal based on the determined correction information,
wherein the accepting section accepts the shift instruction via a first instruction input screen for shifting the second image as a whole and a second instruction input screen for shifting a predetermined portion of the second image.
2. The projector according to claim 1,
wherein the accepting section accepts the shift instruction issued via the first instruction input screen before the shift instruction issued via the second instruction input screen.
3. The projector according to claim 1,
wherein when the accepting section accepts the shift instruction via the first instruction input screen, the alignment adjustment section shifts the second image by the same amount of shift in accordance with the shift instruction or offsets data on the second image in accordance with the shift instruction and reads the offset data.
4. The projector according to claim 1,
wherein the second instruction input screen accepts at least one of the shift instruction to shift a plurality of end portions of the second image and the shift instruction to shift an arbitrary portion of the second image.
5. A method for adjusting a projector including a light source section, a first light modulation section that modulates first color component light out of light outputted from the light source section based on a first image signal, a second light modulation section that modulates second color component light out of the light outputted from the light source section based on a second image signal, and a projection section that projects a first image corresponding to the light modulated by the first light modulation section and a second image corresponding to the light modulated by the second light modulation section, the method comprising:
superimposing the first image and the second image on each other and projecting a superimposed image to show position misregistration of the second image relative to the first image;
accepting shift instruction via a first instruction input screen for shifting the second image as a whole relative to the first image;
accepting the shift instruction via a second instruction input screen for shifting a predetermined portion of the second image; and
determining correction information for correcting the position misregistration based on the shift instruction and storing the determined correction information.
6. The method for adjusting a projector according to claim 5,
wherein the accepting of the shift instruction via the first instruction input screen is executed the accepting of the shift instruction via the second instruction input screen.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for manufacturing a Power Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) comprising:
implanting a base region of said Power MOSFET within an epitaxial layer of a semiconductor chip comprising an insulated gate structure,
implanting a source link region on one side of the gate through a first mask, wherein the first mask is partially formed by an edge of the gate, said source link extending from a surface into the epitaxial layer and having a width defined by said first window,
subsequently forming a spacer extending from the edge of said gate which defines said first window and forming a second mask which is partially formed by said spacer, and
implanting a source region through said second mask.
2. The method according to claim 1, wherein the first and second mask are dimensioned such that the source link extends from about the edge of the gate to the edge of the source region.
3. The method according to claim 1, wherein the first and second mask are dimensioned such that the source link extends from about the edge of the gate into the source region.
4. The method according to claim 1, wherein the variables of the implanting of the source link are dimensioned to define a breakdown voltage of said Power MOSFET.
5. The method according to claim 1, wherein the variables of the implanting of the source link are dimensioned to define an on-resistance of said Power MOSFET.
6. The method according to claim 1, wherein the MOSFET is formed within a single manufacturing process for forming a plurality of integrated devices and said MOSFET in the semiconductor chip.
7. The method according to claim 6, wherein the plurality of devices form a microcontroller controlling said MOSFET.
8. The method according to claim 6, wherein the plurality of devices form a pulse width modulator controlling said MOSFET.
9. The method according to claim 6, wherein at least two MOSFETs are formed during said manufacturing process and a drain of a first MOSFET is connected to a source of a second MOSFET.
10. The method according to claim 6, wherein a plurality of MOSFETs are formed during said manufacturing process and said plurality of MOSFETs are interconnected to form an H-bridge.
11. The method according to claim 1, wherein the base MOSFET is formed within an area defined by surrounding field oxide.
12. The method according to claim 11, further comprising the step of forming a buried layer prior to the implanting step.
13. The method according to claim 1, further comprising forming a drain region on the other side of the gate extending from a top surface into the epitaxial layer.
14. The method according to claim 13, further comprising forming a plurality of transistor cells within said epitaxial layer and forming metal layers to interconnect said gates, drain and source regions of said plurality of transistor cells.
15. A Power Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) comprising:
a base region of said Power MOSFET implanted within an epitaxial layer of a semiconductor chip comprising an insulated gate structure,
a source link region implanted on one side of the gate through a first mask, wherein the first mask is partially formed by an edge of the gate, said source link extending from a surface into the epitaxial layer and having a width defined by said first window,
a spacer extending from the edge of said gate which defines said first window and forming a second mask which is partially formed by said spacer, and
a source region implanted through said second mask.
16. The Power Metal-Oxide-Semiconductor Field-Effect-Transistor according to claim 15, wherein the first and second mask are dimensioned such that the source link extends from about the edge of the gate to the edge of the source region.
17. The Power Metal-Oxide-Semiconductor Field-Effect-Transistor according to claim 15, wherein the first and second mask are dimensioned such that the source link extends from about the edge of the gate into the source region.
18. The Power Metal-Oxide-Semiconductor Field-Effect-Transistor according to claim 15, wherein the variables of the implanting of the source link are dimensioned to define a breakdown voltage of said Power MOSFET.
19. The Power Metal-Oxide-Semiconductor Field-Effect-Transistor according to claim 15, wherein the variables of the implanting of the source link are dimensioned to define an on-resistance of said Power MOSFET.
20. The Power Metal-Oxide-Semiconductor Field-Effect-Transistor according to claim 15, wherein the MOSFET is formed within a single manufacturing process for forming a plurality of integrated devices and said MOSFET in the semiconductor chip.
21. The Power Metal-Oxide-Semiconductor Field-Effect-Transistor according to claim 20, wherein the plurality of devices form a microcontroller controlling said MOSFET.
22. The Power Metal-Oxide-Semiconductor Field-Effect-Transistor according to claim 20, wherein the plurality of devices form a pulse width modulator controlling said MOSFET.
23. The Power Metal-Oxide-Semiconductor Field-Effect-Transistor according to claim 20, wherein at least two MOSFETs are formed during said manufacturing process and a drain of a first MOSFET is connected to a source of a second MOSFET.
24. The Power Metal-Oxide-Semiconductor Field-Effect-Transistor according to claim 20, wherein a plurality of MOSFETs are formed during said manufacturing process and said plurality of MOSFETs are interconnected to form an H-bridge.
25. The Power Metal-Oxide-Semiconductor Field-Effect-Transistor according to claim 15, wherein the base MOSFET is formed within an area defined by surrounding field oxide.
26. The Power Metal-Oxide-Semiconductor Field-Effect-Transistor according to claim 25, further comprising a buried layer.
27. The Power Metal-Oxide-Semiconductor Field-Effect-Transistor according to claim 15, further comprising a drain region on the other side of the gate extending from a top surface into the epitaxial layer.
28. The Power Metal-Oxide-Semiconductor Field-Effect-Transistor according to claim 27, further comprising a plurality of transistor cells within said epitaxial layer and metal layers to interconnect said gates, drain and source regions of said plurality of transistor cells.