1. A device comprising:
an output circuit including a plurality of unit buffers, each of the unit buffers having an adjustable impedance;
a controller circuit operable to selectively activate at least one of the unit buffers; and
an impedance adjustment part operable to adjust the impedance of each of the unit buffers in response to a change of the number of the unit buffers that are selectively activated by the controller circuit; and
a first terminal configured to be coupled to an external resistor, and wherein the impedance adjustment part includes:
an impedance adjustment circuit operable to generate a first impedance adjustment signal in response to a resistance of the external resistor; and
a correction circuit receiving the first impedance adjustment signal and operable to perform a correction for the first impedance adjustment signal to generate a second impedance adjustment signal, the correction corresponding to the number of the unit buffers that are selectively activated by the controller circuit, and supplying the second impedance adjustment signal to the unit buffers to adjust the impedance of each of the unit buffers.
2. The device as recited in claim 1, wherein the correction circuit comprises:
a first correction value memory part operable to store a plurality of preset correction values,
a selection circuit operable to select one of the preset correction values in response to the number of the unit buffers that are selectively activated by the controller circuit, and
an addition circuit operable to add the one of the preset correction values to the first impedance adjustment signal to generate the second impedance adjustment signal.
3. The device as recited in claim 2, further comprising:
a mode register operable to store data indicative of the number of the unit buffers, and
wherein the first correction value memory part includes a plurality of second correction value memory parts, each of the second correction value memory parts storing an associated one of the preset correction values,
the mode register is operable to output a setting signal in response to the data indicative of the number of the unit buffers, and
the selection circuit is operable to select one of the second correction value memory parts in response to the setting signal when the setting signal is inputted to the selection circuit.
4. The device as recited in claim 3, further comprising:
an output terminal,
wherein each of the unit buffers includes;
a pull-up circuit operable to drive the output terminal into a first power supply voltage level, and
a pull-down circuit operable to drive the output terminal into a second power supply voltage level,
the setting signal includes a first setting signal and a second setting signal, and
the controller circuit is operable to
activate one of the pull-up circuit and the pull-down circuit depending upon the first setting signal so as to drive the output terminal when a read command is inputted to the device, the read command performing an operation of reading data stored within the device and outputting the data to the output terminal, and
activate both of the pull-up circuits and the pull-down circuits depending upon the second setting signal so as to drive a second terminal when an on-die termination signal is inputted to the device, the on-die termination signal instructing the output circuit to function as a terminating resistor.
5. The device as recited in claim 2, wherein the first correction value memory part includes a nonvolatile memory element, and
the preset correction values are written into the nonvolatile memory element when a test command is supplied externally to the device.
6. The device as recited in claim 1, further comprising an output terminal, and wherein the unit buffers are coupled in common to the output terminal.
7. The device as recited in claim 1, wherein the controller circuit is operable to activate a first number of the unit buffers in a first operation mode and activate a second number of the unit buffers in a second operation mode.
8. The device as recited in claim 7, wherein the first number is different from the second number.
9. The device as recited in claim 7, wherein the first operation mode is a data output mode and the second operation mode is an ODT mode.
10. A data processing system comprising;
a controller unit; and
a memory device coupled to the controller unit, the memory device comprising;
an output circuit including a plurality of unit buffers, each of the unit buffers having an adjustable impedance;
a controller circuit operable to selectively activate at least one of the unit buffers;
an impedance adjustment part operable to adjust the impedance of each of the unit buffers in response to a change of the number of the unit buffers that are selectively activated by the controller circuit
an external resistor; and
a first terminal coupled to the external resistor, wherein the impedance adjustment part includes:
an impedance adjustment circuit operable to generate a first impedance adjustment signal in response to a resistance of the external resistor; and
a correction circuit receiving the first impedance adjustment signal and operable to perform a correction for the first impedance adjustment signal to generate a second impedance adjustment signal, the correction corresponding to the number of the unit buffers that are selectively activated by the controller circuit, and supplying the second impedance adjustment signal to the unit buffers to adjust the impedance of each of the unit buffers.
11. The data processing system as recited in claim 10, wherein the correction circuit comprises:
a first correction value memory part operable to store a plurality of preset correction values,
a selection circuit operable to select one of the preset correction values in response to the number of the unit buffers that are selectively activated by the controller circuit, and
an addition circuit operable to add the one of the preset correction values to the first impedance adjustment signal to generate the second impedance adjustment signal.
12. The data processing system as recited in claim 11, wherein the memory device further comprises:
a mode register operable to store data indicative of the number of the unit buffers, and
wherein the first correction value memory part includes a plurality of second correction value memory parts, each of the second correction value memory parts storing an associated one of the preset correction values,
the mode register is operable to output a setting signal in response to the data indicative of the number of the unit buffers, and
the selection circuit is operable to select one of the second correction value memory parts in response to the setting signal when the setting signal is inputted to the selection circuit.
13. The data processing system as recited in claim 12, wherein the memory device further comprises:
an output terminal,
wherein each of the unit buffers includes;
a pull-up circuit operable to drive the output terminal into a first power supply voltage level, and
a pull-down circuit operable to drive the output terminal into a second power supply voltage level,
the setting signal includes a first setting signal and a second setting signal, and
the controller circuit is operable to:
activate one of the pull-up circuit and the pull-down circuit depending upon the first setting signal so as to drive a output terminal when a read command is inputted to the device, the read command performing an operation of reading data stored within the device and outputting the data to the output terminal, and
activate both of the pull-up circuits and the pull-down circuits depending upon the second setting signal so as to drive a second terminal when an on-die termination signal is inputted to the device, the on-die termination signal instructing the output circuit to function as a terminating resistor.
14. The system as recited in claim 11, wherein the first correction value memory part includes a nonvolatile memory element, and
the preset correction values are written into the nonvolatile memory element when a test command is supplied externally to the device.
15. The system as recited in claim 10, wherein the memory device further comprises an output terminal, and wherein the unit buffers are coupled in common to the output terminal.
16. The system as recited in claim 10, wherein the controller circuit is operable to activate a first number of the unit buffers in a first operation mode and activate a second number of the unit buffers in a second operation mode.
17. The system as recited in claim 16, wherein the first number is different from the second number.
18. The system as recited in claim 16, wherein the first operation mode is a data output mode and the second operation mode is an ODT mode.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An operational amplifier comprising:
a differential amplifier for differentially amplifying first and second differential input signals to generate first and second output signals through first and second nodes;
a driver for driving an output node in response to the second output signal; and
a drive current adjuster for adjusting a driving current of the driver in response to the first output signal, wherein
the drive current adjuster comprises:
a first transistor including a drain connected to the output node, a gate, and a source connected to a ground voltage;
a second transistor including a gate connected to the first node, a drain, and a source connected to a source voltage;
a third transistor including a drain connected to the drain of the second transistor, a source, and a gate connected to a first bias voltage; and
a fourth transistor including a drain connected to the source of the third transistor, a source connected to the ground voltage, and a gate connected to a second bias voltage,
wherein the gate of the first transistor is commonly connected to the drains of the second and third transistors.
2. The operational amplifier of claim 1, wherein the driver comprises:
a current source transistor controlled by the second output signal to charge the output node; and
a current sink transistor controlled by the second bias voltage to discharge the output node.
3. The operational amplifier of claim 2, wherein the current source transistor is a PMOS transistor including a source connected to the source voltage, a drain connected to the output node, and a gate connected to the first output signal.
4. The operational amplifier of claim 2, wherein the current sink transistor is a NMOS transistor including a drain connected to the output node, a source connected to the ground voltage, and a gate connected to the second bias voltage.
5. The operational amplifier of claim 1, wherein the differential amplifier comprises:
a first NMOS transistor including a drain connected to the first node, a source, and a gate connected to the first differential input signal;
a second NMOS transistor including a drain connected to the second node, a source connected to the source of the first NMOS transistor, and a gate connected to the second differential input signal;
a first PMOS transistor including a source connected to the source voltage, a drain connected to the first node, and a gate connected to the first node;
a second PMOS transistor including a source connected to the source voltage, a drain connected to the second node, and a gate connected to the first node;
a first bias transistor including a drain connected to the sources of the first and second transistors, a source, and a gate connected to the first bias voltage; and
a second bias transistor including a drain connected to the source of the first bias transistor, a source connected to the ground voltage, and a gate connected to the second bias voltage.
6. A signal processing circuit comprising:
a digital-to-analog converter for converting a digital video signal into an analog video signal; and
an output buffer for amplifying the analog video signal and providing the amplified analog video signal to a display panel, wherein
the output buffer comprises:
a differential amplifier for differentially amplifying first and second differential input signals to generate first and second output signals through first and second nodes;
a driver for driving an output node in response to the second output signal; and
a drive current adjuster for adjusting a driving current of the driver in response to the first output signal, wherein
the drive current adjuster comprises:
a first transistor including a drain connected to the output node, a gate, and a source connected to a ground voltage;
a second transistor including a gate connected to the first node, a drain, and a source connected to a source voltage;
a third transistor including a drain connected to the drain of the second transistor, a source, and a gate connected to a first bias voltage; and
a fourth transistor including a drain connected to the source of the third transistor, a source connected to the ground voltage, and a gate connected to a second bias voltage,
wherein the gate of the first transistor is commonly connected to the drains of the second and third transistors.
7. The signal processing circuit of claim 6, further comprising a source drive integrated circuit.
8. A differential amplifier for differentially amplifying first and second differential input signals to generate first and second output signals through first and second nodes, the differential amplifier comprising:
a first NMOS transistor including a drain connected to the first node, a source, and a gate connected to the first differential input signal;
a second NMOS transistor including a drain connected to the second node, a source connected to the source of the first NMOS transistor, and a gate connected to the second differential input signal;
a first PMOS transistor including a source connected to a source voltage, a drain connected to the first node, and a gate connected to the first node;
a second PMOS transistor including a source connected to the source voltage, a drain connected to the second node, and a gate connected to the first node;
a first bias transistor including a drain connected to the sources of the first and second transistors, a source, and a gate connected to the first bias voltage;
a second bias transistor including a drain connected to the source of the first bias transistor, a source connected to the ground voltage, and a gate connected to the second bias voltage;
a driver for driving an output node in response to the second output signal; and
a drive current adjuster for adjusting a driving current of the driver in response to the first output signal.
9. The differential amplifier of claim 8, wherein the driver comprises:
a current source transistor controlled by the second output signal to charge the output node; and
a current sink transistor controlled by the second bias voltage to discharge the output node.
10. The differential amplifier of claim 9, wherein the current source transistor is a PMOS transistor including a source connected to the source voltage, a drain connected to the output node, and a gate connected to the first output signal.
11. The differential amplifier of claim 9, wherein the current sink transistor is a NMOS transistor including a drain connected to the output node, a source connected to the ground voltage, and a gate connected to the second bias voltage.
12. The differential amplifier of claim 8, wherein the drive current adjuster comprises:
a first transistor including a drain connected to the output node, a gate, and a source connected to a ground voltage;
a second transistor including a gate connected to the firs node, a drain, and a source connected to a source voltage;
a third transistor including a drain connected to the drain of the second transistor, a source, and a gate connected to a first bias voltage; and
a fourth transistor including a drain connected to the source of the third transistor, a source connected to the ground voltage, and a gate connected to a second bias voltage,
wherein the gate of the first transistor is commonly connected to the drains of the second and third transistors.