1.-30. (canceled)
31. A transmitter, comprising:
a first digital processing branch configured to process an in-phase component of a digital input signal to provide a processed in-phase signal;
a second digital processing branch configured to process a quadrature phase component of the digital input signal to provide a processed quadrature phase signal;
a compressive nonlinearity module configured to amplitude compress the processed in-phase signal and the processed quadrature phase signal to provide an amplitude compressed in-phase signal and an amplitude compressed quadrature phase signal, respectively,
a first analog processing branch configured to process the amplitude compressed in-phase signal to provide a processed amplitude compressed in-phase signal;
a second analog processing branch configured to process the amplitude compressed quadrature phase signal to provide a processed amplitude compressed quadrature phase signal;
a upconverter module configured to frequency translate the amplitude compressed in-phase signal and the amplitude compressed quadrature phase signal to provide a frequency translated baseband signal; and
an amplifier, having a rated power level, configured to amplify the frequency translated baseband signal to a power level that is greater than the rated power level.
32. The transmitter of claim 31, wherein the first digital processing branch comprises:
a first upsampler configured to upsample the in-phase component to provide an upsampled in-phase signal; and
a digital low pass filter configured to filter the upsampled in-phase signal to provide the processed in-phase signal, and
wherein the second digital processing branch comprises:
a second upsampler configured to upsample the quadrature phase component to provide an upsampled quadrature phase signal; and
a second digital low pass filter configured to filter the upsampled quadrature phase signal to provide the processed quadrature phase signal.
33. The transmitter of claim 31, wherein the first analog processing branch comprises:
a first digital to analog converter configured to convert the amplitude compressed in-phase signal from a digital domain to an analog domain to provide an analog amplitude compressed in-phase signal;
a first analog low pass filter configured to filter the analog amplitude compressed in-phase signal to provide the processed amplitude compressed in-phase signal, and
wherein the second analog processing branch comprises:
a second digital to analog converter configured to convert the amplitude compressed quadrature phase signal from the digital domain to the analog domain to provide an analog amplitude compressed quadrature phase signal;
a second analog low pass filter configured to filter the analog amplitude compressed quadrature phase signal to provide the processed amplitude compressed quadrature phase signal.
34. The transmitter of claim 31, wherein the compressive nonlinearity module is further configured to amplitude compress the processed in-phase signal and the processed quadrature phase signal using a first and a second compressive nonlinearity function, respectively.
35. The transmitter of claim 34, wherein compressions of the first and the second compressive nonlinearity functions increase with an amplitude of the processed in-phase signal and an amplitude of the processed quadrature phase signal, respectively.
36. The transmitter of claim 34, wherein the first and the second compressive nonlinearity functions are configured to enable compliance with a spectral mask as measured at an output of the amplifier.
37. The transmitter of claim 34, wherein the first and the second compressive nonlinearity functions are configured to substantially preserve an angle of the in-phase and quadrature phase components.
38. A transmitter, comprising:
an inverse Fast-Fourier transform (IFFT) module configured to implement an IFFT on symbol data to provide a time-domain representation of the symbol data;
a compressive nonlinearity module configured to provide an amplitude compressed time-domain representation in response to the time-domain representation;
an amplifier configured to provide an amplified output having a power level that is greater than a rated power level of the amplifier module in response to the amplitude compressed time-domain representation.
39. The transmitter of claim 38, wherein the compressive nonlinearity module is further configured to amplitude compress its input using a compressive nonlinearity function.
40. The transmitter of claim 39, wherein compression of the compressive nonlinearity function increases with an amplitude of its input.
41. The transmitter of claim 39, wherein the compressive nonlinearity function is configured to enable compliance with a spectral mask as measured at an output of the amplifier.
42. The transmitter of claim 38, further comprising:
an upsampler configured to upsample the time-domain representation to provide an unsampled time-domain representation; and
a digital low pass filter configured to filter the upsampled time-domain representation to provide a filtered time-domain representation,
wherein the compressive nonlinearity module is further configured to amplitude compress the filtered time-domain representation to provide the amplitude compressed time-domain representation.
43. The transmitter of claim 38, further comprising:
a digital to analog converter configured to convert the amplitude compressed time-domain representation from a digital domain to an analog domain to provide an analog amplitude compressed time-domain representation;
an analog low pass filter configured to filter the analog amplitude compressed time-domain representation to provide a filtered amplitude compressed time-domain representation; and
an upconverter module configured to frequency translate the filtered amplitude compressed time-domain representation to provide a frequency translated amplitude compressed time-domain representation,
wherein the amplifier is configured to amplify the frequency translated amplitude compressed time-domain representation to provide the amplified output.
44. A transmitter, comprising:
a compressive nonlinearity module configured to amplitude compress a time-domain representation of symbol data in a time-domain using a compressive nonlinearity function to provide an amplitude compressed time-domain representation; and
an amplifier configured to provide an amplified output having a power level that is greater than a rated power level of the amplifier module in response to the amplitude compressed time-domain representation.
45. The transmitter of claim 44, wherein compression of the compressive nonlinearity function increases with an amplitude of the time-domain representation of the symbol data.
46. The transmitter of claim 44, wherein the compressive nonlinearity function is configured to enable compliance with a spectral mask as measured at an output of the amplifier.
47. The transmitter of claim 44, wherein the symbol data is Orthogonal Frequency Division Multiplexed (OFDM) symbol data.
48. The transmitter of claim 47, further comprising:
an inverse Fast-Fourier transform (IFFT) module configured to implement an IFFT on the OFDM symbol data to provide a time-domain representation of the OFDM symbol data;
a digital processing branch configured to process the time-domain representation to provide a processed time-domain representation;
wherein the compressive nonlinearity module is further configured to amplitude compress the processed time-domain representation.
49. The transmitter of claim 48, wherein the digital processing branch comprises:
an upsampler configured to upsample the time-domain representation to provide an upsampled time-domain representation; and
a digital low pass filter configured to filter the upsampled time-domain representation to provide the processed time-domain representation.
50. The transmitter of claim 47, further comprising:
an analog processing branch configured to process an output of the compressive nonlinearity module to provide an analog processed time-domain representation;
an upconverter module configured to frequency translate the analog processed time-domain representation to provide a frequency translated time-domain representation,
wherein the amplifier is configured to amplify the frequency translated time-domain representation to provide the amplified output.
51. The transmitter of claim 50, wherein the analog processing branch comprises:
a digital to analog converter configured to convert the output of the compressive nonlinearity module from a digital domain to an analog domain to provide an analog amplitude compressed time-domain representation; and
an analog low pass filter configured to filter the analog amplitude compressed time-domain representation to provide the analog processed time-domain representation.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A programmable logic device comprising:
a plurality of logic blocks;
a plurality of inputoutput blocks;
a volatile memory block adapted to store user data within the programmable logic device, but which is not adapted to configure the logic blocks and the inputoutput blocks;
configuration memory adapted to store first configuration data for configuration of the logic blocks, the inputoutput blocks, and the volatile memory block of the programmable logic device; and
a non-volatile memory adapted to store the user data provided from the volatile memory block and further adapted to store configuration data for transfer to the configuration memory, the non-volatile memory being partitioned to provide a configuration portion to store configuration data for transfer to the configuration memory and a user portion to store the user data for the volatile memory block,
wherein the volatile memory block and the configuration memory are distinct and separate from each other and located in different portions of the programmable logic device.
2. The programmable logic device of claim 1, wherein the volatile memory block includes embedded block RAM.
3. The programmable logic device of claim 1, further comprising control logic adapted to control transfer of the user data from the volatile memory block to the non-volatile memory and from the non-volatile memory to the volatile memory block.
4. The programmable logic device of claim 1, further comprising a non-volatile memory controller adapted to control transfer of the user data from the volatile memory block to the non-volatile memory and from the non-volatile memory to the volatile memory block.
5. The programmable logic device of claim 1, wherein the non-volatile memory is further partitioned to provide at least one of a trim portion, a test portion, and a tag portion.
6. The programmable logic device of claim 1, wherein the configuration portion and the user portion each has a different starting address.
7. The programmable logic device of claim 1, further comprising at least a first data port adapted to receive commands for controlling reconfiguration of the programmable logic device.
8. The programmable logic device of claim 1, wherein the volatile memory block is further adapted to function as virtual flash memory, wherein at least one of the configuration memory is associated with the volatile memory block and provides a control signal to control whether the volatile memory block transfers its user data to the non-volatile memory.
9. The programmable logic device of claim 1, wherein the non-volatile memory is flash memory partitioned into a configuration flash portion and a user flash portion.
10. A programmable logic device comprising:
a plurality of logic blocks;
a plurality of inputoutput blocks;
a volatile memory block adapted to store user data within the programmable logic device, but which is not adapted to configure the logic blocks and the inputoutput blocks;
configuration memory adapted to store first configuration data for configuration of the logic blocks, the inputoutput blocks, and the volatile memory block of the programmable logic device; and
non-volatile memory partitioned to provide a configuration portion to store configuration data for transfer to the configuration memory and a user portion to store the user data for the volatile memory block,
wherein the volatile memory block and the configuration memory are distinct and separate from each other and located in different portions of the programmable logic device, and the volatile memory block is further adapted to function as virtual flash memory, with the non-volatile memory accessed via the volatile memory block.
11. A programmable logic device comprising:
a plurality of logic blocks;
a volatile memory block adapted to store user data within the programmable logic device, wherein the volatile memory block is not adapted to configure the logic blocks;
configuration memory adapted to store first configuration data for configuration of the logic blocks and the volatile memory block of the programmable logic device;
means for storing in a non-volatile manner the user data from the volatile memory block and configuration data for the configuration memory, wherein the storing means is partitioned to provide a configuration portion to store configuration data for transfer to the configuration memory and a user portion to store the user data for the volatile memory block; and
means for controlling transfer of the user data from the volatile memory block to the storing means and from the storing means to the volatile memory block and for controlling transfer of configuration data from the storing means to the configuration memory,
wherein the volatile memory block and the configuration memory are distinct and separate from each other and located in different portions of the programmable logic device.
12. The programmable logic device of claim 11, further comprising means for communicating with the controlling means.
13. A programmable logic device comprising:
a plurality of logic blocks;
a volatile memory block adapted to store user data within the programmable logic device, wherein the volatile memory block is not adapted to configure the logic blocks;
configuration memory adapted to store first configuration data for configuration of the logic blocks and the volatile memory block of the programmable logic device;
means for storing in a non-volatile manner the user data from the volatile memory block and configuration data for the configuration memory, wherein the storing means is partitioned to provide a configuration portion to store configuration data for transfer to the configuration memory and a user portion to store the user data for the volatile memory block; and
means for controlling transfer of the user data from the volatile memory block to the storing means and from the storing means to the volatile memory block,
wherein the volatile memory block and the configuration memory are distinct and separate from each other and located in different portions of the programmable logic device; and
wherein at least one cell of the configuration memory is associated with the volatile memory block and provides a control signal to control whether the volatile memory block can transfer its user data to the storing means.
14. A method of storing information within a programmable logic device, the method comprising:
providing a volatile memory block adapted to store user data, wherein the volatile memory block is not adapted to configure the programmable logic device;
providing configuration memory adapted to configure the programmable logic device based on data stored in the configuration memory;
providing a non-volatile memory block partitioned into a configuration portion and a user portion, wherein the configuration portion is adapted to store configuration data for transfer to the configuration memory to configure the programmable logic device, and wherein the user portion is adapted to store user data for the volatile memory block; and
controlling transfer of configuration data from the non-volatile memory block to the configuration memory and transfer of the user data from the volatile memory block to the non-volatile memory block and from the non-volatile memory block to the volatile memory blocks,
wherein the volatile memory block and the configuration memory are distinct and separate from each other and located in different portions of the programmable logic device.
15. The method of claim 14, wherein the volatile memory block is configurable to function as shadow user non-volatile memory and is associated with the user portion of the non-volatile memory block.
16. The method of claim 14, further comprising a plurality of the volatile memory blocks, wherein the non-volatile memory block is further partitioned into a plurality of user portions associated with the volatile memory blocks, and wherein the non-volatile memory block is further partitioned into at least one of a trim portion, a test portion, and a tag portion.
17. The method of claim 14, further comprising performing a background programming operation prior to the transfer of the user data from the volatile memory block to the non-volatile memory block to preserve the user data from the volatile memory block during a reconfiguration.