1. A telecommunications device comprising:
a chassis having a front and a rear;
a plurality of jack inserts mounted in the chassis, the jack inserts including access ports adapted for receiving plugs, the jack inserts including normal-through switches having tip and ring springs for contacting the plugs when the plugs are inserted within the access ports, the normal through switches also including normal springs that engage the tip and ring springs when the plugs are not inserted in the access ports, the access ports being accessible from the front of the chassis;
cross-connect termination structures accessible from the rear of the chassis;
INOUT termination structures accessible from the rear of the chassis;
first and second circuit board sections electrically connected together, the first circuit board section being located behind the jack inserts and in front of the second circuit board section, the second circuit board section being located in front of the cross-connect termination structures and the INOUT termination structures, the first and second circuit board sections each including a major first side and a major second side, the major first sides facing in a forward direction and the major second sides facing in a rearward direction; and
normal-through circuits that electrically connect the INOUT termination structures to the cross-connect termination structures, the normal-through circuits including the normal-through switches, the normal-through circuits also including electrical pathways provided by the first and second circuit board sections.
2. The telecommunications device of claim 1, wherein the first and second circuit board sections are separated by a stand-off piece.
3. The telecommunications device of claim 1, wherein the first and second circuit board sections include separate circuit boards electrically interconnected by an electrical connector.
4. The telecommunications device of claim 1, wherein the first and second circuit board sections defined by a flexible circuit board including a bend portion that electrically connects the first and second circuit board sections.
5. The telecommunications device of claim 1, wherein the first and second circuit board sections are generally parallel.
6. The telecommunications device of claim 1, wherein the first and second circuit board sections are generally parallel relative to a back plane of the chassis.
7. The telecommunications device of claim 1, wherein the chassis has a height less than 4 inches.
8. The telecommunications device of claim 7, wherein the chassis has a height less than or equal to 3.5 inches.
9. The telecommunications device of claim 7, wherein the chassis is sized to hold at least 56 of the jack inserts.
10. The telecommunications device of claim 9, wherein the chassis is sized to hold at least 64 of the jack inserts.
11. The telecommunications device of claim 10, wherein the chassis is sized to hold at least 84 of the jack inserts.
12. The telecommunications device of claim 11, wherein the chassis has a length of about 23 inches.
13. The telecommunications device of claim 1, wherein the cross-connect termination structures and the INOUT termination structures include wire wrap members.
14. The telecommunications device of claim 13, wherein the wire wrap members are mechanically and electrically connected directly to the second circuit board section.
15. The telecommunications device of claim 14, wherein the tip springs, the ring springs and the normal springs are electrically connected to the first circuit board section by intermediate electrical conductors.
16. The telecommunications device of claim 1, wherein the jack inserts each include a dielectric body in which the tip springs, the ring springs and the normal springs are mounted, the dielectric body including front and rear ends, the front end defining the access ports, and the springs including tails that project rearwardly from the rear end of the dielectric body.
17. The telecommunications device of claim 1, further comprising a plurality of jack modules that mount within the chassis, each of the jack modules including a jack mount for holding a plurality of the jack inserts.
18. The telecommunications device of claim 1, further comprising a plurality of the first circuit board sections positioned in front of the second circuit board section.
19. The telecommunications device of claim 18, wherein the plurality of first circuit board sections are positioned side-by-side one another.
20. The telecommunications device of claim 19, wherein the plurality of first circuit board sections are aligned in a common plane.
21. The telecommunications device of claim 19, wherein the second circuit board section includes a single circuit board.
22. The telecommunications device of claim 21, wherein the second circuit board is co-extensive with a majority of a back plane of the chassis.
23. The telecommunications device of claim 1, wherein each jack defines two monitor ports accessible from the front of the chassis.
24. The telecommunications device of claim 23, wherein the chassis has a height less than 4 inches.
25. The telecommunications device of claim 24, wherein the chassis has a height less than or equal to 3.5 inches.
26. The telecommunications device of claim 7, wherein the jack inserts have a density greater than 43 jack inserts per foot of chassis length.
27. A telecommunications device comprising:
a chassis having a front and a rear;
a plurality of jack inserts mounted in the chassis, the jack inserts including access ports adapted for receiving plugs, the jack inserts including normal-through switches having tip and ring springs for contacting the plugs when the plugs are inserted within the access ports, the normal through switches also including normal springs that engage the tip and ring springs when the plugs are not inserted in the access ports, the access ports being accessible from the front of the chassis;
cross-connect termination structures accessible from the rear of the chassis;
INOUT termination structures accessible from the rear of the chassis;
the jack inserts each including a dielectric body in which the tip springs, the ring springs and the normal springs are mounted, the dielectric body including front and rear ends, the front end defining the access ports, and the springs including tails that project rearwardly from the rear end of the dielectric body; and
normal-through circuits that electrically connect the INOUT termination structures to the cross-connect termination structures, the normal-through circuits including the normal-through switches.
28. The telecommunications device of claim 27, wherein each jack defines two monitor ports accessible from the front of the chassis.
29. The telecommunications device of claim 28, wherein the chassis has a height less than 4 inches.
30. The telecommunications device of claim 28, wherein the chassis has a height less than or equal to 3.5 inches.
31. The telecommunications device of claim 29, wherein the jack inserts have a density greater than 40 jack inserts per foot of chassis length.
32. The telecommunications device of claim 30, wherein the jack inserts have a density greater than 43 jack inserts per foot of chassis length.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for process, voltage, and temperature compensation, comprising:
training at least one functional delay cell for a clock path which has a delay setting and training a spare delay cell which has a one-fourth cycle delay setting;
calculating a ratio for the at least one functional delay cell by dividing the at least one functional delay cells’ delay setting into the spare delay cells’ one-fourth cycle delay setting;
entering a functional mode and switching to a Master-Slave approach.
2. The method as claimed in claim 1, wherein a delay cell is utilized for the at least one functional delay cell which can update the at least one functional delay cells’ delay setting in one selected from the group consisting of a single update and a series of incremental updates creating glitches on a clock passing through.
3. The method as claimed in claim 1, wherein a one-fourth cycle delay shift of a clock is achieved.
4. The method as claimed in claim 1, wherein during functional mode the spare delay cell repeats the training sequence continuously to update the spare delay cells one-fourth cycle delay setting while the at least one functional delay cell delays a clock.
5. The method as claimed in claim 4, further including the step of updating the at least one functional delay cell during functional mode at the end of each training sequence of the spare delay cell by dividing the ratio of the at least one functional delay cell into the spare delay cell’s updated one-fourth delay setting.
6. The method as claimed in claim 1, wherein a functional delay cell is trained for each clock path.
7. The method as claimed in claim 6, wherein the training is performed in parallel for each delay cell.
8. A computer readable medium having computer-executable instructions for performing a method for process, voltage, and temperature compensation, said method comprising:
training at least one functional delay cell for a clock path which has a delay setting and training a spare delay cell which has a one-fourth cycle delay setting;
calculating a ratio for the at least one functional delay cell by dividing the at least one functional delay cells’ delay setting into the spare delay cells’ one-fourth cycle setting;
entering a functional mode and switching to a Master-Slave approach.
9. The computer readable medium having computer-executable instructions for performing a method for process, voltage, and temperature compensation as claimed in claim 8, wherein a delay cell is utilized for the at least one functional delay cell which can update the at least one functional delay cells’ delay setting in one selected from consisting of a single update and a series of incremental updates creating glitches on a clock passing through.
10. The computer readable medium having computer-executable instructions for performing a method for process, voltage, and temperature compensation as claimed in claim 8, wherein a one-fourth cycle delay shift of a clock is achieved.
11. The computer readable medium having computer-executable instructions for performing a method for process, voltage, and temperature compensation as claimed in claim 8, wherein during functional mode the spare delay cell repeats the training sequence continuously to update the spare delay cells one-fourth cycle delay setting while the at least one functional delay cell delays a clock.
12. The computer readable medium having computer-executable instructions for performing a method for process, voltage, and temperature compensation as claimed in claim 11, wherein the method further includes the step of updating the at least one functional delay cell during functional mode at the end of each training sequence of the spare delay cell by dividing the ratio of the at least one functional delay cell into the spare delay cell’s updated one-fourth delay setting.
13. The computer readable medium having computer-executable instructions for performing a method for process, voltage, and temperature compensation as claimed in claim 8, wherein a functional delay cell is trained for each clock path.
14. The computer readable medium having computer-executable instructions for performing a method for process, voltage, and temperature compensation as claimed in claim 13, wherein the training is performed in parallel for each delay cell.
15. A system for process, voltage, and temperature compensation, comprising:
means for training at least one functional delay cell for a clock path which has a delay setting and training a spare delay cell which has a one-fourth cycle delay setting;
means for calculating a ratio for the at least one functional delay cell by dividing the at least one functional delay cells’ delay setting into the spare delay cells’ one-fourth cycle delay setting;
means for entering a functional mode and switching to a Master-Slave approach.
16. The system for process, voltage, and temperature compensation as claimed in claim 15, wherein a delay cell is utilized for the at least one functional delay cell which can update the at least one functional delay cells’ delay setting in one selected from the group consisting of a single update and a series of incremental updates creating glitches on a clock passing through.
17. The system for process, voltage, and temperature compensation as claimed in claim 15, wherein a one-fourth cycle delay shift of a clock is achieved.
18. The system for process, voltage, and temperature compensation as claimed in claim 15, wherein during the functional mode the spare delay cell repeats the training sequence continuously to update the spare delay cells one-fourth cycle delay setting while the at least one functional delay cell delays a clock.
19. The system for process, voltage, and temperature compensation as claimed in claim 18, further comprising means for updating the at least one functional delay cell during functional mode at the end of each training sequence of the spare delay cell by dividing the ratio of the at least one functional delay cell into the spare delay cell’s updated one-fourth delay setting.
20. The system for process, voltage, and temperature compensation as claimed in claim 15, wherein a functional delay cell is trained for each for each clock path.
21. The system for process, voltage, and temperature compensation as claimed in claim 20, wherein the training is performed in parallel for each delay cell.