1. A power supply system for a telecommunications facility, comprising:
a liquid source;
a vaporizing system for the vaporization of a liquid from said liquid source into a vaporous fuel, said vaporizing system including a ventilated housing which is associated with a heater which is adapted to blow heated air across a portion of said vaporization system for the purpose of avoiding the development of frozen condensate on said vaporizing system, said vaporization resulting in heat absorption;
a cooling system which is adapted to use said heat absorption for cooling said facility; and
a generator which generates electric current using said vaporous fuel.
2. The system of claim 1, wherein said liquid comprises hydrogen.
3. The system of claim 1, wherein said generator comprises an internal combustion engine.
4. The system of claim 3, wherein said internal combustion engine is piston driven.
5. The system of claim 1, wherein said generator includes a proton exchange membrane.
6. The system of claim 1, wherein said electric current comprises alternating current.
7. The system of claim 1, wherein said electric current comprises direct current.
8. The system of claim 1, wherein said cooling system comprises:
a first heat transfer device which absorbs heat into at least one of a liquid and vaporous hydrogen from a heat transfer medium, said heat transfer medium being useable for cooling purposes.
9. The system of claim 8 wherein said heat transfer medium is a fluid.
10. The system of claim 9 wherein said fluid comprises ethylene glycol.
11. The system of claim 10 wherein said fluid comprises water.
12. The system of claim 8 wherein said heat transfer medium is a refrigerant.
13. The system of claim 8 further comprising a second heat transfer device which accepts said heat transfer medium from said first heat transfer device and uses said heat transfer medium for cooling purposes.
14. The system of claim 8, wherein said first heat transfer device is incorporated into said vaporizing system.
15. The system of claim 1, wherein said cooling system is used for air conditioning in the facility.
16. The system of claim 1, wherein said heater receives heat energy from a heat-delivering medium, said heat energy being drawn from a power-generating device.
17. The system of claim 16, wherein said power-generating device produces electricity.
18. The system of claim 16, wherein said power-generating device is said generator.
19. The system of claim 18, wherein said generator comprises an internal combustion engine.
20. The system of claim 19, wherein said heat-delivering medium is also used to cool the internal combustion engine.
21. The system of claim 20, wherein said heat-delivering medium is run through an engine jacket of the internal combustion engine and transmitted using an engine-jacket pump.
22. A method of supplying power for use in a telecommunications facility, comprising:
providing a liquid source;
vaporizing the liquid into a vaporous fuel using a conduit, blowing heated air past said conduit to prevent the development of frozen condensate thereon, said vaporization resulting in heat absorption;
using said heat absorption for cooling purposes in the telecommunications facility; and
generating electric current using said vaporous fuel.
23. The method of claim 22, comprising:
selecting hydrogen as the liquid.
24. The method of claim 22, comprising:
combusting the vaporous fuel in accomplishing the generating step.
25. The method of claim 22, comprising:
combusting the vaporous fuel in a piston-driven internal combustion engine in accomplishing the generating step.
26. The method of claim 22, comprising:
introducing the vaporous fuel into a proton exchange membrane in accomplishing said generating step.
27. The method of claim 22, comprising:
absorbing heat into at least one of said liquid and vaporous hydrogen from a heat transfer medium; and
using said heat transfer medium for cooling purposes.
28. The method of claim 27, comprising:
selecting a fluid to serve as the heat transfer medium.
29. The method of claim 27, comprising:
selecting ethylene glycol to comprise a part of said heat transfer medium.
30. The method of claim 27, comprising:
receiving said heat transfer medium after said heat has been absorbed out of it; and
cooling with said heat transfer medium.
31. The method of claim 30, comprising:
air conditioning a portion of said facility using cooling provided by said heat transfer medium.
32. The method of claim 22, comprising:
including said conduit in a housing;
ventilating said housing; and
transmitting said heated air in and out of said housing.
33. The method of claim 22, comprising:
drawing heat energy from a power-generating device in creating said heated air.
34. The method of claim 22, comprising:
drawing heat energy from an internal combustion engine in creating said heated air.
35. The method of claim 22, comprising:
drawing heat energy from the same device used to accomplish said generating step in creating said heated air.
36. The method of claim 22, comprising:
deriving a heat-delivering medium from a power-generating device in creating said heated air.
37. The method of claim 36, comprising:
selecting as said heat-delivering medium a fluid used to cool said power-generating device.
38. The method of claim 37, comprising:
pumping said heat-delivering medium from an engine jacket on said power-generating device in creating said heated air; and
returning said heat-delivering medium to said engine jacket after it has been used in creating said heated air.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A phase change memory device comprising:
a semiconductor substrate;
a plurality of cell arrays stacked above said semiconductor substrate, each cell array having memory cells arranged in a matrix manner for storing resistance values as data that are determined by phase change of said memory cells, bit lines each commonly connecting one ends of plural memory cells arranged in a first direction of said matrix and word lines each commonly connecting the other ends of plural memory cells arranged in a second direction of said matrix;
a readwrite circuit formed on said semiconductor substrate as underlying said cell arrays for reading and writing data of said cell arrays;
first and second vertical wirings disposed outside of first and second boundaries that define a cell layout region of said cell arrays in said first direction to connect said bit lines of the respective cell arrays to said readwrite circuit; and
third vertical wirings disposed outside of one of third and fourth boundaries that define said cell layout region in said second direction to connect said word lines of the respective cell arrays to said readwrite circuit.
2. The phase change memory device according to claim 1, wherein
each said memory cell has a stack structure of a chalcogenide and a diode as disposed at each cross portion of said bit lines and word lines in the respective cell arrays.
3. The phase change memory device according to claim 2, wherein
said diode of said memory cell is serially connected to said chalcogenide while having a polarity with said bit line side as a cathode and with said word line side as an anode, and wherein
said bit lines and word lines are so potentially fixed as to reversely bias said diode in a non-selected mode, while a selected bit line and a selected word line are pulse driven in negative and positive directions, respectively, in data read and write modes.
4. The phase change memory device according to claim 1, wherein
said cell arrays are so stacked as to share bit lines and word lines with adjacent two cell arrays.
5. The phase change memory device according to claim 1, wherein
said first to third vertical wirings are contact plugs which are buried in an interlayer dielectric film surrounding said cell arrays.
6. The phase change memory device according to claim 1, wherein
neighboring two memory cells in each said cell array constitute a pair cell for storing complementary data one of which is a high resistance value state, and the other is a low resistance value state, and wherein
said complementary data of said pair cell are read out to a bit line pair as one bit of data.
7. The phase change memory device according to claim 6, wherein
said pair cell is selected such that another bit line is disposed between said bit line pair to which said complementary data are read out.
8. The phase change memory device according to claim 1, wherein
said readwrite circuit comprises:
a global bus region having a plurality of data lines to which read data are transferred and a plurality of write pulse signal lines for transferring write pulses to said bit lines, said data lines and said write pulse signal lines being so disposed as to cross a central portion of said cell layout region in said second direction;
first and second bit line select circuits disposed along said first and second boundaries of said cell layout region, respectively, to which the respective bit lines of neighboring two cell arrays are connected;
first and second sense amp arrays for sensing data of bit lines selected by said first and second bit line select circuits, respectively, said first and second sense amp arrays being disposed between said first, second bit line select circuits and said global bus region, respectively;
a word line select circuit disposed along one of said third and fourth boundaries of said cell layout region, to which shared word lines of said neighboring two cell arrays are connected; and
a write circuit disposed along the other of said third and fourth boundaries of said cell layout region for generating said write pulses supplied to said write pulse signal lines.
9. The phase change memory device according to claim 8, wherein
said shared word lines are simultaneously activated for a certain range which is selected by said word line select circuit, and the respective bit lines of said neighboring two cell arrays are simultaneously selected for the respective certain ranges which are selected by said first and second bit line select circuits, respectively, so that the respective plural memory cells in said neighboring two cell arrays are simultaneously accessed.
10. The phase change memory device according to claim 9, wherein
said first and second sense amp arrays have sense amps for simultaneously sensing data of the respective plural memory cells which are simultaneously selected in said neighboring two cell arrays, sensed data of which are simultaneously transferred to said data lines in said global bus region.
11. The phase change memory device according to claim 9, wherein
said write circuit is configured to simultaneously output write pulses, which are to be transferred to the respective plural bit lines simultaneously selected in said neighboring two cell arrays, to said write pulse signal lines in said global bus region.
12. The phase change memory device according to claim 8, wherein
neighboring two memory cells in each said cell array constitute a pair cell for storing complementary data, one of which is a high resistance value state and the other is a low resistance value state, and wherein
each of said first and second sense amp arrays comprises differential type current sensing amplifiers arranged therein, each of said current sensing amplifiers being connected to a bit line pair to which said pair cell is connected for sensing a current difference due to said complementary data.
13. The phase change memory device according to claim 8, wherein
said write circuit comprises:
a logic pulse generation circuit for generating positive logic pulses and negative logic pulses to be supplied to selected word lines and selected bit lines in each said cell array, respectively, said positive logic pulses and negative logic pulses being controlled to have overlap widths therebetween in correspondence with write data; and
a write pulse generation circuit for selectively boosting said negative logic pulses output from said logic pulse generation circuit in correspondence with write data to output said write pulse signal lines.
14. The phase change memory device according to claim 13, wherein
said logic pulse generation circuit comprises:
a pulse generation circuit for generating two pulses with the same pulse width, which are phase-shifted each other; and
a logic gate circuit for outputting said negative logic pulses and positive logic pulses with an overlap time determined by combination logics determined depending on write data.
15. The phase change memory device according to claim 1, wherein
said plurality of cell arrays comprise:
a first cell array having a plurality of mutually parallel first bit lines formed on an interlayer dielectric film covering said readwrite circuit, a plurality of memory cells laid out on each first bit line at a certain pitch, and a plurality of first word lines laid out on said memory cells in such a manner as to commonly connect together plural memory cells aligned in a direction crossing said first bit lines;
a second cell array being formed above said first cell array while sharing said first word lines with said first cell array and having a plurality of memory cells arrayed in the same layout as said first cell array and a plurality of second bit lines overlying the memory cells in such a manner as to commonly connect together plural memory cells aligned in a direction crossing said first word lines;
a third cell array being formed above said second cell array while sharing said second bit lines with said second cell array and having a plurality of memory cells laid out in the same layout as said second cell array and a plurality of second word lines overlying the memory cells in such a manner as to commonly connect together plural memory cells aligned in a direction crossing said second bit lines; and
a fourth cell array being formed above said third cell array while sharing said second word lines with said third cell array and having a plurality of memory cells disposed in the same layout as the memory cells of said third cell array and a plurality of third bit lines overlying the memory cells in such a manner as to commonly connect together plural memory cells aligned in a direction crossing said second word lines.
16. The phase change memory device according to claim 15, wherein
said memory cell of each said cell array has a chalcogenide and a diode which are stacked at each corresponding cross portion of said first to third bit lines and said first and second word lines.
17. The phase change memory device according to claim 16, wherein
the lamination order of said chalcogenide and diode is inverse between upper and lower neighboring cell arrays, and said diode is formed to have a polarity with the side of said first to third bit lines as a cathode.
18. The phase change memory device according to claim 15, wherein
said readwrite circuit comprises:
a global bus region having a plurality of data lines to which read data are transferred and a plurality of write pulse signal lines for transferring write pulses to said bit lines, said data lines and said write pulse signal lines being so disposed as to cross a central portion of said cell layout region in said second direction;
a first bit line select circuit disposed along said first boundary of said cell layout region, to which said first and third bit lines are commonly connected;
a second bit line select circuit disposed along said second boundary of said cell layout region, to which said second bit lines are connected;
first and second sense amp arrays for sensing data of bit lines selected by said first and second bit line select circuits, respectively, said first and second sense amp arrays being disposed between said first, second bit line select circuits and said global bus region, respectively;
a word line select circuit disposed along one of said third and fourth boundaries of said cell layout region, to which said first and second word lines are connected; and
a write circuit disposed along the other of said third and fourth boundaries of said cell layout region for generating said write pulses supplied to said write pulse signal lines.
19. The phase change memory device according to claim 18, wherein
said word line select circuit is configured to simultaneously activate a certain range of either one of said first and second word lines, and wherein
said first and second bit line select circuit are configured to simultaneously select a certain range of either one of said first and third bit lines, and simultaneously select a certain range of said second bit lines, respectively.
20. The phase change memory device according to claim 19, wherein
said first and second sense amp arrays have sense amps for simultaneously sensing data of the respective plural memory cells which are simultaneously selected in said first and second cell arrays or in said third and fourth cell arrays, sensed data of which are simultaneously transferred to said data lines in said global bus region.
21. The phase change memory device according to claim 19, wherein
said write circuit is configured to simultaneously output write pulses, which are to be transferred to the respective plural bit lines simultaneously selected in said first and second cell arrays or in said third and fourth cell arrays, to said write pulse signal lines in said global bus region.
22. The phase change memory device according to claim 15, wherein
neighboring two memory cells sharing said first or second word lines in each of said first to fourth cell arrays constitute a pair cell for storing complementary data one of which is a high resistance value state, and the other is a low resistance value state, and wherein
said complementary data of said pair cell are read out to a bit line pair as one bit of data.
23. The phase change memory device according to claim 22, wherein
said pair cell is selected such that another bit line is disposed between said bit line pair to which said complementary data are read out.