1. A multi-channel serdes receiver, comprising:
a central frequency synthesizer configured to provide both in-phase and quadrature-phase clock signals; and
a plurality of channel-specific receivers coupled to said central frequency synthesizer, each of said plurality of channel-specific receivers configured to receive and deserialize a data signal and include a clock recovery circuit having a phase detector and a phase interpolator, said interpolator configured to receive said clock signals from said central frequency synthesizer and couple said phase detector and said central frequency synthesizer.
2. The receiver as recited in claim 1 wherein said central frequency synthesizer includes a voltage-controlled oscillator.
3. The receiver as recited in claim 1 wherein said central frequency synthesizer is a phase-locked loop.
4. The receiver as recited in claim 1 wherein said plurality further includes at least one integrator coupled to said phase interpolator and a demultiplexer.
5. The receiver as recited in claim 4 wherein said at least one integrator performs an integrate-and-dump function.
6. The receiver as recited in claim 1 wherein said clock recovery circuit comprises a delay-locked loop clock and data recovery circuit.
7. The receiver as recited in claim 1 wherein said plurality includes two integrators configured to perform a first 1:2 demultiplexing operation and four latches coupled to said integrators and configured to perform a second 1:2 demultiplexing operation.
8. The receiver as recited in claim 1 further comprising a clock generation circuit coupled to said phase interpolator and configured to generate a plurality of clock signals.
9. The receiver as recited in claim 8 further comprising at least one synchronizer configured to reduce skew between said plurality of clock signals.
10. A method of operating a multi-channel serdes receiver, comprising:
generating a central clock signal having both in-phase and quadrature-phase clock signals with a central frequency synthesizer; and
transmitting said central clock signal to a plurality of channel-specific receivers coupled to said central frequency synthesizer, each of said plurality receiving and deserializing a data signal and including a clock recovery circuit having a phase detector and a phase interpolator, said interpolator receiving said clock signals from said central frequency synthesizer.
11. The method as recited in claim 10 wherein said central frequency synthesizer includes a voltage-controlled oscillator or a phase-locked loop.
12. The method as recited in claim 10 wherein said plurality further includes at least one integrator coupled to said phase interpolator and a demultiplexer.
13. The method as recited in claim 12 wherein said at least one integrator performs an integrate-and-dump function.
14. The method as recited in claim 10 wherein said clock recovery circuit comprises a delay-locked loop clock and data recovery circuit.
15. The method as recited in claim 10 wherein said plurality includes two integrators, said integrators performing a first 1:2 demultiplexing operation, and four latches coupled to said integrators, said latches performing a second 1:2 demultiplexing operation.
16. The method as recited in claim 10 further comprising generating a plurality of clock signals via a clock generation circuit coupled to said phase interpolator and reducing a skew between said plurality of clock signals with at least one synchronizer.
17. An integrated circuit, comprising:
a substrate; and
a plurality of circuit layers located over said substrate and arranged to form a multi-channel serdes receiver that includes:
a central frequency synthesizer configured to provide both in-phase and quadrature-phase clock signals; and
a plurality of channel-specific receivers coupled to said central frequency synthesizer, each of said plurality of channel-specific receivers configured to receive and deserialize a data signal and include a clock recovery circuit having a phase detector and a phase interpolator, said interpolator configured to receive said clock signals from said central frequency synthesizer.
18. The integrated circuit as recited in claim 17 wherein said central frequency synthesizer includes a voltage-controlled oscillator.
19. The integrated circuit as recited in claim 17 wherein said central frequency synthesizer is a phase-locked loop.
20. The integrated circuit as recited in claim 17 wherein said plurality further includes at least one integrator coupled to said phase interpolator and a demultiplexer that performs an integrate-and-dump function.
21. The integrated circuit as recited in claim 17 wherein said clock recovery circuit comprises a delay-locked loop clock and data recovery circuit.
22. The integrated circuit as recited in claim 17 wherein said plurality includes two integrators configured to perform a first 1:2 demultiplexing operation and four latches coupled to said integrators and configured to perform a second 1:2 demultiplexing operation.
23. The integrated circuit as recited in claim 17 further comprising a clock generation circuit coupled to said phase interpolator and configured to generate a plurality of clock signals.
24. The integrated circuit as recited in claim 23 further comprising at least one synchronizer configured to reduce skew between said plurality of clock signals.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A processor element for a memory module bus of a computer system, said processor element comprising:
a field programmable gate array configurable to perform an identified algorithm on an operand provided thereto and operative to alter data provided directly thereto on said memory module bus; and
a direct data connection coupled to said field programmable gate array for providing said altered data directly from said memory module bus to an external device coupled thereto.
2. The processor element of claim 1 further comprising:
a control connection coupled to said processor element for indicating to a processor of said computer system an arrival of data on said data connection from said external device.
3. The processor element of claim 2 wherein said control connection indicates said arrival of data to said processor by means of a peripheral bus.
4. The processor element of claim 3 wherein said peripheral bus comprises a PCI bus.
5. The processor element of claim 2 wherein said control connection indicates said arrival of data to said processor by means of a graphics bus.
6. The processor element of claim 5 wherein said graphics bus comprises an AGP bus.
7. The processor element of claim 2 wherein said control connection indicates said arrival of data to said processor by means of a system maintenance bus.
8. The processor element of claim 7 wherein said system maintenance bus comprises an SM bus.
9. The processor element of claim 1 wherein said memory module bus comprises a DIMM bus.
10. The processor element of claim 9 wherein said processor element comprises a DIMM physical format.
11. The processor element of claim 1 wherein said memory module bus comprises a in-line memory module serial interface bus.
12. The processor element of claim 11 wherein said processor element comprises a in-line memory module serial interface physical format.
13. The processor element of claim 1 wherein said external device comprises one of another computer system, switch or network.
14. The processor element of claim 1 wherein said processor of said computer system comprises a plurality of processors.
15. The processor element of claim 1 wherein said field programmable gate array is further operative to alter data provided thereto from said external device on said data connection and providing said altered data on said memory module bus.