What is claimed is:
1. A method for removing contaminants from an ink jet print head having a nozzle plate with a plurality of nozzles, said method comprising:
a) applying a heat-activatable adhesive material over the surface of said nozzle plate having contaminants on the surface thereof;
b) applying heat to said heat-activatable adhesive material to cause it to flow over the surface of said nozzle plate having contaminants on the surface thereof, thereby causing said contaminants to adhere to said heat-activatable adhesive material; and
d) removing said heat-activatable adhesive material having said contaminants adhered thereto.
2. The method of claim 1 wherein pressure is also applied to said heat-activatable adhesive material.
3. The method of claim 1 wherein said heat-activatable material is a wax, a colloidal dispersion, a hot-melt polymer, a thermal-curable or photo-curable material or a thermally reversible polymer gel.
4. The method of claim 1 wherein said heat-activatable material comprises a thermally reversible polymer gel of a tri-block copolymer of poly(methyl methacrylate)-b-poly(n-butyl acrylate)-b-poly(methyl methacrylate).
5. The method of claim 4 wherein said heat-activatable material contains an organic solvent.
6. The method of claim 4 wherein said heat-activatable material also comprises a thermal-curable or photo-curable material.
7. The method of claim 6 wherein said heat-activatable material also contains a cross-linking agent.
8. The method of claim 1 wherein said heat-activatable adhesive material is carried by a support which forms a tape which is then applied over the surface of said nozzle plate having contaminants on the surface thereof, and the removal of said heat-activatable adhesive material having said contaminants adhered thereto is accomplished by peeling off said tape from said nozzle plate.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An electronic circuit comprising:
a first transistor having a source terminal coupled to a first node and a drain terminal coupled to a second node, wherein the first transistor has a first nominal threshold voltage;
a second transistor of the same type as the first transistor, the second transistor having a source terminal coupled to the first node and a drain terminal coupled to the second node, wherein the second transistor has a second nominal threshold voltage;
a third transistor having a drain terminal coupled to the second node and a source terminal coupled to a third node, the third transistor being of a different type than the first and second transistors, wherein the third transistor has a third nominal threshold voltage, and wherein gate terminals of the first and third transistors are coupled together; and
a fourth transistor having a drain terminal coupled to the second node and a source terminal coupled to the third node, the fourth transistor being of the same type as the third transistor, wherein the fourth transistor has a fourth nominal threshold voltage, and wherein gate terminals of the second and fourth transistors are coupled together;
wherein each of the first, second, third, and fourth nominal threshold voltages is different from each of the other ones of the first, second, third, and fourth nominal threshold voltages.
2. The electronic circuit as recited in claim 1, further comprising a first plurality of transistors including the first transistor and a second plurality of transistors including the second transistor, wherein each of the transistors of the first plurality is configured to activate based on the first nominal threshold voltage, and wherein each of the transistors of the second plurality is configured to activate based on the second nominal threshold voltage.
3. The electronic circuit as recited in claim 2, further comprising a third plurality of transistors including the third transistor and a fourth plurality of transistors including the fourth transistor, wherein each of the third plurality of transistors is configured to activate based on the third nominal threshold voltage and wherein each of the fourth plurality of transistors is configured to activate based on the fourth nominal threshold voltage.
4. The electronic circuit as recited in claim 3, wherein each transistor of the first and second pluralities of transistors is a p-type metal oxide semiconductor (PMOS) transistor, and wherein each transistor of the third and fourth plurality of transistors is an n-type metal oxide semiconductor (NMOS) transistor.
5. The electronic circuit as recited in claim 1, wherein the first transistor has a first nominal gate oxide thickness, and wherein the second transistor has a second nominal gate oxide thickness different from the first nominal gate oxide thickness.
6. The electronic circuit as recited in claim 1, wherein the first transistor has a first nominal channel dopant density, and wherein the second transistor has a second nominal channel dopant density different from the first channel dopant density.
7. The electronic circuit as recited in claim 1, wherein the electronic circuit includes a NAND gate.
8. The electronic circuit as recited in claim 1, wherein the electronic circuit includes an inverter.
9. A logic gate comprising:
a plurality of p-type metal oxide semiconductor (PMOS) transistors including a first subset of PMOS transistors having a first PMOS transistor, wherein each PMOS transistor of the first subset of PMOS transistors is configured to activate based on a first gate-source voltage, and a second subset of PMOS transistors including a second PMOS transistor, wherein each PMOS transistor of the second subset of PMOS transistors is configured to activate responsive to a second gate-source voltage different from the first gate-source voltage; and
a plurality of n-type metal oxide semiconductor (NMOS) transistors including a first subset of NMOS transistors having a first NMOS transistor, wherein each NMOS transistor of the first subset of NMOS transistors is configured to activate based on a third gate-source voltage, and a second subset of NMOS transistors including a second NMOS transistor, wherein each NMOS transistor of the second subset of NMOS transistors is configured to activate responsive to a fourth gate-source voltage different from the third gate-source voltage;
wherein a gate terminal of each of the plurality of PMOS transistors is coupled to a corresponding gate terminal of a corresponding one of the plurality of NMOS transistors.
10. The logic gate as recited in claim 9, wherein the first subset of PMOS transistors includes a greater number of PMOS transistors than the second subset of PMOS transistors.
11. The logic gate as recited in claim 9, wherein the first subset of NMOS transistors includes a greater number of NMOS transistors than the second subset of NMOS transistors.
12. The logic gate as recited in claim 9, wherein the logic gate is configured to perform at least one of a NAND function and an invert function.
13. An integrated circuit comprising:
a plurality of logic gates, wherein the power switch circuit and each of the plurality of logic gates includes a first plurality of p-type metal oxide semiconductor (PMOS) transistors, a second plurality of PMOS transistors, a first plurality of n-type metal oxide semiconductor (NMOS) transistors, and a second plurality of NMOS transistors, wherein:
each of the PMOS transistors of the first plurality of PMOS transistors is configured to become active responsive to a gate-source voltage less than a first nominal threshold voltage;
each of the PMOS transistors of the second plurality of PMOS transistors is configured to become active responsive to a gate-source voltage less than a second nominal threshold voltage;
each of the NMOS transistors of the first plurality of NMOS transistors is configured to become active responsive to a gate-source voltage greater than a third nominal threshold voltage;
each of the NMOS transistors of the second plurality of NMOS transistors is configured to become active responsive to a gate-source voltage greater than a fourth nominal threshold voltage;
wherein a gate terminal of each of the first plurality of PMOS transistors is coupled to a gate terminal of a corresponding one of the first plurality of NMOS transistors; and
wherein a gate terminal of each of the second plurality of PMOS transistors is coupled to a gate terminal of a corresponding one of the second plurality of NMOS transistors.
14. The integrated circuit as recited in claim 13, wherein the first nominal threshold voltage is less than the second nominal threshold voltage, and wherein the third nominal threshold voltage is greater than the fourth nominal threshold voltage.
15. The integrated circuit as recited in claim 13, wherein each of the first plurality of PMOS transistors has a channel dopant density different from that of the second plurality of PMOS transistors, and wherein each of the first plurality of NMOS transistors has a channel dopant density different from that of the second plurality of NMOS transistors.
16. The integrated circuit as recited in claim 13, wherein at least one of the plurality of logic gates includes a greater number of the first plurality of PMOS transistors than of the second plurality of PMOS transistors, and further includes a greater number of the first plurality of NMOS transistors than of the second plurality of NMOS transistors.
17. The integrated circuit as recited in claim 13, further comprising a power switch, wherein the power switch includes one or more of the first plurality of NMOS transistors and one or more of the second plurality of NMOS transistors.
18. The integrated circuit as recited in claim 13, wherein at least one of the plurality of logic gates is configured to perform a NAND function, and wherein at least one of the plurality of logic gates is configured to perform an invert function.