1. A microprocessor on a chip comprising:
a plurality of arithmetic units;
a register file comprising a plurality of data registers communicatively connected to the plurality of arithmetic units; and
an instruction fetcher and instruction decoder supplying instructions of one or more software threads to the plurality of arithmetic units;
wherein the microprocessor is capable of executing the one or more software threads in at least one mode of a plurality of modes , the plurality of modes including:
i) the arithmetic units are operating jointly on one of the one or more software threads using a single program pointer; and
ii) a plurality of groups of arithmetic units are operating on different software threads of the one or more software threads using a plurality of program pointers, each group of arithmetic units having one of the plurality of program pointers dedicated to that group of arithmetic units.
2. The microprocessor according to claim 1, wherein the microprocessor further comprises a plurality of instruction decode units supplying instructions to the plurality of arithmetic units according to the single program pointer or the plurality of program pointers.
3. The microprocessor according to claim 2, wherein the plurality of arithmetic units are arranged in an array.
4. The microprocessor according to claim 3, wherein a network interconnects the plurality of arithmetic units in the array.
5. The microprocessor according to claim 3, wherein while executing the one or more software threads in a loop, at least a plurality of the instructions stay the same for a plurality of clock cycles once supplied to the arithmetic units while multiple data words are streamed through the arithmetic units and processed by the arithmetic units based on the at least a plurality of the instructions.
6. The microprocessor according to claim 1, wherein in mode (ii) the register file is split, providing a dedicated register space to each group of arithmetic units operating on a different thread.
7. A method for operating a microprocessor on a chip, the method comprising:
providing a plurality of arithmetic units and a register file comprising a plurality of data registers communicatively connected to the plurality of arithmetic units;
providing an instruction fetcher and instruction decoder to supply instructions of one or more software threads to the plurality of arithmetic units; and
executing the one or more software threads in at least one mode of a plurality of modes, the plurality of modes including:
i) the arithmetic units are operating jointly on one of the one or more software threads using a single program pointer; and
ii) a plurality of groups of arithmetic units are operating on different software threads of the one or more software threads using a plurality of program pointers, each group of arithmetic units having one of the plurality of program pointers dedicated to that group of arithmetic units.
8. The method according to claim 7, further comprising supplying instructions to the plurality of arithmetic units according to the single program pointer or the plurality of program pointers using a plurality of instruction decode units.
9. The method according to claim 8, wherein the plurality of arithmetic units are arranged in an array.
10. The method according to claim 9, wherein a network interconnects the plurality of arithmetic units in the array.
11. The method according to claim 9, wherein while executing the one or more software threads in a loop, at least a plurality of the instructions stay the same for a plurality of clock cycles once supplied to the arithmetic units while multiple data words are streamed through the arithmetic units and processed by the arithmetic units based on the at least a plurality of the instructions.
12. The method according to claim 7, wherein in mode (ii) the register file is split, providing a dedicated register space to each group of arithmetic units operating on a different thread.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A hanger device comprising of:
(a) a bracket;
(b) a first hanger arm having a top surface and a bottom surface, wherein said top surface of said first hanger arm comprises at least one notch, wherein said bottom surface of said first hanger arm comprises at least one notch, and wherein said first hanger arm is connected to said bracket via a first hinge; and
(c) a second hanger arm having a top surface and a bottom surface, wherein said top surface of said second hanger arm comprises at least one notch, wherein said bottom surface of said second hanger arm comprises at least one notch, and wherein said second hanger arm is connected to said first hanger arm via a second hinge.
2. The hanger device of claim 1, wherein said first hanger arm comprises at least one eyelet and said second hanger arm comprises at least one eyelet.
3. The hanger device of claim 1, wherein said hanger device has three configurations.
4. The hanger device of claim 1, wherein said bracket is positioned substantially parallel to said first hanger arm and said second hanger arm.
5. The hanger device of claim 1, wherein said at least one notch of said top surface of said first hanger arm and said at least one notch of said top surface of said second hanger arm are aligned, wherein said at least one notch of said bottom surface of said first hanger arm and said at least one notch of said bottom surface of said second hanger arm are aligned.
6. The hanger device of claim 2, wherein said at least eyelet of said first hanger arm and said at least one eyelet of said second hanger arm are aligned.
7. The hanger device of claim 1, wherein said bracket and said first hanger arm are connected at a 0 degree angle.
8. The hanger device of claim 1, wherein said first hanger arm and said second hanger arm are connected at a 0 degree angle.
9. The hanger device of claim 1, further comprising a mounting block.