1. An oral pharmaceutical composition in unit dose form, each unit dose comprising a statin within a unitary carrier body, said body comprising a soft, chewable, gelled oil-in-water emulsion, one or both of the oil phase and the water phase whereof comprises a physiologically tolerable omega-3 acid ester.
2. The oral pharmaceutical composition of claim 1, wherein said physiologically tolerable omega-3 acid ester is an EPA ester, a DHA ester or a combination of EPA and DHA esters.
3. A composition as claimed in claim 1 or claim 2 wherein said statin is selected from lovastatin, simvastatin, pravastatin, atorvastatin, and rosuvastatin.
4. A composition as claimed in any one of claims 1 to 3 wherein said emulsion contains gelatin as a gelling agent.
5. A composition as claimed in any one of claims 1 to 4 consisting of a said gelled emulsion wherein the said statin is present in the aqueous phase.
6. A pharmaceutical package comprising a foil-encased composition as claimed in any one of claims 1 to 5.
7. A package as claimed in claim 6 in the form of a blister pack.
8. A process for preparing an oral pharmaceutical composition in unit dose form, which process comprises: forming an oil phase comprising a physiologically tolerable oil which comprises a physiologically tolerable omega-3 acid ester; forming an aqueous phase comprising an aqueous solution of a physiologically tolerable gelling agent; forming an oil-in-water emulsion with said oil phase and said aqueous phase; allowing said emulsion to gel to form a soft chewable mass; and, before, during or after gelling of said emulsion, dividing said emulsion into dose units; wherein a statin is incorporated within one or both of said oil and water phases.
9. The process of claim 8, wherein said statin is incorporated within the oil phase.
10. A process for preparing an oral pharmaceutical composition in unit dose form, which process comprises: forming an oil phase comprising a physiologically tolerable oil; forming an aqueous phase comprising an aqueous solution of a statin dissolved or dispersed therein; forming a water-in-oil emulsion with said oil phase and said aqueous phase, forming an oil-in-water emulsion with said water-in-oil phase and a further aqueous phase, comprising an aqueous solution of a physiologically tolerable gelling agent, allowing said emulsion to gel to form a soft chewable mass; and, before, during or after gelling of said emulsion, dividing said emulsion into dose units.
11. A method of treatment of a human subject to combat cardiovascular disease, said method comprising orally administering an effective amount of a composition as claimed in any one of claims 1 to 5 to said subject.
12. In a method of treatment of a human subject to combat cardiovascular disease, which method comprises administering to said subject an effective amount of a statin and, in a separate dosage unit, an effective amount of a physiologically tolerable omega-3 acid ester, the improvement comprising administering said omega-3 acid ester in a dose unit comprising a gelled oil-in-water emulsion wherein the oil phase comprises said ester.
13. A physiologically tolerable gelled oil-in-water emulsion the oil phase whereof comprises a physiologically tolerable omega-3 acid ester for use in a method of treatment of a human subject to combat cardiovascular disease, which method comprises administering to said subject a statin and, in a separate dosage unit, said emulsion.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A nonvolatile semiconductor memory device comprising:
a plurality of memory cells which are arranged at the intersections of a plurality of word lines and a plurality of bit lines and each of which includes a variable-resistance element and a diode;
a sense amplifier which compares a voltage corresponding to current in a memory cell selected from said plurality of memory cells with a reference voltage to detect data read from the selected memory cell; and
a controller which generates the reference voltage according to the logical value of a signal output from the sense amplifier and which, before detecting data in the memory cell, adjusts the reference voltage on the basis of current flowing in one of said plurality of bit lines connected to said plurality of memory cells in a half-selected state detected by the sense amplifier.
2. The device according to claim 1, further comprising:
a voltage application module which applies half a read voltage to the word lines and the bit lines when the controller adjusts the reference voltage.
3. The device according to claim 2,
wherein the voltage application module, when reading a memory cell, applies the read voltage to the selected bit line and a voltage lower than half the read voltage to the selected word line.
4. The device according to claim 1,
wherein the reference voltage is set to a third voltage between a first voltage corresponding to data on a high resistance stored in the memory cell and a second voltage corresponding to data on a low resistance.
5. The device according to claim 1,
wherein the controller comprises:
a digital signal generator circuit which generates a digital signal according to the logical value of a signal output from the sense amplifier; and
a digital-to-analog converter which converts a digital signal generated by the digital signal generator circuit into the reference voltage.
6. The device according to claim 5,
wherein the digital signal generator circuit includes a counter which counts up or down the digital signal according to the logical value of a signal output from the sense amplifier.
7. The device according to claim 6,
wherein the controller causes the counter to count down from when the output signal of the sense amplifier has gone to \u201c0\u201d until a certain period of time has elapsed.
8. A nonvolatile semiconductor memory device comprising:
a plurality of memory cells which are arranged at the intersections of a plurality of word lines and a plurality of bit lines and each of which includes a variable-resistance element and a diode;
a sense amplifier which is connected to the selected bit line and which compares a voltage corresponding to current flowing in the selected memory cell with a reference voltage to detect data read from the memory cell; and
a controller which, before reading the memory cell, adjusts the reference voltage according to the logical value of a signal output from the sense amplifier and which adjust the reference voltage in a state where half a read voltage is applied to said plurality of bit lines and said plurality of word lines.
9. The device according to claim 8, further comprising:
a voltage application module which applies half the read voltage to the word lines and the bit lines when the controller adjusts the reference voltage.
10. The device according to claim 9,
wherein the voltage application module, when reading a memory cell, applies the read voltage to the selected bit line and a voltage lower than half the read voltage to the selected word line.
11. The device according to claim 10,
wherein the reference voltage is set to a third voltage between a first voltage corresponding to data on a high resistance stored in the memory cell and a second voltage corresponding to data on a low resistance.
12. The device according to claim 8,
wherein the controller includes a counter which counts up or down according to the logical value of a signal output from the sense amplifier.
13. The device according to claim 12,
wherein the controller causes the counter to count down from when the output signal of the sense amplifier has gone to \u201c0\u201d until a certain period of time has elapsed.
14. A method of reading a nonvolatile semiconductor memory device, the method comprising:
applying half a read voltage to a plurality of bit lines and a plurality of word lines to set a plurality of memory cells in a half-selected state before reading, each of said plurality of memory cells including a variable-resistance element and a diode;
comparing a voltage corresponding to current flowing in a bit line connected to a memory cell in the half-selected state with a reference voltage to generate an adjusted reference voltage; and
comparing a voltage corresponding to current flowing in the selected memory cell with the adjusted reference voltage to read the selected memory cell.
15. The method according to claim 14, wherein the adjusted reference voltage is set to a third voltage between a first voltage corresponding to data on a high resistance stored in the memory cell and a second voltage corresponding to data on a low resistance.
16. The method according to claim 14, further comprising:
applying the read voltage to the selected bit line and a voltage lower than half the read voltage to the selected word line when reading a memory cell.