1-20. (canceled)
21. A computer-implemented method executed by one or more processors, the method comprising:
identifying a plurality of communication plans;
identifying a first communication associated with a first access method and particular to a first attribute;
determining a first communication plan associated with the first communication from the plurality of communication plans, the determination based at least in part on the first attribute particular to the first communication;
identifying a second communication different than the first communication and associated with the first access method, the second communication particular to a second attribute different than the first attribute; and
determining a second communication plan associated with the second communication from the plurality of communication plans, the determination based at least in part on the second attribute particular to the second communication,
wherein the first communication plan is associated with a first prepaid subscription or pay-as-you-go monetary value, and the second communication plan is associated with a second prepaid subscription or pay-as-you-go monetary value.
22. The method of claim 21, further comprising:
identifying a third communication different than the first communication and second communication and associated with a second access method different from the first access method, the third communication particular to a third attribute; and
determining a third communication plan associated with the third communication from the plurality of communication plans, the determination based at least in part on the third attribute particular to the third communication, wherein the third communication plan is associated with a third prepaid subscription or pay-as-you-go monetary value.
23. The method of claim 21, wherein the first attribute is a destination address, and the second attribute is an origination address.
24. The method of claim 21, wherein the first attribute is an access method group, and the second attribute is a time of day.
25. The method of claim 21, wherein the first communication plan is an unlimited communication plan and the second communication plan is a pay-as-you-go communication plan.
26. The method of claim 21, further comprising:
identifying one or more restrictions associated with the first communication plan;
determining whether the first communication violates the one or more restrictions associated with the first communication plan; and
presenting the first communication with an option to use an alternate communication plan upon determination that the first communication violates the one or more restrictions associated with the first communication plan.
27. A computer-implemented method executed by one or more processors, the method comprising:
identifying a first communication including an associated destination address;
identifying a communication plan associated with the first communication;
determining, by the one or more processors, to associate the destination address with the communication plan;
associating the destination address with the communication plan upon determining to associate the destination address; and
permitting subsequent communications to the destination address under the communication plan,
wherein the communication plan is associated with a prepaid subscription or pay-as-you-go monetary value.
28. The method of claim 27, further comprising:
determining a number of destination addresses associated with the communication plan; and
determining whether the number of destination addresses associated with the communication plan is less than a maximum number of destination addresses that can be associated with the communication plan,
wherein associating the destination address with the communication plan occurs in response to determining that the number of destination addresses associated with the communication plan is less than the maximum number of destination addresses.
29. The method of claim 27, further comprising:
presenting the first communication with an option to use an alternate communication plan upon determination that a number of destination addresses associated with the communication plan is greater than or equal to a maximum number of destination addresses that can be associated with the communication plan.
30. The method of claim 27, wherein the determination to associate the destination address with the communication plan is based at least in part on the first communication being a completed communication.
31. The method of claim 27, further comprising:
identifying a reset condition associated with the communication plan; and
disassociating the destination address from the communication plan upon an occurrence of the reset condition.
32. The method of claim 31, wherein the reset condition is configured to occur at a particular time.
33. The method of claim 31, wherein the reset condition is configured to occur after a certain number of communications are permitted to the destination address under the communication plan.
34. The method of claim 31, wherein the reset condition is configured to occur after a certain number of communications are permitted to all destination addresses associated with the communication plan.
35. A system, comprising:
memory for storing data; and
one or more processors operable to perform operations comprising:
identifying a plurality of communication plans;
identifying a first communication associated with a first access method and particular to a first attribute;
determining a first communication plan associated with the first communication from the plurality of communication plans, the determination based at least in part on the first attribute particular to the first communication;
identifying a second communication different than the first communication and associated with the first access method, the second communication particular to a second attribute different than the first attribute; and
determining a second communication plan associated with the second communication from the plurality of communication plans, the determination based at least in part on the second attribute particular to the second communication,
wherein the first communication plan is associated with a first prepaid subscription or pay-as-you-go monetary value, and the second communication plan is associated with a second prepaid subscription or pay-as-you-go monetary value.
36. The system of claim 35, the operations further comprising:
identifying a third communication different than the first communication and second communication and associated with a second access method different from the first access method, the third communication particular to a third attribute; and
determining a third communication plan associated with the third communication from the plurality of communication plans, the determination based at least in part on the third attribute particular to the third communication, wherein the third communication plan is associated with a third prepaid subscription or pay-as-you-go monetary value.
37. The system of claim 35, wherein the first attribute is a destination address, and the second attribute is an origination address.
38. The system of claim 35, wherein the first attribute is an access method group, and the second attribute is a time of day.
39. The system of claim 35, wherein the first communication plan is an unlimited communication plan and the second communication plan is a pay-as-you-go communication plan.
40. The system of claim 35, the operations further comprising:
identifying one or more restrictions associated with the first communication plan;
determining whether the first communication violates the one or more restrictions associated with the first communication plan; and
presenting the first communication with an option to use an alternate communication plan upon determination that the first communication violates the one or more restrictions associated with the first communication plan.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A FinFET device comprising:
a lower fin body disposed on a substrate;
an upper fin body having first and second sidewalls extending upwardly from a portion of the lower fin body the first and second sidewalls facing each other;
a gate structure crossing over the upper fin body and covering an upper surface of the upper fin body and the first and second sidewalls; and
a source and a drain disposed on sidewalls of the upper fin body adjacent to sidewalls of the gate structure, made of a metal material layer, and disposed on an upper surface of the lower fin body positioned at both sides of the upper fin body, wherein the source and drain form a Schottky barrier to the lower and upper fin bodies.
2. The FinFET device according to claim 1, wherein the lower and upper fin bodies are formed of the same material layer, the material layer comprsing at least one layer selected from the group consisting of a silicon (Si) layer, a germanium (Ge) layer, a silicon germanium (SiGe) layer, a silicon germanium carbide (SiGeC) layer, and a silicon carbide (SiC) layer.
3. The FinFET device according to claim 1, wherein the metal material layer is a metal suicide layer.
4. The FinFET device according to claim 3, wherein the metal silicide layer comprises at least one layer selected from the group consisting of a tantalum silicide (TaSi) layer, a titanium silicide (TiSi) layer, a tungsten silicide (WSi) layer, a nickel silicide (NiSi) layer, a cobalt silicide (CoSi) layer, a platinum silicide (PtSi) layer, an erbium silicide (ErSi) layer, a ytterbium silicide (YbSi) layer, a yttrium silicide (YSi) layer, a gadolinium silicide (GdSi) layer, a Terbium silicide (TbSi) layer, a dysprosium silicide (DySi) layer, a holmium silicide (HoSi) layer, a thulium silicide (TmSi) layer, a lutetium silicide (LuSi) layer, a palladium silicide (PdSi) layer, an osmium silicide (OsSi) layer, an iridium silicide (IrSi) layer, and a rhenium silicide (ReSi) layer.
5. The FinFET device according to claim 1, further comprising a gate spacer for covering the sidewalls of the gate structure.
6. A FinFET device comprising:
a lower fin body disposed on a substrate;
an upper fin body having first and second sidewalls extending upwardly from the lower fin body having third and fourth sidewalls;
a gate structure crossing over the upper fin body and covering an upper surface of the upper fin body and the first and second sidewalls;
a source and a drain disposed on sidewalls of the upper fin body adjacent to sidewalls of the gate structure, made of a metal material layer, and disposed on an upper surface of the lower fin body positioned at both sides of the upper fin body, wherein the source and drain form a Schottky barrier to the lower and upper fin bodies; and
wherein the first and second sidewalls of the upper fin body are self-aligned with the third and fourth sidewalls of the lower fin body, respectively.
7. The FinFET device according to claim 6, wherein the gate structure extends from the first and second sidewalls of the upper fin body to cover the sidewalls of the lower fin body adjacent to the first and second sidewalls of the upper fin body.
8. A FinFET device comprising:
a lower fin body disposed on a substrate;
an upper fin body having first and second sidewalls extending upwardly from the lower fin body having third and fourth sidewalls;
a source and a drain disposed on the first and second sidewalls of the fin body, made of a metal material layer, and disposed on an upper surface of the lower fin body positioned at both sides of the upper fin body, wherein the source and drain form a Schottky barrier to the lower and upper fin bodies;
a gate dielectric layer on the top surface of the upper fin body; and
a gate structure on the gate dielectric layer.
9. The FinFET device according to claim 8, wherein the first and second sidewalls of the upper fin body are self-aligned with the third and fourth sidewalls of the lower fin body, respectively.
10. The FinFET device according to claim 8, further comprising first and second gate spacers for covering the sidewalls of the gate structure.
11. The FinFET device according to claim 10, further comprising third and fourth gate spacers connecting with a portion of the source and drain.
12. A method of fabricating a FinFET device, comprising:
forming a preliminary fin body on a substrate;
forming a gate structure crossing over the preliminary fin body and covering an upper surface and sidewalls of the preliminary fin body;
forming a gate spacer covering sidewalls of the gate structure;
partially etching the preliminary fin body using the gate spacer and the gate structure as etching masks to form an upper fin body positioned under the gate structure and a lower fin body positioned at a lower level than the upper fin body, the upper fin body having exposed sidewalls; and
forming a source and a drain of a metal material layer forming a Schottky barrier to the upper and lower fin bodies on surfaces of the exposed sidewalls of the upper fin body and an upper surface of the lower fin body positioned at both sides of the upper fin body.
13. The method according to claim 12, wherein the preliminary fin body comprises at least one layer selected from the group consisting of a silicon (Si) layer, a germanium (Ge) layer, a silicon germanium (SiGe) layer, a silicon germanium carbide (SiGeC) layer, and a silicon carbide (SiC) layer.
14. The method according to claim 12, wherein the source and drain are formed of a metal silicide layer.
15. The method according to claim 14, wherein the metal silicide layer comprises at least layer one selected from the group consisting of a tantalum silicide (TaSi) layer, a titanium silicide (TiSi) layer, a tungsten silicide (WSi) layer, a nickel silicide (NiSi) layer, a cobalt silicide (CoSi) layer, a platinum silicide (PtSi) layer, an erbium silicide (ErSi) layer, a ytterbium silicide (YbSi) layer, a yttrium silicide (YSi) layer, a gadolinium silicide (GdSi) layer, a Terbium silicide (TbSi) layer, a dysprosium silicide (DySi) layer, a holmium silicide (HoSi) layer, a thulium silicide (TmSi) layer, a lutetium silicide (LuSi) layer, a palladium silicide (PdSi) layer, an osmium silicide (OsSi) layer, an iridium silicide (IrSi) layer, and a rhenium silicide (ReSi) layer.
16. The method according to claim 12, wherein forming the source and drain comprises:
forming a metal layer on the surface of the substrate having the lower and upper fin bodies;
heat-treating the substrate having the metal layer to react the lower and upper fin bodies with the metal layer; and
removing an unreacted portion of the metal layer.
17. The method according to claim 12, wherein the source and drain are self-aligned with the sidewalls of the gate structure, or overlap the gate structure.
18. The method according to claim 12, further comprising forming a gate dielectric layer between the preliminary fin body and the gate structure.
19. A method of fabricating a FinFET device, comprising:
forming a fin body on a substrate;
forming a sacrificial mask crossing over the fin body and covering an upper surface and sidewalls of the fin body;
forming a source and a drain of a metal material layer forming a Schottky barrier to the fin body on surfaces of the fin body positioned at both sides of the sacrificial mask;
forming an insulating pattern surrounding sidewalls of the sacrificial mask and covering the fin body;
removing the sacrificial mask to form an opening for exposing a portion of the fin body; and
forming a gate structure covering the exposed fin body.
20. The method according to claim 19, wherein the fin body comprises at leat one layer selected from the group consisting of a silicon (Si) layer, a germanium (Ge) layer, a silicon germanium (SiGe) layer, a silicon germanium carbide (SiGeC) layer, and a silicon carbide (SiC) layer.
21. The method according to claim 19, wherein the source and drain are formed of a metal silicide layer.
22. The method according to claim 21, wherein the metal silicide layer comprises at least one layer selected from the group consisting of a tantalum silicide (TaSi) layer, a titanium silicide (TiSi) layer, a tungsten silicide (WSi) layer, a nickel silicide (NiSi) layer, a cobalt silicide (CoSi) layer, a platinum silicide (PtSi) layer, an erbium silicide (ErSi) layer, a ytterbium silicide (YbSi) layer, a yttrium silicide (YSi) layer, a gadolinium silicide (GdSi) layer, a Terbium silicide (TbSi) layer, a dysprosium silicide (DySi) layer, a holmium silicide (HoSi) layer, a thulium silicide (TmSi) layer, a lutetium silicide (LuSi) layer, a palladium silicide (PdSi) layer, an osmium silicide (OsSi) layer, an iridium silicide (IrSi) layer, and a rhenium silicide (ReSi) layer.
23. The method according to claim 19, wherein forming the soure and drain comprises:
forming a metal layer on the substrate having the sacrificial layer;
heat-treating the substrate having the metal layer to react the fin body with the metal layer; and
removing an unreacted portion of the metal layer.
24. The method according to claim 19, wherein the insulating pattern is formed of a material layer having an etching selectivity with respect to the sacrificial mask.
25. The method according to claim 19, wherein the gate structure is formed of a gate insulating layer and a gate electrode, which are sequentially stacked.
26. The method according to claim 25, wherein the gate insulating layer is formed using a chemical vapor deposition method or an atomic layer depositoin method, and the gate electrode comprises at least one layer selected from the group consisting of a siliocn layer, a metal layer, and a metal silicide layer.
27. The method according to claim 19, wherein the source and drain are self-aligned with sidewalls of the gate structure, or overlap the gate structure.
28. The method according to claim 19, wherein forming the sacrificial mask comprises:
forming a preliminary sacrificial mask crossing over the fin body and covering an upper surface and sidewalls of the fin bdy, the preliminary sacrificial mask having a first width; and
isotropically etching the preliminary sacrificial mask to cross over the fin body having a second width smaller than the first width.
29. A method of fabricating a FinFET device, comprising:
forming a lower fin body on a substrate;
forming an upper fin body having first and second sidewalls extending upwardly from the lower fin body having third and fourth sidewalls;
forming a gate dielectric layer on the top surface of the upper fin body;
forming a source and a drain on the first and second sidewalls of the fin body, made of a metal material layer, and on an upper surface of the lower fin body positioned at both sides of the upper fin body, wherein the source and drain form a Schottky barrier to the lower and upper fin bodies; and
forming a gate structure on the gate dielectric layer.
30. The method according to claim 28, wherein the first and second sidewalls of the upper fin body are self-aligned with the third and fourth sidewalls of the lower fin body, respectively.
31. The method according to claim 28, further comprising forming first and second gate spacers for covering the sidewalls of the gate structure.
32. The method according to claim 28, further comprising forming third and fourth gate spacers connecting with a portion of the source and drain.