1. A turbocharged engine system, comprising:
an engine;
an air inlet to provide air to the engine;
an air bypass valve that vents air from the air inlet;
a turbocharger disposed in the air inlet;
a catalytic converter located downstream of the engine; and
an air bypass valve controller to open the air bypass valve when an exhaust gas temperature entering the catalytic converter exceeds a predetermined temperature.
2. The turbocharged engine system of claim 1, wherein the air bypass valve controller predicts the exhaust gas temperature.
3. The turbocharged engine system of claim 2, further comprising at least one sensor,
wherein the air bypass valve controller predicts the exhaust gas temperature based on information received from the at least one sensor.
4. The turbocharged engine system of claim 1, further comprising an exhaust gas temperature sensor,
wherein the exhaust gas temperature sensor measures the exhaust gas temperature and transmits the measured exhaust gas temperature to the air bypass controller.
5. The turbocharged engine system of claim 1, wherein the turbocharger is configured to rotate faster to compensate for pressure lost by opening the air bypass valve.
6. The turbocharged engine system of claim 1, further comprising a fuel injection system,
wherein the fuel injection system is configured to provide fuel to the engine in a lean state when the air bypass valve is opened.
7. A method for cooling exhaust from a turbocharged engine, comprising the steps of:
determining the temperature of an engine exhaust gas;
determining if the predicted exhaust gas temperature is above a predetermined temperature; and
venting pressurized intake air upstream of the turbocharger if the predicted temperature is above the predetermined temperature.
8. The method of claim 7, further comprising spinning the turbocharger to maintain air pressure upstream of the turbocharger while the pressurized air is vented to the atmosphere.
9. The method of claim 7, wherein the step of determining the exhaust gas temperature includes measuring the exhaust gas temperature.
10. The method of claim 7, wherein the step of determining the exhaust gas temperature includes predicting the exhaust gas temperature according to engine operating conditions.
11. The method of claim 7, further comprising:
providing a fuel air mixture to the engine during the step of venting.
12. The method of claim 7, wherein the pressurized air is vented to the atmosphere.
13. The method of claim 7, further comprising:
measuring a boost pressure;
determining if the boost pressure is falling; and
reducing the venting of the pressurized air if the boost pressure is determined to be falling.
14. The method of claim 7, further comprising:
measuring a boost pressure;
determining if the boost pressure exceeds a predetermine boost pressure limit; and
venting the pressurized air if the measured boost pressure exceeds the predetermined boost pressure limit.
15. The method of claim 14, wherein the venting includes opening an air bypass valve upstream of the engine and downstream of the turbocharger.
16. The method of claim 7, further comprising:
determining if the determined exhaust gas temperature is below a predetermined lower temperature limit; and
closing an air bypass valve if the determined exhaust gas temperature is below the predetermined lower temperature limit.
17. A turbocharged engine system, comprising:
an engine;
an air inlet to provide air to the engine;
a turbocharger having an impeller to pressurize air entering through the air inlet to the engine and a turbine to convert exhaust gas into rotational energy to spin the impeller;
a bypass valve disposed between the impeller and the engine, the bypass valve configured to selectively vent the pressurized air; and
a bypass controller configured to determine exhaust gas temperature and to open the bypass valve when the engine exhaust temperature exceeds a predetermined temperature.
18. The turbocharged engine system of claim 17, wherein the air bypass valve vents the pressurized air to atmosphere when the engine exhaust gas temperature exceeds a predetermined temperature.
19. The turbocharged engine system of claim 17, wherein:
the bypass controller is configured to determine if a turbine overpressure event is occurring; and wherein
the bypass controller opens the bypass valve when the turbine overpressure event occurs.
20. The turbocharged engine system of claim 19, wherein the air bypass valve is configured to vent the pressurized air to a portion of the air inlet upstream of the turbocharger during the turbine overpressure event.
21. The turbocharged engine system of claim 17, wherein the engine is configured to maintain a lean operating state when the engine operates at a high engine output to maintain a predetermined exhaust gas temperature.
22. The turbocharged engine system of claim 21, wherein the engine is configured to operate in an enriched state after the air bypass valve is opened and the engine exhaust temperature is greater than the predetermined exhaust gas temperature.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor structure comprising:
a single crystalline material layer located in a substrate;
a plurality of semiconductor fins located directly on a first portion of a top surface of said single crystalline material layer;
at least one dielectric material portion located directly on a second portion of said top surface of said single crystalline material layer and laterally between each semiconductor fin of said plurality of semiconductor fins;
a gate structure including a vertical stack of a gate dielectric and a gate electrode and contacting a top surface of each of said at least one dielectric material portion and sidewalls of said plurality of semiconductor fins; and
a gate spacer laterally contacting sidewalls of said gate structure and sidewalls of said at least one dielectric material portion and a third portion of said top surface of said single crystalline material layer.
2. The semiconductor structure of claim 1, wherein all sidewall surfaces of said at least one dielectric material portion are vertically coincident with sidewalls of said gate structure or sidewalls of said plurality of semiconductor fins.
3. The semiconductor structure of claim 1, further comprising:
a source region overlying a fourth portion of said top surface of single crystalline material layer and in contact with first sidewalls of said plurality of semiconductor fins; and
a drain region overlying a fifth portion of said topmost surface of said single crystalline material layer and in contact with second sidewalls of said plurality of semiconductor fins.
4. The semiconductor structure of claim 3, wherein bottom surfaces of said source region and said drain region are located below a horizontal plane including at least one top surface of said at least one dielectric material portion.
5. The semiconductor structure of claim 3, wherein said at least one dielectric material portion is laterally spaced from said source region and said drain region by a width of said gate spacer.
6. The semiconductor structure of claim 3, wherein each of said source region and said drain region is single crystalline and is epitaxially aligned to a single crystalline material within said single crystalline material layer.
7. The semiconductor structure of claim 6, wherein said source region and said drain region comprise a doped semiconductor material having a lattice constant that is different from a lattice constant of said single crystalline material, and apply a stress to said plurality of semiconductor fins.
8. The semiconductor structure of claim 3, wherein each of said source region and said drain region is in physical contact with said top surface of said single crystalline material layer.
9. The semiconductor structure of claim 3, further comprising:
a source-side intrinsic semiconductor material portion in contact with said fourth portion of said top surface of said single crystalline material layer and a bottom surface of said source region; and
a drain-side intrinsic semiconductor material portion in contact with said fifth portion of said top surface of said single crystalline material layer and a bottom surface of said drain region.
10. The semiconductor structure of claim 1, wherein interfaces between said plurality of semiconductor fins and said source region and interfaces between said plurality of semiconductor fins and said drain region are vertically coincident with outer sidewalls of said gate spacer.
11. The semiconductor structure of claim 1, wherein said at least one dielectric material portion has a bottommost surface that is coplanar with a bottommost surface of each semiconductor fin of said plurality of semiconductor fins.
12. The semiconductor structure of claim 1, wherein said single crystalline material layer is a rare-earth oxide material.
13. The semiconductor structure of claim 12, wherein said rare-earth oxide comprises a rare earth element selected from La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu.