1. A circuit analysis device for acquiring a signal delay time at a Register Transfer level of a circuit including multiple components, comprising:
a storage unit for storing:
connection information including information about kinds and numbers of said multiple components and connection relations among components;
delay information including information about a delay time of a discrete component and a chain delay time which is a delay time in a case in which a chain delay effect is generated by a connection with another component about each kind of said multiple components; and
chain effect propagating component information including information about kinds of chain effect propagating components which are components for transmitting the chain delay effect, and
a data processing unit for:
when inputting said connection information, said delay information about each kind of said multiple components and said chain effect propagating component information, storing these kinds of information in said storage unit;
referring to information stored in said storage unit;
performing a total delay time calculation process of sequentially adding delay times of components along a signal path in said circuit; and
determining that a chain effect propagating component is halfway through a signal path in a total delay time calculation process, examining a connection relation between components that precede and follow said chain effect propagating component and determining a delay time of the component that follows said chain effect propagating component that corresponds to the connection relations.
2. The circuit analysis device according to claim 1, wherein:
determining that a chain effect propagating component is connected halfway through said signal path in said total delay time calculation process, said data processing unit determines whether or not a connection between components that precede and follow said chain effect propagating component is in a connection relation for generating the chain delay effect so as to replace the delay time of the component that follows said chain effect propagating component by the chain delay time in a case of being in the connection relation, and to replace the delay time of the component that follows said chain effect propagating component by the delay time of the discrete component in a case of not being in the connection relation.
3. The circuit analysis device according to claim 1, wherein said chain effect propagating component is a component for inputting and outputting signals via a bus.
4. The circuit analysis device according to claim 1, wherein:
said chain effect propagating component includes multiple paths leading from an input to an output and has a property to propagate or not to propagate the chain delay effect for each of said multiple paths; and
said chain effect propagating component information includes information about whether or not to propagate the chain delay effect for each of said multiple paths of said chain effect propagating component.
5. A circuit analysis device for acquiring a signal delay time at a Register Transfer level of a circuit including multiple components, comprising:
a storage unit for storing:
connection information including information about kinds and numbers of said multiple components and connection relations among components;
delay information including information about a delay time of a discrete component and a chain delay time which is a delay time in a case in which a chain delay effect is generated by a connection with another component about each kind of said multiple components; and
chain effect propagating component information including information about kinds of chain effect propagating components which are components for passing the chain delay effect, and
a data processing unit for:
when inputting information about behavioral description of said circuit, said delay information about each kind of said multiple components and said chain effect propagating component information, storing these kinds of information in said storage unit;
performing a synthesis process of generating said connection information from said information about behavioral description and storing said connection information in said storage unit;
referring to information stored in said storage unit;
performing a total delay time calculation process of sequentially adding delay times of components along a signal path in said circuit; and
determining that a chain effect propagating component is halfway through a signal path in said total delay time calculation process, examining a connection relation between components that precede and follow said chain effect propagating component and determining the delay time of the component that follows said chain effect propagating component that corresponds to the connection relations.
6. The circuit analysis device according to claim 5, wherein:
information about a performance specification of said circuit is stored in said storage unit; and
said data processing unit compares a result of said total delay time calculation process with said performance specification, performs said synthesis process and said total delay time calculation process again in a case in which said performance specification is not satisfied, and makes an output unit output a result of said synthesis process in a case in which the performance specification is satisfied.
7. The circuit analysis device according to claim 5, wherein:
determining that a chain effect propagating component is connected halfway through said signal path in said total delay time calculation process, said data processing unit determines whether or not a connection between components that precede and follow said chain effect propagating component is in a connection relation for generating the chain delay effect so as to replace the delay time of the component that follows said chain effect propagating component by the chain delay time in a case of being in the connection relation, and to replace the delay time of the component that follows said chain effect propagating component by the delay time of the discrete component in a case of not being in the connection relation.
8. The circuit analysis device according to claim 5, wherein said chain effect propagating component is a component for inputting and outputting signals via a bus.
9. The circuit analysis device according to claim 5, wherein:
said chain effect propagating component includes multiple paths leading from an input to an output and has a property to propagate or not to propagate the chain delay effect for each of said multiple paths; and
said chain effect propagating component information includes information about whether or not to propagate the chain delay effect for each of said multiple paths of said chain effect propagating component.
10. A circuit analysis method by a circuit analysis device for acquiring a signal delay time at a Register Transfer level of a circuit including multiple components, comprising the steps of:
storing as machine readable information in a machine storage unit, connection information including information about kinds and numbers of said multiple components and connection relations among components; delay information including information about a delay time of a discrete component and a chain delay time which is a delay time in a case in which a chain delay effect is generated by a connection with another component about each kind of said multiple components; and chain effect propagating component information including information about kinds of chain effect propagating components which are components for transmitting the chain delay effect, and
referring to information stored in said storage unit;
performing a total delay time calculation process of sequentially adding delay times of the components along a signal path in said circuit; and
determining that a chain effect propagating component is halfway through a signal path in said total delay time calculation process, examining a connection relation between components that precede and follow said chain effect propagating component and determining a delay time of the component that follows said chain effect propagating component that corresponds to the connection relations.
11. The circuit analysis method according to claim 10, wherein:
determining that a chain effect propagating component is connected halfway through the signal path in said total delay time calculation process, it is determined whether or not a connection between components that precede and follow said chain effect propagating component is in a connection relation for generating the chain delay effect so as to replace the delay time of the component that follows said chain effect propagating component by the chain delay time in a case of being in the connection relation, and to replace the delay time of the component that follows said chain effect propagating component by the delay time of the discrete component in a case of not being in the connection relation.
12. The circuit analysis method according to claim 10, wherein said chain effect propagating component is a component for inputting and outputting signals via a bus.
13. The circuit analysis method according to claim 10, wherein:
said chain effect propagating component includes multiple paths leading from an input to an output and has a property to propagate or not to propagate the chain delay effect for each of said multiple paths; and
said chain effect propagating component information includes information about whether or not to propagate the chain delay effect for each of said multiple paths of said chain effect propagating component.
14. A circuit analysis method by a circuit analysis device for acquiring a signal delay time at a Register Transfer level of a circuit including multiple components, comprising the steps of:
storing machine readable information in a machine storage unit, information about behavioral description of said circuit; delay information including information about a delay time of a discrete component and a chain delay time which is a delay time in a case in which a chain delay effect is generated by a connection with another component about each kind of said multiple components; and chain effect propagating component information including information about kinds of chain effect propagating components which are components for passing the chain delay effect, and
performing a synthesis process of generating connection information including information about kinds and numbers of said multiple components and connection relations among the components from said information about behavioral description and storing said connection information in said storage unit;
referring to information stored in said storage unit;
performing a total delay time calculation process of sequentially adding delay times of components along a signal path in said circuit; and
determining that a chain effect propagating component is halfway through a signal path in said total delay time calculation process, examining a connection relation between components that precede and follow said chain effect propagating component and determining the delay time of the component that follows said chain effect propagating component that corresponds to the connection relations.
15. The circuit analysis method according to claim 14, wherein:
information about a performance specification of said circuit is stored in said storage unit; and
a result of said total delay time calculation process is compared with said performance specification so that said synthesis process and said total delay time calculation process are performed again in a case in which said performance specification is not satisfied, and a result of said synthesis process is outputted by an output unit in a case in which said performance specification is satisfied.
16. The circuit analysis method according to claim 14, wherein:
determining that a chain effect propagating component is connected halfway through the signal path in said total delay time calculation process, it is determined whether or not a connection between components that precede and follow said chain effect propagating component is in a connection relation for generating the chain delay effect so as to replace the delay time of the component that follows said chain effect propagating component by the chain delay time in a case of being in the connection relation, and to replace the delay time of the component that follows said chain effect propagating component by the delay time of the discrete component in a case of not being in the connection relation.
17. The circuit analysis method according to claim 14, wherein said chain effect propagating component is a component for inputting and outputting signals via a bus.
18. The circuit analysis method according to claim 14, wherein:
said chain effect propagating component includes multiple paths leading from an input to an output and has a property to propagate or not to propagate the chain delay effect for each of said multiple paths; and
said chain effect propagating component information includes information about whether or not to propagate the chain delay effect for each of said multiple paths of said chain effect propagating component.
19. A recording medium including a computer-readable program recorded therein for acquiring a signal delay time at a Register Transfer level of a circuit including multiple components, the program causing the computer to execute a process comprising the steps of:
storing in a storage unit, connection information including information about kinds and numbers of said multiple components and connection relations among components; delay information including information about a delay time of a discrete component and a chain delay time which is a delay time in a case in which a chain delay effect is generated by a connection with another component about each kind of said multiple components; and chain effect propagating component information including information about kinds of chain effect propagating components which are components for transmitting the chain delay effect, and
referring to information stored in said storage unit;
performing a total delay time calculation process of sequentially adding delay times of the components along a signal path in said circuit; and
determining that a chain effect propagating component is halfway through a signal path in said total delay time calculation process, examining a connection relation between components that precede and follow said chain effect propagating component and determining a delay time of the component that follows said chain effect propagating component that corresponds to the connection relations.
20. The recording medium having a program recorded therein according to claim 19, the program causing the computer to further execute the steps of:
determining that a chain effect propagating component is connected halfway through the signal path in said total delay time calculation process, determining whether or not a connection between components that precede and follow said chain effect propagating component is in a connection relation for generating the chain delay effect; and
replacing the delay time of the component that follows said chain effect propagating component by the chain delay time in a case in which the connection is in the connection relation for generating the chain delay effect, and replacing the delay time of the component that follows said chain effect propagating component by the delay time of the discrete component in a case in which the connection is not in the connection relation for generating the chain delay effect.
21. The recording medium including a program recorded therein according to claim 19, wherein said chain effect propagating component is a component for inputting and outputting signals via a bus.
22. The recording medium including a program recorded therein according to claim 19, wherein:
said chain effect propagating component includes multiple paths leading from an input to an output and has a property to propagate or not to propagate the chain delay effect for each of said multiple paths; and
said chain effect propagating component information includes information about whether or not to propagate the chain delay effect for each of said multiple paths of said chain effect propagating component.
23. A recording medium including a computer-readable program recorded therein for acquiring a signal delay time at a Register Transfer level of a circuit including multiple components, the program causing the computer to execute a process comprising the steps of:
storing in a storage unit, information about behavioral description of said circuit; delay information including information about a delay time of a discrete component and a chain delay time which is a delay time in a case in which a chain delay effect is generated by a connection with another component about each kind of said multiple components; and chain effect propagating component information including information about kinds of chain effect propagating components which are components for passing the chain delay effect, and
performing a synthesis process of generating connection information including information about kinds and numbers of said multiple components and connection relations among the components from said information about behavioral description and storing said connection information in said storage unit;
referring to information stored in said storage unit;
performing a total delay time calculation process of sequentially adding delay times of components along a signal path in said circuit; and
determining that a chain effect propagating component is halfway through a signal path in said total delay time calculation process, examining a connection relation between components that precede and follow said chain effect propagating component and determining the delay time of the component that follows said chain effect propagating component that corresponds to the connection relations.
24. The recording medium including a program recorded therein according to claim 23, the program causing the computer to further execute the steps of:
storing information about a performance specification of said circuit in said storage unit; and
comparing a result of said total delay time calculation process with said performance specification, performing said synthesis process and said total delay time calculation process again in a case in which said performance specification is not satisfied, and making an output unit output a result of said synthesis process in a case in which said performance specification is satisfied.
25. The recording medium having a program recorded therein according to claim 23, the program causing the computer to further execute the steps of:
determining that a chain effect propagating component is connected halfway through the signal path in said total delay time calculation process, determining whether or not a connection between components that precede and follow said chain effect propagating component is in a connection relation for generating the chain delay effect; and
replacing the delay time of the component that follows said chain effect propagating component by the chain delay time in a case in which the connection is in the connection relation for generating the chain delay effect, and replacing the delay time of the component that follows said chain effect propagating component by the delay time of the discrete component in a case in which the connection is not in the connection relation for generating the chain delay effect.
26. The recording medium including a program recorded therein according to claim 23, wherein said chain effect propagating component is a component for inputting and outputting signals via a bus.
27. The recording medium including a program recorded therein according to claim 23, wherein:
said chain effect propagating component includes multiple paths leading from an input to an output and has a property to propagate or not to propagate the chain delay effect for each of said multiple paths; and
said chain effect propagating component information includes information about whether or not to propagate the chain delay effect for each of said multiple paths of said chain effect propagating component.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of producing maraging steel and controlling the growth of oxide and titanium nitride inclusions in the maraging steel by the addition of a controlled amount of Mg added to a consumable electrode which is subjected to vacuum arc remelting, the maraging steel exhibiting improved fatigue strength containing from not less than 0.3 mass % to not more than 2.0 mass % of Ti, and from more than zero to less than 15ppm of Mg, less than 10 ppm oxygen and less than 15 ppm nitrogen which method comprises:
producing a consumable electrode wherein the consumable electrode contains oxide inclusions and titanium nitride inclusions and the consumable electrode is subjected to vacuum arc remelting by casting a molten steel which has been melted under vacuum, the consumable electrode containing Mg, and non-metallic inclusions comprising oxide inclusions and titanium nitride inclusions, which titanium nitride inclusions have a nucleus of MgO, wherein the total of all Mg present is not less than 5 ppm; and
subsequently subjecting the consumable electrode to vacuum arc remelting to control the growth of the oxide inclusions and the titanium nitride inclusions, whereby the titanium nitride inclusions and the nucleus of MgO in the titanium nitride inclusions are decomposed so that the Mg content in the maraging steel which is produced by the vacuum arc remelting is reduced from the Mg content in the consumable electrode due to vaporization so that the Mg content in the maraging steel is made to be less than the Mg content in the consumable electrode, wherein the maraging steel contains the titanium nitride inclusions having a size of not more than 15 \u03bcm in maximum length and the oxide inclusions having a size of not more than 20 \u03bcm in maximum length, and wherein
the oxide inclusions comprise spinel form inclusions and alumina inclusions in which a content of the spinel form inclusions having a size of not less than 10 \u03bcm in length divided by a total content of the spinel form inclusions having a size of not less than 10 \u03bcm in length plus the alumina inclusions having a size of not less than 10 \u03bcm in length is more than 0.33.
2. A method of producing maraging steel according to claim 1, wherein the molten steel for casting has been produced by a vacuum induction melting process.
3. A method of producing maraging steel according to claim 1, wherein a maraging steel product obtained by the vacuum arc remelting is subjected to plastic working to produce a thin strip having a thickness of not more than 0.5 mm.
4. Maraging steel comprising, by mass, at least, from not less than 0.3% to not more than 2.0% Ti, from more than zero to less than 15 ppm of Mg, less than 10 ppm oxygen and less than 15 ppm nitrogen, wherein
the maraging steel contains titanium nitride inclusions having a size of not more than 15 \u03bcm in maximum length and oxide inclusions having a size of not more than 20 \u03bcm in maximum length, and wherein
the oxide inclusions comprise spinel form inclusions and alumina inclusions in which a content of the spinel form inclusions having a size of not less than 10 \u03bcm in length divided by a total content of the spinel form inclusions having a size of not less than 10 \u03bcm in length plus the alumina inclusions having a size of not less than 10 \u03bcm in length is more than 0.33.
5. Maraging steel according to claim 4, consisting essentially of, by mass, not more than 0.01% C (carbon), 8.0 to 22.0% Ni, 5.0 to 20.0% Co, 2.0 to 9.0% Mo, from not less than 0.3% to not more than 2.0% Ti, not more than 1.7% Al, from more than zero to less than 10 ppm Mg, less than 10ppm oxygen, less than 15 ppm nitrogen, and the balance of Fe and incidental impurities.
6. A thin strip which is made from maraging steel as defined in claim 4, and which has a thickness of not more than 0.5 mm.
7. A thin strip which is made from maraging steel as defined in claim 5, and which has a thickness of not more than 0.5 mm.
8. The method according to claim 1, wherein a thin strip having a thickness of not more than 0.5 mm is produced by plastic working the maraging steel after the vacuum arc remelting.
9. The method according to claim 3, wherein the thin strip having a thickness of not more than 0.5 mm is a component of a continuously variable transmission.
10. The method according to claim 8, wherein the thin strip having a thickness of not more than 0.5 mm is a component of a continuously variable transmission.
11. A component of a continuously variable transmission, which is made of the thin strip having a thickness of not more than 0.5 mm as defined in claim 6.
12. A component of continuously variable transmissions, which is made of the thin strip having a thickness of not more than 0.5 mm as defined in claim 7.
13. A method of producing maraging steel according to claim 1, wherein the amount of Mg is from more than 0 to less than 10 ppm in the maraging steel and wherein the consumable electrode contains from 10 to 150 ppm Mg.
14. A method of producing maraging steel according to claim 1, wherein the consumable electrode contains from 5 to not more than 300 ppm Mg.
15. A method of producing maraging steel according to claim 1, wherein the consumable electrode contains from 5 to not more than 250 ppm Mg.
16. A method of producing maraging steel according to claim 1, wherein the maraging steel consists essentially of, by mass, not more than 0.01% C (carbon), 8.0 to 22.0% Ni, 5.0 to 20.0% Co, 2.0 to 9.0% Mo, from not less than 0.3% to not more than 2.0% Ti, not more than 1.7% Al, from more than zero to less than 10 ppm Mg, less than 10 ppm oxygen, less than 15 ppm nitrogen, and the balance of Fe and incidental impurities.
17. A method of producing maraging steel according to claim 13, wherein the maraging steel compounds by mass from more than 0 to 5 ppm Mg.
18. Maraging steel according to claim 4, wherein the maraging steel comprises by mass, from more than 0 to 5 ppm Mg.
19. A method according to claim 13, wherein a maraging steel product obtained by the vacuum arc remelting is subjected to plastic working to produce a thin strip having a thickness of not more than 0.5 mm.
20. A method according to claim 19, wherein the thin strip having a thickness of not more than 0.5 mm is a component of a continuously variable transmission.