1. A drill and a screw system for use in orthopedic surgery wherein the screw is cannulated and has a proximal torque driving head and a distal threaded portion, the screw head having an area defining a maximum screw diameter and having a convexly rounded distal area adjacent the area defining the maximum screw diameter, and the drill comprises a shaft, a handle and a drill head, where the drill head has a modified bulb shape extending along a longitudinal axis from the distal tip to a proximal portion and the drill head is narrowest at the distal most end and has a first area of a first diameter, wherein the drill head includes from 2 to 6 cutting flutes that each define a cutting edge about the longitudinal axis and the cutting flutes flaring from about the first diameter area to at least a second area having a second diameter, and the second diameter is greater than the first diameter, and wherein a third diameter of the drill head is the maximum diameter of the drill head and the cutting edges of the cutting flutes end at the third diameter of the drill head whereby the third diameter is slightly larger than or corresponds to the maximum screw diameter which is implanted using the drill of the system.
2. The drill and the screw system as set forth in claim 1 wherein the drill head includes between 3 and 5 cutting flutes.
3. The drill and the screw system as set forth in claim 2 in which the increase in diameter between the first and the second area is a linear increase along the longitudinal axis.
4. The drill and the screw system as set forth in claim 3 wherein a third area having the third diameter is proximal to the second area.
5. The drill and the screw system as set forth in claim 4 wherein there is an increase in the diameter from the second area to the third area which is not a linear increase along the longitudinal axis.
6. The drill and the screw system as set forth in claim 5 wherein the proximal torque driving head has a convexly rounded distal portion and the shaft has a distal area of cancellous threads adjacent a more proximal area of shaft without threads.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A process for forming trench isolation in a semiconductor memory device, said process comprising the steps of:
etching a first trench to a first level, into a conductively doped portion of a semiconductor assembly;
etching a second trench to a second level, into said conductively doped portion of said semiconductor assembly, including second trench spanning said first trench, said step of etching a second trench simultaneously etching said first trench to a third level that corresponds to said second level;
forming isolation material in said first and second trenches;
forming conductive wells having a common boundary but have opposite conductivity type within said conductively doped portion said isolation material interposed at said common boundary of said conductive wells.
2. The process as recited in claim 1, wherein said step of etching a first trench comprises etching said first trench to a width that is wider than a width of said second trench.
3. The process as recited in claim 1, wherein said step of etching a second trench comprises etching said second trench to consume a portion of each said conductive well at said common boundary.
4. A process for forming trench isolation in a semiconductor memory device, said process comprising the steps of:
etching an inter-well trench to a first inter-well trench depth, into a conductively doped portion of a semiconductor assembly;
etching intra-well trenches to an intra-well trench depth on opposing sides of said inter-well trench, while simultaneously etching said inter-well trench to a second inter-well trench depth;
forming isolation material in said intra-well trenches and said inter-well trench;
forming conductive wells having a common boundary but having opposite conductivity type within said conductively doped region, said isolation material interposed at said common boundary of said conductive wells.
5. The process as recited in claim 4, wherein said steps of etching an inter-well trench to a first inter-well trench depth and of simultaneously etching said inter-well trench to a second inter-well trench depth comprises etching said inter-well trench into a first and second stepped trench having said first step being wider than said second step.
6. The process as recited in claim 4, wherein said step of simultaneously etching said inter-well trench to a second inter-well trench depth comprises etching said inter-well trench to consume a portion of each said conductive well at said common boundary.
7. A process for forming trench isolation in a semiconductor memory device, said process comprising the steps of:
forming a photoresist material over a silicon substrate;
forming a photoresist pattern from said photoresist material to form a first, second and third level into said photoresist pattern, said first level defining active areas within said silicon substrate, said second level defining an intra-well width, an intra-well depth, a first inter-well width and a first inter-well depth, said third level defining a second inter-well width and a second inter-well depth;
etching said silicon substrate by transferring said photoresist pattern thereto to form an inter-well trench having an overall combined width and depth comprising said first inter-well width, said first inter-well depth, said second inter-well width and said second inter-well depth, said step of etching simultaneously forming intra-well trenches on opposing sides of said inter-well trench;
forming isolation material in said intra-well trenches and said inter-well trench;
forming conductive wells having a common boundary but having opposite conductivity type within said define active areas, said isolation material interposed at said common boundary of said conductive wells.
8. The process as recited in claim 7, wherein said step of forming a photoresist pattern comprises using gradient photolithography to impose a gradient exposure on said photoresist material.
9. The process as recited in claim 8, wherein said step of using gradient photolithography comprises implementing a gradient exposure by using a gradient mask so that a gradient exposure intensity corresponds to said first, second and third levels.
10. The process as recited in claim 7, wherein said step of forming a photoresist pattern comprises using masks in succession to form said photoresist pattern corresponding to said first, second and third levels.
11. A dual depth trench isolation structure for a semiconductor assembly comprising:
a first inter-well isolation structure having a first isolation trench depth;
a second inter-well isolation structure having a second isolation trench depth, said second isolation trench depth combining with said first isolation trench depth forming a dual depth trench containing said dual depth trench isolation structure comprising said first inter-well isolation structure and said second inter-well isolation structure, said first and second inter-well isolation structures comprising said dual depth trench isolation structure.
12. An intra-well and inter-well isolation structure for a semiconductor assembly comprising:
a first inter-well isolation structure having a first inter-well isolation trench depth;
a second inter-well isolation structure having a second inter-well isolation trench depth, said second inter-well isolation trench depth combining with said first inter-well isolation trench depth to form a dual depth trench containing a dual depth trench isolation structure comprising said first inter-well isolation structure and said second inter-well isolation structure;
a first intra-well isolation structure having a first isolation trench depth; and
a second intra-well isolation structure having a second isolation trench depth.
13. A dual depth trench isolation structure between active devices and conductive well regions of same conductivity type for a complimentary metal oxide semiconductor device comprising:
a first inter-well isolation structure having a first isolation trench depth;
a second inter-well isolation structure having a second isolation trench depth, said second isolation trench depth combining with said first isolation trench depth to form a dual depth trench containing said dual depth trench isolation structure comprising said first inter-well isolation structure and said second inter-well isolation structure, said dual depth trench isolation interposed at the boundary of an n-well conductive region and a p-well conductive region.
14. A dual depth trench isolation structure between active devices and conductive well regions of same conductivity type for a complimentary metal oxide semiconductor device comprising:
a first inter-well isolation structure having a first isolation trench depth;
a second inter-well isolation structure having a second isolation trench depth, said second isolation trench depth combining with said first isolation trench depth to form a dual depth trench containing said dual depth trench isolation structure comprising said first inter-well isolation structure and said second inter-well isolation structure, said dual depth trench isolation interposed at the boundary of an n-well conductive region and a p-well conductive region;
a first intra-well isolation structure having a first isolation trench depth, said first intra-well isolation structure interposed between a pair of p-channel transistors residing in said n-well region; and
a second intra-well isolation structure having a second isolation trench depth, said second intra-well isolation structure interposed between a pair of n-channel transistors residing in said p-well region.
15. A set of transistors of complimentary conductivity for a semiconductor device comprising:
a pair of p-channel transistors residing in an n-well region and separated by a first intra-well isolation structure entrenched at a first isolation trench depth;
a pair of n-channel transistors residing in a p-well region and separated by a second intra-well isolation structure entrenched a first isolation trench depth;
an inter-well isolation structure entrenched at a dual trench depth and interposed at a boundary of said n-well region and a p-well region;
wherein said dual trench depth of said inter-well isolation structure is stepped such that a first step resides above a second step to form said inter-well structure having a first step wider than an underlying second step, said first step being at substantially the same depth as said intra-well isolation structures and said second step being entrenched deeper than said first step.