1. An opto-electronic system comprising:
an optoelectronic module including a housing with an optical connector, a groove and a first electrical connector, and
a cage assembly for mounting on a host printed circuit board, the cage assembly including:
a faceplate having an opening through which the opto-electronic module passes,
a cage forming a cavity for receiving the opto-electronic module therein with the optical connector extending outwardly therefrom, and
a second electrical connector for mating with the first electrical connector,
wherein the cage assembly includes a stop extending into the opening for receipt in the groove during insertion of the opto-electronic module into the cage, enabling the opto-electronic module to pass into the cage unobstructed, the cage assembly further includes a stop projection for preventing other non-compatible opto-electronic modules with similar cross-sectional dimensions to the optoelectronic module, but without the groove, from becoming fully inserted into said cage assembly.
2. The opto-electronic system according to claim 1, wherein the stop extends from the faceplate.
3. The opto-electronic system according to claim 1, wherein the stop extends from the cage.
4. The opto-electronic system according to claim 1, wherein the stop extends from the host printed circuit board.
5. The opto-electronic system according to claim 1, wherein the stop extends from the second electrical connector.
6. The opto-electronic system according to claim 1, wherein the groove extends from a front end to a rear end of the opto-electronic module housing.
7. The opto-electronic system according to claim 6, wherein the groove extends along a corner of the opto-electronic module at an intersection of two perpendicular surfaces thereof.
8. The opto-electronic system according to claim 1, further comprising a finger extending from the housing for abutting said cage assembly, thereby preventing the opto-electronic module from becoming fully inserted into said cage assembly without displacing said finger away from said cage assembly.
9. The optoelectronic system according to claim 8, further comprising a camming surface on said finger, and a tab on said cage assembly for engaging said camming surface during insertion of the opto-electronic module into said cage assembly, thereby pivoting the finger away from said cage assembly.
10. The opto-electronic system according to claim 8, wherein the finger comprises a spring finger biased outwardly from the housing with an abutment surface on an outer free end thereof.
11. An opto-electronic system comprising:
an opto-electronic module including a housing and a first electrical connector, the housing including a first camming surface; and
a cage assembly for mounting on a host printed circuit board, the cage assembly including a faceplate, a cage forming a cavity with an opening for receiving the opto-electronic module, and a second electrical connector for mating with the first electrical connector, the cage assembly including a second camming surface extending therefrom into the cavity or the opening for engaging the first camming surface, whereby the first or second camming surface is rotated relative to the housing to a module insertion position enabling the opto-electronic module to be fully inserted into the cage assembly, thereby preventing non-compatible opto-electronic modules with similar cross-sectional dimensions to the opto-electronic module, but without the first camming surface, from becoming fully inserted into said cage assembly, in which the cage assembly includes a stop extending therefrom into the cavity to prevent non-compatible opto-electronic modules with similar cross-sectional dimensions to the opto-electronic module from being fully inserted into the cage assembly unless the second camming surface is rotated relative to the housing.
12. The opto-electronic system according to claim 11, wherein the first or second camming surface comprises a spring finger extendable between said opto-electronic module and said cage assembly.
13. The opto-electronic system according to claim 12, wherein the spring finger includes an abutment surface on an outer free end thereof for engaging cage assemblies or modules without the first or second camming surface, respectively.
14. The opto-electronic system according to claim 12, wherein the second camming surface comprises a ramp for engaging the first camming surface and gradually rotating the spring finger.
15. The opto-electronic system according to claim 12, wherein the spring finger includes the second camming surface and extends from said housing for abutting cage assemblies without the first camming surface.
16. The opto-electronic system according to claim 15, wherein the second camming surface comprises a ramp formed in the spring finger adjacent to the abutment surface for engaging the first camming surface and gradually rotating the spring finger away from the cage assembly.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A memory device, comprising:
a plurality of row lines and a plurality of column lines; and
a memory cell coupled to one of the plurality of column lines and to one of the plurality of row lines, the memory cell including:
a capacitor with a first plate coupled to a storage node of the memory cell; and
a CMOS-compatible non-volatile storage element comprising a first node coupled to the storage node, wherein the CMOS-compatible non-volatile storage element is configured to hold a charge corresponding to a binary value, and
wherein the CMOS-compatible non-volatile storage element is coupled to a control line; and
access circuitry coupled to the plurality of row lines, the plurality of column lines, and the control line, wherein the access circuitry is configured to toggle the control line to a control voltage during a read operation, and wherein the CMOS-compatible non-volatile storage element is configured to set, in response to the control voltage, a voltage on the storage node that is dependent on a value of the charge.
2. The memory device of claim 1, wherein the memory cell further comprises an access transistor including a word line gate, a first node, and a second node, wherein the word line gate is coupled to the one of the plurality of row lines, the first node is coupled to a second plate of the capacitor, and wherein the second node is coupled to the one of the plurality of column lines.
3. The memory device of claim 2, further comprising a voltage-dependent element arranged in series with the second node of the access transistor, wherein the plurality of column lines are configured to be pre-charged to a voltage level, with the pre-charge voltage allocated to the voltage-dependent element and to the capacitor in the memory cell, and wherein the allocation is based, at least in part, on the relative capacitances of the voltage-dependent element and the capacitor.
4. The memory device of claim 3, wherein the voltage-dependent element is the one of the plurality of column lines.
5. The memory device of claim 4, wherein the capacitance of the voltage-dependent element is inversely proportional to the pre-charge voltage allocated to the voltage-dependent element.
6. The memory device of claim 4, wherein at least one of the plurality of column lines is a diffused junction capacitor.
7. The memory device of claim 1, wherein the CMOS-compatible non-volatile storage element is a floating-gate transistor including a control gate coupled to the control line.
8. The memory device of claim 7, wherein a floating gate of the floating-gate transistor is configured to hold the charge, wherein the floating gate is further configured to cause, in response to the control voltage during the read operation, current to flow to the storage node, and wherein a level of the current is dependent on the charge.
9. The memory device of claim 1, wherein the CMOS-compatible non-volatile storage element is one of a Magnetoresistive Random Access Memory (MRAM) cell or a Phase-Change Memory (PCM) cell.
10. The memory device of claim 1, wherein the binary value comprises n bits and the resulting voltage is one of 2n possible voltages, where n is an integer.
11. A method of operating digital memory, the method comprising:
toggling, by access circuitry of a digital memory device during a read operation:
a control gate of a floating-gate transistor to a control voltage of a memory cell in the digital memory device, wherein the floating-gate transistor is configured to hold a charge corresponding to a binary value and to set, in response to the control voltage, a storage node of the memory cell to a voltage that is dependent on a value of the charge held on the floating-gate transistor, wherein the floating-gate transistor is coupled in series to a storage capacitor, wherein a first node of the floating-gate transistor is coupled to a first plate of the storage capacitor and wherein a second node of the floating gate transistor is coupled to a drain line;
a row line coupled to a word line gate of an access transistor of the memory cell to a select voltage, wherein the access transistor includes a first node coupled to a second plate of the storage capacitor and a second node coupled to a column line; and
the drain line to a supply voltage; and
sensing, by the access circuitry, a voltage resulting from said toggling, and
determining, based on the sensed voltage, the binary value.
12. The method of claim 11, wherein the binary value comprises n bits, where n is an integer.
13. An apparatus, comprising:
means for toggling, during a read operation:
a control line of a memory cell in a digital memory device to a control voltage;
a row line coupled to the memory cell to a select voltage; and
a drain line coupled to the memory cell to a supply voltage; and
means for sensing a voltage on a column line resulting from the toggling of the control, row, and drain lines;
wherein the memory cell further comprises a CMOS-compatible non-volatile storage element configured to toggle, in response to the control voltage, the voltage on a storage node of the memory cell, and wherein the voltage is dependent on a value of a held charge.
14. The apparatus of claim 13, wherein the voltage corresponds to a binary value comprising n bits, where n is an integer.
15. A system, comprising:
a digital memory controller configured to issue access commands to a digital memory device; and
the digital memory device, coupled to the controller, and including:
a plurality of row lines and a plurality of column lines;
a memory cell coupled to one of the plurality of column lines, to one of the plurality of row lines, and to a control line, wherein the memory cell comprises:
a capacitor with a first plate coupled to a storage node; and
a CMOS-compatible non-volatile storage element including a first node coupled to the storage node and configured to hold a charge corresponding to a binary value; and
access circuitry coupled to the plurality of row lines, the plurality of column lines, and the control line, wherein the access circuitry is configured to toggle the control line to a control voltage during a read operation, and wherein the CMOS-compatible non-volatile storage element is configured to toggle, in response to the control voltage, the storage node to a voltage that is dependent on a value of the charge.
16. The system of claim 15, wherein the memory cell further comprises an access transistor including a word line gate, a first node, and a second node, wherein the word line gate is coupled to the one of the plurality of row lines, wherein the first node is coupled to a second plate of the capacitor, and wherein the second node is coupled to the one of the plurality of column lines.
17. The system of claim 16, further comprising a voltage- dependent element arranged in series with the second node of the access transistor, wherein the access circuitry is further configured to precharge the plurality of column lines to a precharge voltage level, with a pre-charge voltage allocated to the voltage-dependent element and to the capacitor, and wherein the allocation is based, at least in part, on the relative capacitances of the voltage-dependent element and the capacitor.
18. The system of claim 17, wherein the voltage-dependent element is the one of the plurality of column lines.
19. The system of claim 18, wherein the capacitance of the voltage-dependent element is inversely proportional to the voltage allocated to the voltage-dependent element.
20. The system of claim 18, wherein at least one of the plurality of column lines is a diffused junction capacitor.
21. The system of claim 15, wherein the CMOS-compatible non-volatile storage element is a floating-gate transistor.
22. The system of claim 21, wherein a floating gate of the floating-gate transistor is configured to hold the charge, wherein the floating gate is further configured to cause, in response to the control voltage during the read operation, current to flow to the storage node, and wherein a level of the current is dependent on the charge.
23. The system of claim 15, wherein the CMOS-compatible non-volatile storage element is one of a Magnetoresistive Random Access Memory (MRAM) cell or a Phase-Change Memory (PCM) cell.
24. The system of claim 15, wherein the binary value comprises n bits, where n is an integer.
25. An article of manufacture, comprising a non-transitory computer-readable medium including a plurality of computer-readable hardware design language instructions, or compilation of the hardware design language instructions, wherein the hardware design language instructions specify an implementation of the memory device as set forth in claim 1 as an integrated circuit.
26. The article of manufacture of claim 25, wherein a hardware design language of the hardware design language instructions comprises either VHDL or Verilog.