1. A line driver, said line driver providing an output signal in response to an input signal, comprising:
a signal amplifier having an output terminal and connected in a negative feedback loop to receive said input signal; and
a bus connection network connected to said signal amplifier output terminal, wherein said bus connection network is inside said negative feedback loop when said line driver is transmitting said output signal, wherein said bus connection network connects said signal amplifier output terminal to a bus line, said bus connection network comprising:
a bus switch connected between said signal amplifier output terminal and said bus line; and
a feedback switch connected between said bus line and
a negative input terminal of said signal amplifier;
wherein said line driver includes a drive mode in which said bus switch connects said signal amplifier output terminal to said bus line and said feedback switch connects said bus line to said signal amplifier negative input terminal, and all other switches are open.
2. The line driver of claim 1, wherein said bus switch and said feedback switch comprise field effect transistors.
3. The line driver of claim 2, wherein the drain terminal of said bus switch is common with the drain terminal of said feedback switch, said drain terminals connected to said bus line.
4. A line driver, said line driver providing an output signal in response to an input signal, comprising:
a signal amplifier having an output terminal and connected in a negative feedback loop to receive said input signal;
a bus connection network connected to said signal amplifier output terminal, wherein said bus connection network is inside said negative feedback loop when said line driver is transmitting said output signal; and
a presettle circuit connected to settle said signal amplifier prior to said line driver transmitting said output signal onto said bus line, wherein said presettle circuit comprises:
a capacitor connected to said signal amplifier negative input terminal; and
a presettle switch connected between said signal amplifier output terminal and a negative input terminal of said signal amplifier.
5. The line driver of claim 4, wherein said capacitor is connected to said signal amplifier negative input terminal through a cap switch.
6. The line driver of claim 5, wherein said presettle switch and said cap switch are closed and all other switches are open when said line driver is operating in a presettle mode.
7. The line driver of claim 6, wherein said cap switch remains closed for a duration after said line driver has transitioned out of presettle mode.
8. A line driver, said line driver providing an output signal in response to an input signal, comprising:
a signal amplifier having an output terminal and connected in a negative feedback loop to receive said input signal;
a bus connection network connected to said signal amplifier output terminal, wherein said bus connection network is inside said negative feedback loop when said line driver is transmitting said output signal; and
an offset cancellation circuit connected to correct any offset current from said signal amplifier output, wherein said offset cancellation circuit comprises:
an offset amplifier having positive and negative input terminals and an output terminal, said offset amplifier positive input terminal biased with a voltage, said offset amplifier output terminal connected to said signal amplifier output terminal;
a capacitor connected to said offset amplifier negative input terminal; and
an offset switch connected between said offset amplifier negative input terminal and said offset amplifier output terminal.
9. The line driver of claim 8, further comprising an offset bias network connected to said signal amplifier, said bias network comprising:
a reference terminal to receive a reference voltage; a first switch connected between said reference terminal and said signal amplifier negative input; and
a second switch connected between said negative and positive inputs of said signal amplifier.
10. The line driver of claim 9, wherein said line driver includes an offset cancellation mode in which said first, second and offset switches are closed, and all other switches are open.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method in a sense amplifier, comprising:
coupling a first terminal of a sense transistor to a current mirror through a first coupling transistor, wherein a second terminal of the sense transistor is coupled to a floating gate of a floating gate memory device;
coupling a third terminal of the sense transistor to a current sink through a second coupling transistor; and
floating the first terminal and the second terminal of the sense transistor while programming and erasing the floating gate memory device.
2. The method of claim 1, wherein the sense transistor, the first coupling transistor and the second coupling transistor comprise MOS transistors, wherein a source of the first coupling transistor is connected to a drain of the sense transistor, wherein a source of the sense transistor is connected to a drain of the second coupling transistor, and wherein floating the sense transistor comprises applying a control voltage to control gates of the first coupling transistor and the second coupling transistor, wherein the control voltage is configured to turn off the first coupling transistor and the second coupling transistor.
3. The method of claim 2, further comprising configuring the control voltage to turn on the first coupling transistor and the second coupling transistor to read the floating gate memory device.
4. An apparatus, comprising:
a first transistor coupled to a floating gate of a memory device;
a second transistor coupled between the first transistor and a current mirror; and
a third transistor coupled between the first transistor and a current sink, wherein the second transistor and the third transistor each have a control terminal coupled to a control voltage, and wherein the control voltage is configured to turn the second transistor and the third transistor off when the memory device is being programmed, wherein the first transistor is protected from a programming voltage and a coupling coefficient of the memory device is increased.
5. The apparatus of claim 4, wherein the control voltage is configured to turn the second transistor and the third transistor on to read the memory device.
6. The apparatus of claim 4, wherein the first transistor comprises an MOS sense transistor having a first gate, a first drain and a first source, the second transistor comprises a first MOS coupling transistor having a second gate, a second drain and a second source and the third transistor comprises a second MOS coupling transistor having a third gate, a third drain and a third source, wherein the first gate is coupled to the floating gate of the memory device, the first drain is coupled to the second source and the first source is coupled to the third drain, wherein the second drain is coupled to the current mirror and the third source is coupled to the current source, and wherein the second gate and the third gate are coupled to the control voltage.
7. The apparatus of claim 4, wherein the first transistor, the second transistor and the third transistor comprise one side of a balanced sense amplifier, the apparatus further comprising:
a fourth transistor;
a fifth transistor coupled between the fourth transistor and the current mirror; and
a sixth transistor coupled between the fourth transistor and the current sink, wherein the fifth transistor and the sixth transistor each have a control terminal coupled to the control voltage, and wherein the control voltage is configured to turn the fifth transistor and the sixth transistor off when the memory device is being programmed.
8. The apparatus of claim 7, wherein the fourth transistor is matched to the first transistor, the fifth transistor is matched to the second transistor and the sixth transistor is matched to the third transistor.
9. The apparatus of claim 7, wherein the control voltage is configured to turn the fifth transistor and the sixth transistor on to read the memory device.
10. The apparatus of claim 7, wherein the fourth transistor comprises an MOS output transistor having a fourth gate, a fourth drain and a fourth source, the fifth transistor comprises a third MOS coupling transistor having a fifth gate, a fifth drain and a fifth source and the sixth transistor comprises a fourth MOS coupling transistor having a sixth gate, a sixth drain and a sixth source, wherein the fourth drain is coupled to the fifth source and the fourth source is coupled to the sixth drain, wherein the fifth drain is coupled to the current mirror and the sixth source is coupled to the current source, and wherein the fifth gate and the sixth gate are coupled to the control voltage.
11. An apparatus, comprising:
means for floating a source and a drain of a MOS sense transistor during memory program and erase operations;
means for reducing voltage-induced gate oxide stress in the MOS sense transistor during memory program and erase operations; and
means for reducing parasitic gate capacitance in the MOS sense transistor during the memory program and erase operations.