1. An apparatus
configured to read data from and write data to memory during normal operation of a memory system over a bus, wherein the apparatus comprises:
a test mode engine configured to control the bus responsive to an indication that a test mode of operation is desired, wherein the test mode engine is configured to provide the memory with a signal indicative of entering the test mode of operation over the bus; and
a built-in self test (BIST) engine configured to provide signals for testing the memory over the bus, wherein either the BIST engine or the test mode engine is configured to provide the signals for testing the memory to the bus.
2. The apparatus of claim 1, wherein the bus is not externally accessible.
3. The apparatus of claim 1, wherein the test mode engine is configured to provide the signal indicative of entering the test mode of operation to one or a subset of a plurality of devices in the memory.
4. The apparatus of claim 1, wherein the signal indicative of entering the test mode of operation comprises a combination of signals that would be illegal during normal operation of the memory.
5. The apparatus of claim 1, wherein the test mode engine is further configured to provide control of the bus to the BIST engine responsive, at least in part, to providing the signal indicative of entering the test mode of operation over the bus.
6. The apparatus of claim 5, wherein the BIST engine is further configured to provide control of the bus to the test mode engine responsive, at least in part, to providing the signals for testing the memory to the bus.
7. The apparatus of claim 1, wherein the bus comprises solder traces on a printed circuit board.
8. The apparatus of claim 1, wherein the memory comprises an array of DRAM memory cells.
9. The apparatus of claim 1, wherein the test mode engine is included in a logic controller that is configured to provide the signals for testing the memory to the bus, and wherein the apparatus comprises a memory controller configured to store test mode data received from the memory in a location accessible to the memory controller.
10. The apparatus of claim 1, wherein the test mode engine is further configured to cause repair of the memory during the test mode operation.
11. The apparatus of claim 1, wherein the test mode engine is configured to provide signals for testing the memory to the memory interface, and wherein test mode data including locations of failed memory are stored in the memory.
12. The apparatus of claim 11, wherein the signals for testing the memory comprise data, address, and command signals.
13. A method of repairing a memory system, the method comprising:
loading a plurality of test mode commands into a test mode engine of a memory controller;
providing a signal indicative of entering a test mode of operation from the test mode engine to a memory, wherein the signal is provided over a same bus used by the memory controller during normal operation of the memory;
entering test mode operation at the memory responsive to receipt of the signals indicative of entering the test mode operation; and
during test mode operation, receiving signals for testing of the memory from a built-in self test (BIST) engine in communication with andor included in the memory controller.
14. The method of claim 13, further comprising:
returning fail information responsive to the address and data signals for testing of the memory; and
causing the memory to be repaired, using the test mode engine and at least one of the plurality of test mode commands in accordance with the fail information.
15. The method of claim 13, further comprising:
storing fail information in the memory responsive, at least in part, to the address and data signals for testing of the memory.
16. The method of claim 13, further comprising:
preventing, with the test mode engine, the memory from exiting test mode operation.
17. The method of claim 13, wherein the signal indicative of entering a test mode of operation comprise a combination of signals including RAS, CAS, WE, or CS.
18. The method of claim 13, wherein the memory controller comprises a solid-state drive (SSD) controller.
19. The method of claim 13, wherein the memory comprises a plurality of DRAM memory cells.
20. The method of claim 13, wherein the test mode engine is configured to provide the signals for testing the memory to the memory.
21. The method of claim 13, wherein the fail information is stored in the memory controller.
22. The method of claim 13, wherein the fail information comprises fail locations.
23. A memory controller configured to read data from and write data to a memory during normal operation over a bus, wherein the controller comprises:
a test mode engine configured to provide a test mode command to the memory and receive test mode data responsive to the test mode command, wherein the test mode data includes data generated by the memory during a test mode.
24. The memory controller of claim 23, wherein the test mode engine is configured to mask a data field of the test mode command.
25. The memory controller of claim 23, wherein the test mode engine is configured to include a control bit in the test mode command to indicate whether to strobe for data.
26. The memory controller of claim 23, wherein the test mode engine is configured to setup one or more states of the test mode command prior to providing the test mode command to the memory.
27. The memory controller of claim 23, wherein the test mode data includes a number of, or location of available redundant memory locations, or both.
28. The memory controller of claim 23, wherein the test mode data includes a number of or location of failed memory locations, or both.
29. The memory controller of claim 23, wherein the memory controller is configured to provide control of the bus to the test mode engine responsive to an indication of test mode operation being desired.
30. The memory controller of claim 23, wherein the test mode commands are loaded from firmware of the memory controller.
31. A method for repairing memory, the method comprising:
loading at least one test mode command in a test mode engine of a memory controller;
providing a signal from the memory controller to memory, wherein the signals are configured to cause the memory to enter a test mode of operation;
providing the at least one test mode command to the memory over a bus;
receiving test mode data from the memory responsive to the at least one test mode command, wherein the test mode data comprises data generated by the memory during test mode; and
causing the memory to be repaired, using the test mode engine, in accordance with the test mode data.
32. The method of claim 31, wherein the test mode data includes a number of, or location of available redundant memory locations, or both.
33. The method of claim 31, wherein the test mode data includes a number of or location of failed memory locations, or both.
34. The method of claim 31, further comprising storing the test mode data in a location accessible to the test mode engine.
35. The method of claim 31, further comprising loading a plurality of fail locations and wherein said repairing comprises replacing the fail locations in accordance with the test mode data.
36. The method of claim 31, wherein the memory controller is configured to read data from and write data to the memory over the bus during normal operation of the memory.
37. A memory controller configured to read data from and write data to a memory over a bus in accordance with a clock signal during normal operation of the memory, wherein the memory controller comprises: a test mode engine configured to place the memory into a test mode of operation, receive test mode data from the memory over the bus during the test mode of operation, and cause the memory to be repaired over the bus during the test mode of operation, wherein the test mode engine is configured to adjust a frequency of the clock signal and provide at least one loaded test mode command to the memory during the test mode of operation.
38. The memory controller of claim 37, wherein the test mode engine being configured to adjust the frequency of the clock signal comprises the test mode engine being configured to stop the clock signal between test mode commands provided to the memory.
39. The memory controller of claim 38, wherein the test mode engine being configured to stop the clock signal comprises the test mode engine being configured to hold the clock signal at a low level between test mode commands provided to the memory.
40. The memory controller of claim 37, wherein the test mode engine being configured to adjust the frequency of the clock signal comprises the test mode engine being configured to reduce the frequency of the clock signal during the test mode of operation.
41. The memory controller of claim 37, wherein the test mode engine being configured to adjust the frequency of the clock signal comprises the test mode engine being configured to provide NOP commands to the memory at rising edges of the clock signal falling between test mode commands.
42. The memory controller of claim 37, wherein the test mode engine is further configured to restore the clock signal on exiting the test mode of operation.
43. A method for repairing memory, the method comprising:
placing a memory into a test mode of operation at least in part by providing a signal to the memory from a test mode engine of a memory controller over a bus used during normal operation of the memory;
providing a test mode command to the memory during the test mode of operation;
adjusting a frequency of a clock signal provided to the memory during the test mode of operation;
receiving test mode data from the memory; and
repairing the memory in accordance with the test mode data.
44. The method of claim 45, wherein said adjusting a frequency of a clock signal comprises stopping the clock signal between test mode commands.
45. The method of claim 44, wherein said stopping the clock signal comprises holding the clock signal at a low level between test mode commands.
46. The method of claim 43, further comprising restoring a frequency of the clock signal and returning the memory to the normal operation.
47. A memory controller configured to read data from and write data to a memory over a bus in accordance with a clock signal during normal operation of the memory, wherein the memory controller comprises:
a test mode engine configured to place the memory into a test mode of operation, receive test mode data from the memory over the bus during the test mode of operation, and cause the memory to be repaired over the bus during the test mode of operation, wherein the test mode engine is configured to provide at least one NOP command and at least one loaded test mode command to the memory during the test mode of operation.
48. The memory controller of claim 47, further comprising:
a plurality of registers, each of the plurality of registers corresponding to a device of the memory, respectively, and configured to store data during the test mode of operation.
49. The memory controller of claim 47, wherein the at least one NOP command is configured to not provided on the bus responsive, at least in part, to the NOP command.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A wire terminating tool for positioning and terminating a plurality of wires in a termination block, the wire terminating tool comprising:
a handle;
a positioning member operably coupled to the handle, wherein the positioning member comprises a plurality of notches;
a wire retention member retractably coupled to the handle and configured to slidingly translate with respect to the positioning member between a load position and an unload position, wherein the wire retention member comprises a plurality of wire engagement slots, and wherein in the load position, the wire retention member is configured to selectively secure each of the plurality of wires thereto in a respective one of the plurality of wire engagement slots, and wherein in the unload position, the wire retention member is retracted with respect to the positioning member, therein transferring the plurality of wires from the wire retention member to the plurality of notches in the positioning member, and wherein the positioning member is configured to position each of the plurality of wires in a respective terminal of the termination block; and
a seating apparatus configured to seat the plurality of wires in the plurality of terminals, respectively, therein providing a metal-to-metal contact between the respective plurality of wires and plurality of terminals.
2. The wire terminating tool of claim 1, wherein the seating apparatus comprises a seating member respectively associated with each of the plurality of notches, wherein each seating member is operably coupled to the positioning member and configured to seat a respective one of the plurality of wires in the respective terminal concurrent with the retraction of the wire retention member with respect to the positioning member.
3. The wire terminating tool of claim 2, wherein the handle comprises a first portion and a second portion, wherein the first portion and second portion generally retain the wire retention member in sliding engagement thereto, and wherein the seating apparatus is operably coupled to one or more of the first portion and second portion of the handle.
4. The wire terminating tool of claim 3, wherein each seating member comprises one or more of a pin, bar, plate, and extrusion fixedly coupled to one or more of the first portion and second portion of the handle.
5. The wire terminating tool of claim 2, wherein each seating member comprises one or more of a pin, bar and extrusion operably coupled to the positioning member and extending inwardly toward the wire retention member.
6. The wire terminating tool of claim 1, further comprising a cutting apparatus operably coupled to the handle and configured to cut the plurality wires at a predetermined position.
7. The wire terminating tool of claim 6, wherein the cutting apparatus comprises a cutter respectively associated with each of the plurality of notches, wherein each cutter is operably coupled to the positioning member and configured to cut a respective one of the plurality of wires subsequent to the retraction of the wire retention member with respect to the positioning member.
8. The wire terminating tool of claim 7, wherein the handle comprises a first portion and a second portion, wherein the first portion and second portion generally retain the wire retention member in sliding engagement thereto, and wherein the cutting apparatus is operably coupled to one of the first portion and second portion of the handle.
9. The wire terminating tool of claim 8, wherein each cutter comprises one or more of a roller cutter, diagonal cutter, blade, and shear operably coupled to the one of the first portion and second portion of the handle.
10. The wire terminating tool of claim 9, wherein the cutting apparatus comprises an activator operably coupled to each cutter, wherein the activator is configured to translate each cutter with respect to the positioning member, therein cutting each respective wire.
11. The wire terminating tool of claim 10, wherein the activator comprises one or more of a motor, gears, and linkages operably coupled to each cutter.
12. The wire terminating tool of claim 11, further comprising a power source operably coupled to the activator.
13. The wire terminating tool of claim 12, wherein the power source comprises a battery removably positioned within the handle.
14. The wire terminating tool of claim 10, wherein the activator comprises a lever operably coupled to the handle, wherein the lever is manually actuated by a user.
15. The wire terminating tool of claim 7, wherein each cutter comprises one or more shears, and wherein the cutting apparatus further comprises a trigger mechanism and a motor having a shaft operably coupled to each of the one or more shears via a plurality of gears and linkages, wherein the trigger mechanism selectively actuates the motor causing a rotation of the shaft, wherein the rotation of the shaft pivots each of the one or more shears about a respective axis, therein cutting each respective wire.
16. The wire terminating tool of claim 15, further comprising a battery operably coupled to the motor, wherein the battery is removably positioned within the handle.
17. The wire terminating tool of claim 1, further comprising a cutting apparatus configured to cut the plurality wires at a predetermined position, wherein the cutting apparatus comprises one or more of a roller cutter, diagonal cutter, blade, and shear operably coupled to the handle.
18. The wire terminating tool of claim 17, wherein the cutting apparatus comprises one or more cutters associated with each of the plurality of notches, wherein the one or more cutters are operably coupled to one or more levers and gears, and wherein the one or more levers and gears are operably coupled to one or more of a trigger mechanism and a motor, wherein the trigger mechanism andor motor are configured to actuate the one or more cutters, therein cutting the plurality of wires.
19. The wire terminating tool of claim 17, wherein one or more of the seating apparatus and cutting apparatus comprises one or more of a motor, lever, gear, battery, switch, spring, and trigger mechanism.
20. A wire terminating tool, comprising:
a generally hollow handle comprising a first portion and a second portion, wherein at least one of the first portion and second portion comprise one or more cable guidance members extending along a predetermined length of an outer portion of the respective first portion andor second portion, wherein the one or more cable guidance members are configured to engage a cable comprising a plurality of wires;
a positioning member fixedly coupled to the handle, wherein the positioning member comprises a plurality of notches associated with each of the first portion and second portion of the handle; and
a wire retention member retractably coupled to the handle between the first portion and second portion thereof, wherein the wire retention member is configured to slidingly translate with respect to the positioning member between a load position and an unload position, wherein the wire retention member comprises:
a plurality of wire engagement slots having a binding member respectively positioned within each of the wire engagement slots;
one or more location members positioned at one or more ends of the wire retention member, wherein the one or more location members are configured to mate with a location feature of a termination block, and wherein in the load position, the wire retention member is configured to selectively secure each of the plurality of wires thereto in a respective one of the plurality of wire engagement slots, and wherein in the unload position, the wire retention member is retracted with respect to the positioning member, therein transferring the plurality of wires from the wire retention member to the plurality of notches in the positioning member, and wherein the positioning member is configured to position each of the plurality of wires in a respective terminal of the termination block;
a seating apparatus configured to seat the plurality of wires in the plurality of terminals, respectively, therein providing a metal-to-metal contact between the respective plurality of wires and plurality of terminals; and
a cutting apparatus configured to cut the plurality wires at a predetermined position, wherein the cutting apparatus comprises one or more of a roller cutter, diagonal cutter, blade, and shear operably coupled to the handle.