Author: claimsbot

What is claimed is:

1. A friction stir welding method comprising the steps of:
detecting, using a sensor, the position of the tip of a friction stir welding tool mounted on a main shaft;
setting as a reference position the position obtained by adding or subtracting the length of a small-diameter portion of said tool to said detected position; and
performing friction stir welding by inserting said tool into said reference position in a work object.
2. A friction stir welding method comprising the steps of:
detecting the torque, current value of a rotation axis of a friction stir welding tool during a friction stir welding process; and
controlling the depth of insertion of said friction stir welding tool into a work object based on the detected value.
3. A friction stir welding method comprising the steps of:
detecting the torque current value of a rotation axis when inserting a friction stir welding tool into a work object;
correcting the coordinate value of said work object based on said detected torque current value; and
controlling the relative amount of movement of said friction stir welding tool relative to said work object based on the corrected value.
4. A friction stir welding method comprising the steps of:
while inserting a friction stir welding tool into a work object, detecting a current flowing in said tool being transmitted when said tool contacts said work object;
correcting the coordinate value of said work object based on said detected current; and
controlling the relative amount of movement of said friction stir welding tool relative to said work object based on the corrected coordinate value.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of controlling a data strobe clock buffer in a semiconductor memory apparatus, comprising:
enabling a buffer enable signal;
generating an internal strobe clock signal by buffering an external data strobe clock signal pair;
disabling the buffer enable signal by discriminating toggle timing of the internal data strobe clock signal according to a burst length of data input to the semiconductor memory apparatus; and
stopping the buffering operation for the external data strobe clock signal pair.
2. The method of claim 1, wherein the disabling the buffer enable signal comprises:
generating a timing discrimination signal by discriminating the toggle timing of the internal data strobe clock signal in response to a burst start signal and a burst length signal; and
disabling the buffer enable signal in response to the timing discrimination signal.
3. The method of claim 2, wherein the timing discrimination signal includes a first timing discrimination signal and a second timing discrimination signal.
4. The method of claim 3, wherein the generating of the timing discrimination signal discriminates how many times the internal data strobe clock signal is toggled according to whether the burst length signal is enabled to enable the first timing discrimination signal.
5. The method of claim 4, wherein the generating of the timing discrimination signal further comprises generating the second timing discrimination signal having the same period as the internal data strobe clock signal and a pulse width narrower than the internal data strobe clock signal.
6. The method of claim 4, wherein the disabling the buffer enable signal in response to the timing discrimination signal disables the buffer enable signal if the second timing discrimination signal is toggled in a state where the first timing discrimination signal is enabled.
7. A method of controlling a semiconductor memory apparatus, comprising:
controlling a data strobe clock buffer of the semiconductor memory apparatus by:
starting a buffering operation for an external data strobe clock signal pair and enabling a buffer enable signal;
generating an internal strobe clock signal by buffering the external data strobe clock signal pair;
disabling the buffer enable signal by discriminating toggle timing of the internal data strobe clock signal according to a burst length of data input to the semiconductor memory apparatus; and
stopping the buffering operation for the external data strobe clock signal pair.
8. The method of claim 7, wherein the disabling the buffer enable signal is controlled by a timing discrimination signal generated by discriminating the toggle timing of the internal data strobe clock signal in response to a burst start signal and a burst length signal of the input data.
9. The method of claim 8, further comprising generating a two-period time delay signal based upon a level change after two time periods of the internal data strobe clock signal when the burst start signal is enabled.
10. The method of claim 9, further comprising delaying the two-period time delay signal by two time periods of the internal data strobe clock signal to generate a four- period time delay signal.
11. The method of claim 10, further comprising combining the two-period time delay signal and the four-period time delay signal based upon the burst length signal to disable the buffer enable signal.

1. A node for use in a 3D graphics hardware accelerator implemented as a plurality of nodes connected to a ring, the node comprising:
a loop interface for receiving packets from a neighboring node on the ring and for transmitting packets to another neighboring node on the ring;
a memory port to a local memory sub-system;
a render stage coupled to the loop interface and to the memory port, the local memory sub-system storing a texture store dedicated to the render stage, the render stage for receiving graphics primitive loop packets via the loop interface, executing the graphics rendering specified in the graphics primitive loop packets including accessing via the memory port the texture store in the local memory sub-system as required by the graphics primitive loop packet, and generating corresponding draw pixel loop packets;
a sample fill stage coupled to the loop interface and to the memory port, the local memory sub-system storing an interleave of a super-sampled frame buffer dedicated to the sample fill stage, the sample fill stage for receiving draw pixel loop packets via the loop interface and, as specified by the draw pixel loop packets, performing via the memory port a conditional sample update function of samples andor pixels in the interleave of the super-sampled frame buffer stored in the local memory sub-system; and
a video output stage coupled to the loop interface and to the memory port, the interleave of the super-sampled frame buffer further dedicated to the video output stage, the video output stage for receiving video pixel loop packets via the loop interface and, as specified by the video pixel loop packets, retrieving via the memory port samples andor pixels in the interleave stored in the local memory sub-system to modify the video pixel loop packets, and transmitting the modified video pixel loop packets via the loop interface.
2. The node of claim 1, further comprising an interface unit, the interface unit including a host interface for connecting to a host computer, the interface unit receiving graphics driver commands from the host computer and converting the graphics driver commands to loop packets for transmission over the ring to other nodes.
3. The node of claim 2, wherein the interface unit converts the graphics driver commands to graphic commands, assigns the graphics commands to render stages and transmits the graphics commands to the assigned render stages via the loop interface.
4. The node of claim 3, wherein the interface unit that assigns the graphic commands uses a load balancing method.
5. The node of claim 2, wherein the interface unit further receives modified video pixel loop packets via the loop interface and transmits rendered images based thereon to the host computer.
6. The node of claim 2, wherein the interface unit further transmits rendered images to one or more physical images display devices not on the ring.
7. The node of claim 1, wherein the video output stage further performs convolution.
8. The node of claim 1, wherein the video output stage further performs anti-aliasing.
9. The node of claim 1, wherein the render stage includes a clip checking operation.
10. The node of claim 1, wherein the render stage includes a clipping operation if needed.
11. The node of claim 1, wherein the render stage includes vertex shading.
12. The node of claim 1, wherein the render stage includes scan converting.
13. The node of claim 1, wherein the render stage includes programmable shading on vertices.
14. The node of claim 1, wherein the render stage includes programmable shading on pixels.
15. The node of claim 1, wherein the render stage includes programmable shading on micropolygon vertices.
16. The node of claim 1, wherein the render stage includes computation processing including texture operations.
17. The node of claim 1, wherein the render stage includes displacement mapping.
18. The node of claim 1, wherein the render stage includes programmable shading.
19. The node of claim 1, wherein the render stage includes multicasting \u201cprojected to screen space boundaries\u201d of the results of tessellating and shading graphics primitives to targeted ones of the interconnected nodes, along with the plane equation of Z.
20. The node of claim 1, wherein the texture store contains a rendered image.
21. The node of claim 1, wherein the render stage applies a texture filtering technique to a texture map stored in the local memory sub-system.
22. The node of claim 21, wherein said texture filtering technique includes one or more of direct access, nearest neighbor access, bi-linear filtering, tri-linear filtering, bi-linear MIP mapping, tri-linear MIP mapping, anisotropic filtering, summed area filtering, procedural textures, bump mapping, displacement mapping, percentage closer shadow filtering, and deep shadow map filtering.
23. The node of claim 1, wherein the render stage includes surface tessellation.
24. The node of claim 23, wherein the surface tessellation includes the tessellation of surface primitives.
25. The node of claim 24, wherein the surface primitives include one or more of polygons, higher order surface primitives, and implicit surfaces.
26. The node of claim 25, wherein the higher order surface primitives includes one or more of conic surfaces, ruled surfaces, surfaces of revolution, B\xe9zier patches, B-Spline patches, NURBS patches, sub-division surfaces, and sub-division surfaces with edge and vertex sharpness control.
27. The node of claim 23, wherein the tessellation includes the application of displacement maps.
28. The node of claim 1, wherein the node uses a single physical connection for all information transfer on the ring.
29. The node of claim 1, wherein the node uses point to point, unidirectional links for all information transfer on the ring.
30. The node of claim 1, wherein the loop interface, render stage, sample fill stage, video output stage, memory port and local memory sub-system are formed of a single processing chip.
31. The node of claim 1, wherein the loop interface, render stage, sample fill stage, video output stage and memory port are formed of a single processing chip and the local memory sub-system is formed of at least one memory chip.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A molded synthetic shingle having:
(a) a tab portion adapted to be weather-exposed in the installed condition on a roof;
(b) a headlap portion adapted to be weather-unexposed in the installed condition on a roof;
(c) the shingle having a top side and a bottom side; with the bottom side being adapted to be applied toward a roof in the installed condition on a roof;
(d) with the headlap portion including a top surface on the top side of the shingle;
(e) at least one fastener location on the top surface of the headlap portion of the shingle; and
(f) a molded moisture guard protruding upwardly from the top surface of the headlap portion of the shingle, at least partially surrounding the at least one fastener location, for deflecting moisture from the at least one fastener location.
2. The shingle of claim 1, wherein there are at least two fastener locations on the top surface of the headlap portion of the shingle, with each said fastener location having a said moisture guard of clause (f) associated therewith.
3. The shingle of claim 2, wherein each said moisture guard completely surrounds its associated fastener location.
4. The shingle of claim 2, wherein each moisture guard has an upwardly opening recess therein for receiving the head of a fastener in the recess, and wherein there is a penetrable or at least partially open bottom in the recess through which a fastener may pass, with the penetrable or at least partially open bottom comprising a said fastener location.
5. The shingle of claim 2, wherein each moisture guard has an upwardly opening recess at least partially surrounded by an upwardly protruding portion of the guard, and the guard being adapted to receive a head of a fastener thereagainst, and with a penetrable or at least partially open bottom in the recess through which a fastener may pass, with the penetrable or at least partially open bottom comprising a fastener location.
6. The shingle of claim 4, wherein the bottom side of the headlap portion of the shingle is provided with bottom recesses located beneath the upwardly opening recesses of the moisture guards.
7. The shingle of claim 2, wherein each said moisture guard has a through-hole therein for receiving a portion of a fastener therethrough.
8. The shingle of claim 2, wherein the bottom side of the tab portion of the shingle is provided with downwardly protruding projections carried thereby, with each downwardly protruding projection having a downwardly opening recess therein comprising means for cooperative engagement with an upwardly protruding moisture guard on the top surface of the headlap portion of an associated other shingle.
9. The shingle of claim 8, wherein said cooperative engagement is in the form of at least partial reception of moisture guards of associated other shingles in the recesses of said downwardly protruding projections.
10. The shingle of claim 8, wherein each downwardly protruding projection and its associated moisture guard comprise means facilitating proper alignment of shingles in next-overlying courses with shingles in next-underlying courses when shingles are installed in courses on a roof.
11. The shingle of claim 2, wherein the bottom side of the tab portion of the shingle is provided with a downwardly protruding projection comprising means for cooperative engagement with an upwardly protruding moisture guard on the top surface of the headlap portion of an associated other shingle.
12. The shingle of claim 2, wherein the bottom side of the tab portion of the shingle is provided with downwardly protruding projections carried thereby, with each such projection being adapted to be received within, in cooperative engagement, a protruding moisture guard on the top surface of the headlap portion of an associated other shingle.
13. The shingle of claim 2, wherein the shingle moisture guards comprise shapes that are any one of:
(a) circular configurations;
(b) oval configurations;
(c) rectangular configurations;
(d) triangular configurations;
(e) hexagonal configurations;
(f) trapezoidal configurations;
(g) semi-circular configurations;
(h) crescent-shaped configurations; and
(i) arcuate configurations.
14. A roof comprising a plurality of shingles according to claim 1, laid up in a plurality of courses, with a plurality of shingles in each course, with shingles in next-overlying courses covering headlap portions of shingles in next-underlying courses and with the tab portions of the shingles being weather-exposed in the installed condition on a roof.
15. A roof comprising a plurality of shingles according to claim 2, laid up in a plurality of courses, with a plurality of shingles in each course, with shingles in next-overlying courses covering headlap portions of shingles in next-underlying courses and with the tab portions of the shingles being weather-exposed in the installed condition on a roof.
16. A roof according to claim 15, wherein each said moisture guard completely surrounds its associated fastener location.
17. A roof according to claim 15, wherein each moisture guard has an upwardly opening recess therein for receiving the head of a fastener in the recess, and wherein there is a penetrable bottom in the recess through which a fastener may pass, with the penetrable bottom comprising a said fastener location.
18. A roof according to claim 17, wherein the bottom side of the headlap portion of the shingle is provided with bottom recesses located beneath the upwardly opening recesses of the moisture guards.
19. A roof according to claim 15, wherein each said moisture guard has a through-hole therein for receiving a portion of a fastener therethrough.
20. A roof according to claim 15, wherein the bottom side of the tab portion of the shingle is provided with downwardly protruding shields carried thereby, with each shield having a downwardly opening recess therein for cooperative engagement with an upwardly protruding moisture guard on the top surface of the headlap portion of a shingle in a next-underlying course of shingles.
21. A roof according to claim 15, wherein the bottom side of the tab portion of the shingle is provided with a downwardly protruding projection comprising means for cooperative engagement with an upwardly protruding moisture guard on the top surface of the headlap portion of an associated other shingle.
22. A method of providing a molded synthetic shingle having a moisture guard, the method comprising the steps of:
(a) providing a tab portion for the shingle, that is adapted to be weather-exposed in the installed condition on a roof;
(b) providing a headlap portion for the shingle, adapted to be weather-unexposed in the installed condition on a roof;
(c) wherein the shingle has a top side and a bottom side; with the bottom side being adapted to be applied toward a roof in the installed condition on a roof;
(d) with the headlap portion including a top surface on the top side of the shingle;
(e) providing at least one fastener location on the top surface of the headlap portion of the shingle; and
(f) providing a molded moisture guard protruding upwardly from the top surface of the headlap portion of the shingle, at least partially surrounding the at least one fastener location, for deflecting moisture from the at least one fastener location.
23. A method of providing a roof covering, the method comprising;
(a) providing a plurality of shingles according to claim 11;
(b) attaching a first course of the shingles to a root and
(c) attaching an overlying second course of shingles with moisture guards of the first course of shingles in alignment with the downwardly protruding projections of shingles of the second course.