Author: claimsbot

1. A riser reactor comprising:
a vertical riser having a hydrocarbon feed inlet; and
a row of baffles located more than about 6 m above the hydrocarbon feed inlet, a front face of the baffle having a ceramic liner facing the center of the riser, a lower end of the baffle attached to a wall of the riser, and the baffle inclined inward from the wall at an angle of about 90\xb0 or less.
2. The riser reactor of claim 1 wherein the baffle is inclined inward at the angle of about 90\xb0.
3. The riser reactor of claim 1 wherein the baffle is inclined inward at the angle of about 10\xb0 to about 45\xb0.
4. The riser reactor of claim 1 wherein the baffle comprises a support plate with the ceramic liner.
5. The riser reactor of claim 1 wherein the baffle comprises a support plate with a ceramic sleeve covering the front and back faces.
6. The riser reactor of claim 1 wherein there are at least two rows of baffles.
7. The riser reactor of claim 1 wherein the row of baffles comprises at least two subsets of baffles, the first subset at a first position, and the second subset at a second position above the first position.
8. The riser reactor of claim 7 wherein the baffles of the first subset are angularly offset from the baffles of the second subset.
9. The riser reactor of claim 1 wherein the baffles are arranged symmetrically around the wall of the riser.
10. The riser reactor of claim 1 wherein baffles cover substantially the entire circumference of the riser.
11. The riser reactor of claim 1 wherein the baffle extends inward from the wall a distance up to about 25% of a radius of the riser.
12. The riser reactor of claim 1 wherein the baffles are in a range of about 0.15 to about 0.30 m long.
13. The riser reactor of claim 1 further comprising a support attached to the back face of the baffle and to the wall.
14. The riser reactor of claim 1 wherein the baffle comprises a fusion-cast ceramic tile with embedded metal.
15. The riser reactor of claim 1 wherein the back face of the baffle is coated with refractory.
16. A riser reactor comprising:
a vertical riser having a hydrocarbon feed inlet; and
a row of baffles located more than about 6 m above the hydrocarbon feed inlet, a front face of the baffle facing the center of the riser, a lower end of the baffle attached to a wall of the riser, and the baffle inclined inward from the wall at an angle of about 90\xb0 or less.
17. The riser reactor of claim 16 wherein the baffle is inclined inward at the angle of about 10\xb0 to about 45\xb0.
18. The riser reactor of claim 16 wherein the baffle comprises a support plate having a ceramic liner on a front face.
19. The riser reactor of claim 16 wherein the baffle comprises a support plate having a ceramic sleeve covering the front and back faces.
20. The riser reactor of claim 16 wherein the row of baffles comprises at least two subsets of baffles, the first subset at a first position, and the second subset at a second position above the first position.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An integrated circuit for processing data, said integrated circuit comprising:
a functional circuit configured to perform data processing operations:
a diagnostic circuit configured to perform diagnostic operations upon said functional circuit, and
an interface circuit configured to use a bi-directional serial link to provide communications between said diagnostic circuit and an external diagnostic device,
wherein said interface circuit and said external diagnostic device are configured when changing communication direction such that a sequence is followed comprising:
(i) driving a signal carried on said bi-directional serial link to a park state having a predetermined signal value for a park state period with whichever one of said interface circuit and said external diagnostic device was serving as a data sender;
(ii) providing for said signal carried on said bi-directional serial link to be substantially undriven and float at substantially said predetermined signal value for an undriven state period;
(iii) driving said signal carried on said bi-directional serial link to a resume state having signal value opposite to said predetermined signal value for a resume state period with whichever one of said interface circuit and said external diagnostic device is to now serve as said data sender.
2. An integrated circuit as claimed in claim 1, wherein transition of said signal carried on said bi-directional serial link from substantially said predetermined signal value during said undriven state period to said signal value opposite to said predetermined signal value during said resume state period is used as a timing reference for subsequent sampling of said signal carried on said bi-directional serial link by whichever one of said interface circuit and said external diagnostic device is to now serve as a data receiver.
3. An integrated circuit as claimed in claim 1 wherein, if said signal carried on said hi-directional serial link is not driven to said resume state by whichever one of said interface circuit and said external diagnostic device is to now serve as said data sender, then this is detectable as a communication error by whichever one of said interface circuit and said external diagnostic device was serving as said data sender.
4. An integrated circuit as claimed in claim 3, wherein following said communication error, changing communication direction is retried for a predetermined number times and, if said communication error remains, then communication between said interface circuit and said external diagnostic device is reset.
5. An integrated circuit as claimed in claim 1, wherein, if said interface circuit has partly received a current frame of data and cannot continue to correctly receive data being sent via said signal carried on said bi-directional serial link, then said interface circuit is configured to assert a wait signal and ignore subsequently received bi-directional serial signals in said current frame of data.
6. An integrated circuit as claimed in claim 5, wherein said interface circuit is configured to ignore subsequently received bi-directional serial signals until said wait signal is cleared by said external diagnostic device.
7. An integrated circuit as claimed in claim 1, wherein, if said interface circuit has partly received a current frame of data and detects a fault, then said interface circuit is configured to assert a fault signal and ignore subsequently received bi-directional serial signals in said current frame of data.
8. An integrated circuit as claimed in claim 7, wherein said interface circuit is configured to ignore subsequently received signals on said bi-directional serial link until said fault signal is cleared by said external diagnostic device.
9. An integrated circuit as claimed in claim 1, wherein, if said interface circuit does not detect a valid message when receiving said signals carried on said bi-directional serial link, then said interface circuit is configured to ignore said signals carried on said bi-directional serial link until a valid message is received.
10. An integrated circuit for processing data, said integrated circuit comprising:
a functional circuit configured to perform data processing operations:
a diagnostic circuit configured to perform diagnostic operations upon said functional circuit, and
an interface circuit configured to use a bi-directional serial link to provide communications between said diagnostic circuit and an external diagnostic device,
wherein, a signal carried on said bi-directional serial link has a default signal value when not being driven by either said interface circuit or said external diagnostic device and, during initialization of communication via said signal carried on said bi-directional serial link, said interface circuit is configured to drive said signal carried on said bi-directional serial link to a signal value opposite to said default signal value for a training period corresponding to a predetermined number of clock periods of an interface circuit clock signal initially to be used by said interface circuit, said external diagnostic device being configured to detect said training period and to adjust to use an external diagnostic device clock signal compatible with said interface signal clock.
11. An integrated circuit as claimed in claim 10, wherein following initialization of communication via said signal carried on said bi-directional serial link, said interface circuit and said external diagnostic device are configured to communicate to establish if a higher signal clock speed is mutually supported to allow faster communication.
12. An integrated circuit as claimed in claim 10, wherein said interface circuit is configured to be triggered to commence initialization of communication by said external diagnostic device driving said signal carried on said bi-directional serial link to said signal value opposite to said default signal value for a reset period corresponding to greater than a predetermined number of clock periods as measured by said interface circuit.
13. An integrated circuit as claimed in claim 10, wherein, if said interface circuit has partly received a current frame of data and cannot continue to correctly receive data being sent via said signal carried on said bi-directional serial link, then said interface circuit is configured to assert a wait signal and ignore subsequently received bi-directional serial signals in said current frame of data.
14. An integrated circuit as claimed in claim 13, wherein said interface circuit continues to ignore subsequently received bi-directional serial signals until said wait signal is cleared by said external diagnostic device.
15. A method of communicating with a diagnostic circuit configured to perform diagnostic operations upon a functional circuit within an integrated circuit, said method comprising the steps of:
communicating with a bi-directional serial link via an interface circuit,
wherein said interface circuit and said external diagnostic device are configured, when changing communication direction, such that a sequence is followed comprising:
(i) driving a signal carried on said bi-directional serial link to a park state having a predetermined signal value for a park state period with whichever one of said interface circuit and said external diagnostic device was serving as a data sender;
(ii) providing for said signal carried on said bi-directional serial link to be substantially undriven and float at substantially said predetermined signal value for an undriven state period;
(iii) driving said signal carried on said bi-directional serial link to a resume state having signal value opposite to said predetermined signal value for a resume state period with whichever one of said interface circuit and said external diagnostic device is to now serve as said data sender.
16. A method as claimed in claim 15, wherein transition of said signal carried on said bi-directional serial link from substantially said predetermined signal value during said undriven state period to said signal value opposite to said predetermined signal value during said resume state period is used as a timing reference for subsequent sampling of said signal carried on said bi-directional serial link by whichever one of said interface circuit and said external diagnostic device is to now serve as a data receiver.
17. A method as claimed in claim 15, wherein, if said signal carried on said bi-directional serial link is not driven to said resume state by whichever one of said interface circuit and said external diagnostic device is to now serve as said data sender, then this is detected as a communication error by whichever one of said interface circuit and said external diagnostic device was serving as said data sender.
18. A method as claimed in claim 17, wherein following said communication error, changing communication direction is retried for a predetermined number times and, if said communication error remains, then communication between said interface circuit and said external diagnostic device is reset.
19. A method as claimed in claim 15, wherein, if said interface circuit has partly received a current frame of data and cannot continue to correctly receive data being sent via said signal carried on said bi-directional serial link, then said interface circuit asserts a wait signal and ignores subsequently received bi-directional serial signals in said current frame of data.
20. A method as claimed in claim 19, wherein said interface circuit continues to ignore subsequently received signals on said bi-directional serial link until said wait signal is cleared by said external diagnostic device.
21. A method as claimed in claim 15, wherein, if said interface circuit has partly received a current frame of data and detects a fault, then said interface circuit asserts a fault signal and ignores subsequently received signals on said bi-directional serial link in said current frame of data.
22. A method as claimed in claim 21, wherein said interface circuit continues to ignore subsequently received signals on said bi-directional serial link until said fault signal is cleared by said external diagnostic device.
23. A method as claimed in claim 15, wherein, if said interface circuit does not detect a valid message when receiving said signal carried on said bi-directional serial link, then said interface circuit ignores signals carried on said bi-directional serial link until a valid message is received.
24. A method of communicating with a diagnostic circuit configured to perform diagnostic operations upon a functional circuit within an integrated circuit, said method comprising the steps of:
communicating with a bi-directional serial link via an interface circuit,
wherein, a signal carried on said bi-directional serial link has a default signal value when not being dnven by either said interface circuit or said external diagnostic device and, during initialization of communication via said signal carried on said bi-directional serial link, said interface circuit drives said signal carried on said bi-directional serial link to a signal value opposite to said default signal value for a training period corresponding to a predetermined number of clock periods of an interface circuit clock signal initially to be used by said interface circuit, said external diagnostic device being configured to detect said training period and to adjust to use an external diagnostic device clock signal compatible with said interface signal clock.
25. A method as claimed in claim 24, wherein following initialization of communication via said signal carried on said bi-directional serial link, said interface circuit and said external diagnostic device communicate to establish if a higher signal clock speed is mutually supported to allow faster communication.
26. A method as claimed in claim 24, wherein said interface circuit is triggered to commence initialization of communication by said external diagnostic device driving said signal carried on said bi-directional serial link to said signal value opposite to said default signal value for a reset period corresponding to greater than a predetermined number of clock periods as measured by said interface circuit.
27. A method as claimed in claim 24, wherein, if said interface circuit has partly received a current frame of data and cannot continue to correctly receive data being sent via said signal carried on said bi-directional serial link, then said interface circuit asserts a wait signal and ignores subsequently received bi-directional serial signals in said current frame of data.
28. A method as claimed in claim 27, wherein said interface circuit continues to ignore subsequently received bi-directional serial signals until said wait signal is cleared by said external diagnostic device.
29. A diagnostic device for performing diagnostic operations upon an integrated circuit, said diagnostic device comprising:
an interface circuit configured to provide communication between said diagnostic device and a diagnostic circuit within said integrated circuit; wherein
said interface circuit configured to use a bi-directional serial link to provide communications between said diagnostic circuit and said diagnostic device,
wherein said interface circuit and said diagnostic device are configured when changing communication direction such that a sequence is followed comprising:
(i) driving a signal carried on said bi-directional serial link to a park state having a predetermined signal value for a park state period with whichever one of said interface circuit and said diagnostic device was serving as a data sender;
(ii) providing for said signal carried on said bi-directional serial link to be substantially undriven and float at substantially said predetermined signal value for an undriven state period;
(iii) driving said signal carried on said bi-directional serial link to a resume state having signal value opposite to said predetermined signal value for a resume state period with whichever one of said interface circuit and said diagnostic device is to now serve as said data sender.
30. A diagnostic device as claimed in claim 29, wherein transition of said signal carried on said bi-directional serial link from substantially said predetermined signal value during said undriven state period to said signal value opposite to said predetermined signal value during said resume state period is used as a timing reference for subsequent sampling of said signal carried on said bi-directional serial link by whichever one of said interface circuit and said diagnostic device is to now serve as a data receiver.
31. A diagnostic device as claimed in claim 29, wherein, if said bi-directional signal is not driven to said resume state by whichever one of said interface circuit and said diagnostic device is to now serve as said data sender, then this is detectable as a communication error by whichever one of said interface circuit and said diagnostic device was serving as said data sender.
32. A diagnostic device as claimed in claim 31, wherein following said communication error, changing communication direction is retried for a predetermined number times and, if said communication error remains, then communication between said interface circuit and said diagnostic device is reset.
33. A diagnostic device as claimed in claim 29, wherein, if said interface circuit has partly received a current frame of data and cannot continue to correctly receive data being sent via said signal carried on said bi-directional serial link, then said interface circuit asserts a wait signal and ignores subsequently received bi-directional serial signals in said current frame of data.
34. A diagnostic device as claimed in claim 33, wherein said interface circuit is configured to ignore subsequently received signals carried over said bi-directional serial link until said wait signal is cleared by said external diagnostic device.
35. A diagnostic device as claimed in claim 29, wherein, if said interface circuit has partly received a current frame of data and detects a fault, then said interface circuit is configured to assert a fault signal and ignore subsequently received signals carried over said bi-directional serial link in said current frame of data.
36. A diagnostic device as claimed in claim 35, wherein said interface circuit is configured to ignore subsequently received bi-directional serial signals until said fault signal is cleared by said external diagnostic device.
37. A diagnostic device as claimed in claim 29, wherein, if said interface circuit does not detect a valid message when receiving said signal carried on said bi-directional serial link, then said interface circuit configured to ignore said signal carried on said bi-directional serial links until a valid message is received.
38. A diagnostic device for performing diagnostic operations upon an integrated circuit, said diagnostic device comprising:
an interface circuit configured to provide communication between said diagnostic device and a diagnostic circuit within said integrated circuit; wherein
said interface circuit is configured to use a bi-directional serial link to provide communications between said diagnostic circuit and said diagnostic device,
wherein, a signal carried on said bi-directional serial link has a default signal value when not being driven by either said interface circuit or said diagnostic device and, during initialization of communication via said signal carried on said bi-directional serial link, said interface circuit is configured to drive said signal carried on said bi-directional serial link to a signal value opposite to said default signal value for a training period corresponding to a predetermined number of clock periods of an interface circuit clock signal initially to be used by said interface circuit, said diagnostic device being configured to detect said training period and to adjust to use an diagnostic device clock signal compatible with said interface signal clock.
39. A diagnostic device as claimed in claim 38, wherein following initialization of communication via said signal carried on said bi-directional serial link, said interface circuit and said external diagnostic device communicate to establish if a higher signal clock speed is mutually supported to allow faster communication.
40. A diagnostic device as claimed in claim 39, wherein said interface circuit is configured to be triggered to commence initialization of communication by said diagnostic device driving said signal carried on said bi-directional serial link to said signal value opposite to said default signal value for a reset period corresponding to greater than a predetermined number of clock periods as measured by said interface circuit.
41. A diagnostic device as claimed in claim 38, wherein, if said interface circuit has partly received a current frame of data and cannot continue to correctly receive data being sent via said signal carried on said bi-directional serial link, then said interface circuit is configured to assert a wait signal and ignore subsequently received bi-directional serial signals in said current frame of data.
42. A diagnostic device as claimed in claim 41, wherein said interface circuit is configured to ignore subsequently received bi-directional serial signals until said wait signal is cleared by said external diagnostic device.

1. A method of forming a thin film transistor (TFT), comprising:
providing a substrate;
forming a gate and a non-transparent structure on said substrate;
forming a dielectric layer which covers said gate on said substrate;
forming a first semi-conductive layer on said dielectric layer;
forming a second semi-conductive layer on said first semi-conductive layer;
forming a photoresist layer on said second semi-conductive layer;
placing a mask on said photoresist layer, wherein said mask has a slit pattern aimed at said gate;
patterning said photoresist layer to form a photoresist pattern over said gate and still over said substrate around said gate, wherein said photoresist pattern further comprises a thin photoresist pattern formed under said slit pattern and a thick photoresist pattern;
removing the portions of said second semi-conductive layer and said first semi-conductive layer without said photoresist pattern covering;
removing said thin photoresist pattern; and
removing the portion of said second semi-conductive layer without the portion of the photoresist pattern covering.
2. The method according to claim 1, wherein the center of said slit pattern is above the center of said gate.
3. The method according to claim 1, wherein said non-transparent structure electrically insulated from said gate, and said non-transparent structure and said gate are formed at the same time, and said non-transparent structure is at least under the portion of said first semi-conductive layer.
4. The method according to claim 1, wherein said photoresist pattern is removed after the portion of said second semi-conductive layer is removed, and then an extra dielectric layer is formed on the substrate to cover said first semi-conductive layer and said second semi-conductive layer.
5. The method according to claim 4, wherein said extra dielectric layer is patterned to form an open region to expose the portion of said second semi-conductive layer.
6. The method according to claim 5, comprising a patterned conductive structure formed on said extra dielectric layer and be filled in said open region.
7. The method according to claim 6, wherein said non-transparent structure electrically insulated from said gate is formed at the same time as said gate formed, said non-transparent structure is at least located under the portion of said patterned conductive structure.
8. The method according to claim 1, wherein the portion of said first semi-conductive layer without covering by the remained portion of said photoresist pattern is removed after removing the portion of said second semi-conductive layer.
9. The method according to claim 8, comprising an extra dielectric layer formed on said substrate to cover said first semi-conductive layer and second semi-conductive layer after removing said photoresist pattern.
10. The method according to claim 9, wherein said extra dielectric layer is patterned to form an open region to expose the portion of said second semi-conductive layer.
11. The method according to claim 10, wherein a patterned conductive structure is formed on said extra dielectric layer and filled in said open region.
12. The method according to claim 11, wherein said non-transparent structure electrically insulated from said gate is formed at the same time as said gate formed, said non-transparent structure is at least under the portion of said patterned conductive structure.
13. A method of forming a thin film transistor (TFT), comprising:
providing a substrate;
forming a conductive structure and a non-transparent structure on said substrate, wherein said conductive structure and said non-transparent structure are electrically insulated each other;
forming a first dielectric layer on said substrate, wherein said first dielectric layer covers said conductive structure and said non-transparent structure;
forming a first semi-conductive layer on said first dielectric layer;
forming a second semi-conductive layer on said first semi-conductive layer;
performing a pattern process to removing the portions of said second semi-conductive layer and said first semi-conductive layer, wherein the remained portions of said second semi-conductive layer and said first semi-conductive layer are at least over said conductive structure;
forming a second dielectric layer on said substrate, wherein said second dielectric layer also covers both remained portions of said second and said first semi-conductive layers;
forming an open region on said second dielectric layer to expose the portion of said second semi-conductive layer; and
forming a patterned semi-conductive layer on said second dielectric and filling said open region.
14. The method according to claim 13, wherein the remained portion of said first semi-conductive layer at least covers the portion of said non-transparent structure.
15. The method according to claim 13, wherein the remained portions of said semi-conductive layers are adjusted along the edges of said conductive structure, and the remained portions of said semi-conductive layers over the conductive structure are wider than other portions.
16. The method according to claim 13, wherein the remained portions of said semi-conductive layers are adjusted along the edges of said non-transparent structure, and the remained portions of said semi-conductive layers over the non-transparent structure are wider than other portions.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for generating a model for simulating systems of reacting species comprising:
receiving a plurality of reaction formulas;
determining a reaction rate expression for each of the received reaction formulas; and
generating a model for simulating systems of reacting species using the received reaction formulas and the determined reaction rate expressions.
2. The method of claim 1, wherein at least one of the reaction formulas is received via a graphical user interface.
3. The method of claim 1, wherein the generated model is displayed on a graphical user interface.
4. The method of claim 1, wherein the determined reaction rate expression is modified via a graphical user interface.
5. The method of claim 1, further comprising generating a reaction list of at least one reaction for at least one of the received reaction formulas.
6. The method of claim 5, further comprising displaying the generated reaction list in a graphical user interface.
7. The method of claim 5, further comprising eliminating at least one reaction rate expression associated with one or more reactions in the reaction list at equilibrium.
8. The method of claim 7, wherein the elimination is based on one or more threshold criteria.
9. The method of claim 5, further comprising determining at least one thermodynamic property of each reaction in the reaction list.
10. The method of claim 5, further comprising determining at least one kinetic property of each reaction in the reaction list.
11. The method of claim 1, further comprising pruning the reaction list to deactivate one or more reactions in the reaction list based on one or more criteria.
12. The method of claim 11, wherein a user modifies the one or more criteria via a graphical user interface.
13. The method of claim 1, further comprising generating a species list based on the received reaction formulas.
14. The method of claim 13, further comprising displaying the species list in a graphical user interface.
15. The method of claim 13, further comprising determining at least one thermodynamic property for each species in the species list.
16. The method of claim 13, further comprising determining at least one transport property for each species in the species list.
17. The method of claim 14, further comprising eliminating at least one time dependent term for at least one species at steady-state.
18. The method of claim 14, further comprising eliminating at least one concentration for at least one species at constant concentration.
19. The method of claim 1, further comprising displaying an output based on the generated model, wherein the output displays the composition and temperature dependence of the system of reacting species.
20. The method of claim 1, further comprising generating material and energy balances for the reacting species as input to a solver of partial differential equations.
21. A system for generating a model for simulating systems of reacting species comprising:
a receiving system that receives a plurality of reaction formulas;
a reaction rate determination system that determines a reaction rate expression for each of the received reaction formulas; and
a model generating system that generates a model for simulating systems of reacting species using the received reaction formulas and the determined reaction rate expressions.
22. The system of claim 21, wherein at least one of the reaction formulas is received via a graphical user interface.
23. The system of claim 21, further comprising a display system that displays the generated model on a graphical user interface.
24. The system of claim 21, wherein the determined reaction rate expression is modified via a graphical user interface.
25. The system of claim 21, further comprising a reaction list generating system that generates a reaction list of at least one reaction for at least one of the received reaction formulas.
26. The system of claim 25, further comprising a display system that displays the generated reaction list in a graphical user interface.
27. The system of claim 25, further comprising an elimination system that eliminates at least one reaction rate expression associated with one or more reactions in the reaction list at equilibrium.
28. The system of claim 27, wherein the elimination is based on one or more threshold criteria.
29. The system of claim 25, further comprising a reaction property determination system that determines at least one thermodynamic property of each reaction in the reaction list.
30. The system of claim 25, further comprising a reaction property determination system that determines at least one kinetic property of each reaction in the reaction list.
31. The system of claim 21, further comprising a pruning system that prunes the reaction list to deactivate one or more reactions in the reaction list based on one or more criteria.
32. The system of claim 31, wherein a user modifies the one or more criteria via a graphical user interface.
33. The system of claim 21, further comprising a species list generating system that generates a species list based on the received reaction formulas.
34. The system of claim 33, further comprising a display system that displays the species list in a graphical user interface.
35. The system of claim 33, further comprising a species property determination system that determines at least one thermodynamic property for each species in the species list.
36. The system of claim 33, further comprising a species property determination system that determines at least one transport property for each species in the species list.
37. The system of claim 34, further comprising an elimination system that eliminates at least one time dependent term for at least one species at steady-state.
38. The system of claim 34, further comprising an elimination system that eliminates at least one concentration for at least one species at constant concentration.
39. The system of claim 21, further comprising a display system that displays an output based on the generated model, wherein the output displays the composition and temperature dependence of the system of reacting species.
40. The system of claim 21, further comprising a material and energy balances generating system that generates material and energy balances for the reacting species as input to a solver of partial differential equations.
41. A computer readable medium having instructions stored thereon for generating a model for simulating systems of reacting species, which when executed by a processor, cause the processor to carry out:
receiving a plurality of reaction formulas;
determining a reaction rate expression for each of the received reaction formulas; and
generating a model for simulating systems of reacting species using the received reaction formulas and the determined reaction rate expressions.
42. The computer readable medium of claim 41, further comprising instructions for receiving at least one of the reaction formulas via a graphical user interface.
43. The computer readable medium of claim 41, further comprising displaying the generated model on a graphical user interface.
44. The computer readable medium of claim 41, further comprising instructions for enabling the determined reaction rate expression to be modified via a graphical user interface.
45. The computer readable medium of claim 41, further comprising instructions for generating a reaction list of at least one reaction for at least one of the received reaction formulas.
46. The computer readable medium of claim 45, further comprising instructions for displaying the generated reaction list in a graphical user interface.
47. The computer readable medium of claim 45, further comprising instructions for eliminating at least one reaction rate expression associated with one or more reactions in the reaction list at equilibrium.
48. The computer readable medium of claim 47, wherein the elimination is based on one or more threshold criteria.
49. The computer readable medium of claim 45, further comprising instructions for determining at least one thermodynamic property of each reaction in the reaction list.
50. The computer readable medium of claim 45, further comprising instructions for determining at least one kinetic property of each reaction in the reaction list.
51. The computer readable medium of claim 41, further comprising instructions for pruning the reaction list to deactivate one or more reactions in the reaction list based on one or more criteria.
52. The computer readable medium of claim 51, further comprising instructions for allowing a user to modify the one or more criteria via a graphical user interface.
53. The computer readable medium of claim 41, further comprising instructions for generating a species list based on the received reaction formulas.
54. The computer readable medium of claim 53, further comprising instructions for displaying the species list in a graphical user interface.
55. The computer readable medium of claim 53, further comprising instructions for determining at least one thermodynamic property for each species in the species list.
56. The computer readable medium of claim 53, further comprising determining at least one transport property for each species in the species list.
57. The computer readable medium of claim 54, further comprising instructions for eliminating at least one time dependent term for at least one species at steady-state.
58. The computer readable medium of claim 54, further comprising instructions for eliminating at least one concentration for at least one species at constant concentration.
59. The computer readable medium of claim 41, further comprising instructions for displaying an output based on the generated model, wherein the output displays the composition and temperature dependence of the system of reacting species.
60. The computer readable medium of claim 41, further comprising instructions for generating material and energy balances for the reacting species as input to a solver of partial differential equations.