Author: claimsbot

1. A method for providing security in an IC having protected functional circuitry, said method comprising:
providing, from the IC, an IC identifier;
in response to providing said IC identifier, receiving at the IC an input IC security key, wherein the input IC security key is provided by a debug device external to the IC, and wherein the debug device prior to providing the input IC security key evaluates a set of IC identifiers and corresponding IC security key values to determine the input IC security key;
comparing, in the IC, the input IC security key to a stored IC security key; and
selectively enabling access to the protected functional circuitry in the IC in response to said step of comparing.
2. The method of claim 1, wherein selectively enabling comprises:
if the input IC security key and stored IC security key match, enabling access to the protected functional circuitry; and
if the input IC security key and stored IC security key do not match, denying access to the protected functional circuitry.
3. The method of claim 2, further comprising:
if the input IC security key and stored IC security key do not match, waiting a predetermined amount of time prior to comparing a second input IC security key received via at least one IC terminal to the stored IC security key.
4. The method of claim 2, further comprising:
if the input IC security key and stored IC security key do not match, receiving a second input IC security key via at least one IC terminal in response to a reset signal.
5. The method of claim 1, wherein if the step of comparing does not result in a match of the input IC security key and stored IC security key within a predetermined window of time, access to the protected functional circuitry is not enabled, and wherein a beginning of the predetermined window of time is independent of reset.
6. The method of claim 1, wherein the IC identifier is provided by the IC via at least one IC terminal, and wherein the input IC security key is received by the IC via said at least one IC terminal.
7. The method of claim 6, wherein said at least one IC terminal comprises a JTAG terminal.
8. The method of claim 1, further comprising forcing access to the protected functional circuitry regardless of a value of the input IC security key.
9. The method of claim 8, wherein said step of forcing comprises providing a force enable value stored in the IC.
10. A method for providing security in an IC having protected functional circuitry and a JTAG interface, said method comprising:
in a first JTAG state, receiving a user defined instruction via the JTAG interface;
in a second JTAG state, receiving an input IC security key via the JTAG interface, wherein the input IC security key is provided by a debug device external to the IC, and wherein the debug device prior to providing the input IC security key evaluates a set of IC identifiers and corresponding IC security key values to determine the input IC security key, and comparing, in the IC, the input IC security key to a stored IC security key; and
selectively enabling access to the protected functional circuitry in the IC via the JTAG interface.
11. The method of claim 10, wherein the first JTAG state corresponds to a SHIFT_IR state.
12. The method of claim 11, wherein the second JTAG state corresponds to a SHIFT_DR state.
13. The method of claim 10, further comprising:
in a third JTAG state, loading an instruction register with the user defined instruction; and
in the second JTAG state, executing the user defined instruction.
14. The method of claim 13, wherein the first JTAG state corresponds to a SHIFT_IR state, the second JTAG state corresponds to a SHIFT_DR state, and the third JTAG state corresponds to a UPDATE_IR state.
15. The method of claim 10, further comprising:
in a third JTAG state, providing an identifier via the JTAG interface.
16. The method of claim 15, wherein the first JTAG state corresponds to a SHIFT_IR state, the second JTAG state corresponds to a SHIFT_DR state, and the third JTAG state corresponds to the SHIFT_IR state.
17. A method for providing security in an IC having protected functional circuitry, comparison circuitry, and at least one IC terminal coupled to the protected functional circuitry, said method comprising:
providing from the IC, an IC identifier;
in response to providing said IC identifier, receiving at the IC an input security key, wherein the input security key is provided by a debug device external to IC, and wherein the debug device prior to providing the input IC security key evaluates a set of IC identifiers and corresponding IC security key values to determine the input IC security key;
accessing the protected functional circuitry via the at least one IC terminal;
programming a force enable indicator to enable the comparison circuitry, wherein the comparison circuitry compares the input IC security key to a stored IC security key and, in response to comparing, selectively enables access to the protected functional circuitry via the at least one IC terminal.
18. The method of claim 17, wherein the force enable indicator comprises a fuse.
19. The method of claim 18, wherein programming the force enable indicator comprises blowing the fuse.
20. A method for providing security in an IC having protected functional circuitry, said method comprising:
executing an instruction in the IC to provide information external to the IC;
in response to executing the instruction in the IC to provide information external to the IC, receiving an input IC security key, wherein the input IC security key is provided by a debug device external to the IC, wherein the debug device prior to providing the input IC security key evaluates a set of IC identifiers and corresponding IC security key values to determine the input IC security key;
comparing, in the IC, the input IC security key to a stored IC security key; and
in response to comparing the input IC security key to a stored IC security key, selectively enabling access to the protected functional circuitry in the IC.
21. A method as in claim 20, wherein the instruction comprises a debug instruction.
22. A method as in claim 21, wherein the debug instruction comprises a JTAG instruction.
23. A method as in claim 21, wherein the debug instruction is executed in preparation for performing a debug operation.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of using a computer to detect data traffic of a mobile device, the computer performing the steps of:
collecting usage data from the mobile device for a time period;
setting threshold values based on a mobile device data plan and an amount of data used by the mobile device within the time period and on historical usage data of the mobile device;
comparing the usage data against the threshold values;
identifying an anomaly if a statistic of the usage data exceeds a corresponding threshold of the threshold values;
generating a graphical user interface including at least one statistic of the usage data; and
overlaying at least one statistic of the existing usage data or predicted data or both onto the at least one statistic of the usage data.
2. The method of claim 1, wherein the weighting afforded the historical usage data is related to the amount of stored history.
3. The method of claim 1, wherein the weighting afforded the historical usage data increases as the amount of stored history increases up to a maximum weighted percentage for the historical usage data.
4. The method of claim 1, further comprising the step of updating the threshold values based on a running average of each statistic of the usage data.
5. The method of claim 1, wherein the time period corresponds to a data plan period.
6. The method of claim 1, wherein the collecting step comprises:
reading, at a first interval, data traffic statistics from a network interface on the mobile device;
adding the data traffic statistics to running totals on the mobile device.
7. The method of claim 6, wherein the collecting step further comprises:
when the running totals exceed a delivery threshold,
sending the running totals to the server; and
adjusting the running totals.
8. The method of claim 1, wherein the collecting step further comprises:
when a delivery timer expires,
sending the running totals to the server; and
adjusting the running totals.
9. The method of claim 1, wherein threshold values include a data limit for the given time period.
10. The method of claim 1, the computer further performing the steps of:
extrapolating data traffic statistics to the end of the given time period;
if a statistic of the extrapolated data traffic statistics exceeds a corresponding threshold value of the threshold values, flagging an anomaly.
11. A method of using a computer to detect data traffic of a mobile device, the computer performing the steps of:
collecting from the mobile device, usage data relating to data usage for the mobile device for a given time period;
setting threshold values based at least in part on a mobile device data plan and an amount of data used by the mobile device within a set time period;
comparing the usage data against the threshold values;
identifying a statistic of the usage data exceeding a corresponding threshold of the threshold values;
generating report based on the identified statistic wherein the report includes a comparison between historical usage data associated with a second given time period to the usage data, the second given time period prior to the given time period;
presenting the report on a Graphical User Interface (GUI) so that a user of the mobile device can assess changes in their data usage in order to avoid overages.
12. The method of claim 11 wherein the threshold values are further set based on historical usage data of the mobile device, where weighting afforded the historical usage data in comparison to the amount of data used by the mobile device within the set time period is related to the amount of stored history
13. The method of claim 12, wherein the weighting afforded the historical usage data increases as the amount of stored history increases up to a maximum weighted percentage for the historical usage data.
14. The method of claim 11 wherein the identified statistic is average data usage for the mobile device over more than one set time period.
15. The method of claim 11, wherein the threshold values are set based on a running average of each statistic of the usage data is based on formula I,
T
0

=
T
0

+

Max
T
0

\xd7

\u0394
max
100

,
T
0

\ue89e
(
\u2211

i
=
1

N

\ue89e

T
i
–

Max
\ue8a0

(
T
1

,
\u2026
\ue89e
,

T
N
)
)
N
–
1
wherein T0 is a current threshold value;
\u0394max is the maximum change of the threshold value, expressed as a percentage;
Ti is the value of a corresponding data traffic statistic i time periods prior to the current period; and
N is the number of time periods used to compute the updated threshold.
16. The method of claim 11, wherein the given time period corresponds to a data plan period.
17. The method of claim 11, wherein the collecting step comprises:
reading, at a first interval, data traffic statistics from a network interface on the mobile device;
adding the data traffic statistics to running totals on the mobile device.
18. The method of claim 17, wherein the collecting step further comprises:
when a delivery timer expires,
sending running totals of data usage to a server wherein the collecting step is performed at the server; and
adjusting the running totals.
19. The method of claim 11, wherein the collecting step further comprises:
when a delivery timer expires,
sending the running totals to the server; and
adjusting the running totals.
20. The method of claim 11, wherein threshold values include a data limit for the given time period.
21. The method of claim 11, the computer further performing the steps of:
extrapolating data traffic statistics to the end of the given time period;
if a statistic of the extrapolated data traffic statistics exceeds a corresponding threshold value of the threshold values, flagging an anomaly and presenting the anomaly on the Graphical User Interface (GUI).

1. A semiconductor device for use in a stacked multi-chip assembly, comprising:
a semiconductor die; and
a dielectric spacer layer secured to at least a portion of a surface of the semiconductor die and protruding from the surface to space the semiconductor die substantially a predetermined distance from an adjacent semiconductor die to accommodate a height of at least one intermediate conductive element that includes a bonding portion secured to a contact of the semiconductor die and a laterally extending portion located between and electrically isolated from an active surface of the semiconductor die and a back side of the adjacent semiconductor die, the dielectric spacer layer including voids communicating with a lateral periphery thereof.
2. The semiconductor device of claim 1, wherein the dielectric spacer layer comprises a plurality of laterally discrete spacers.
3. The semiconductor device of claim 1, further comprising:
at least one discrete conductive element protruding above a surface of the semiconductor die.
4. The semiconductor device of claim 3, wherein the at least one discrete conductive element comprises one of a bond wire, a thermocompression bonded lead, and a tape-automated bond element.
5. The semiconductor device of claim 1, wherein the predetermined distance exceeds a distance a discrete conductive element protrudes above a surface of at least one of the semiconductor die and the adjacent semiconductor die.
6. The semiconductor device of claim 1, wherein the predetermined distance is about the same as or less than a distance a discrete conductive element protrudes above a surface of at least one of the semiconductor die and the adjacent semiconductor die.
7. The semiconductor device of claim 1, wherein the dielectric spacer layer covers only a portion of the surface.
8. The semiconductor device of claim 7, wherein the dielectric spacer layer comprises a pattern.
9. The semiconductor device of claim 7, wherein the dielectric spacer layer comprises randomly arranged features.
10. The semiconductor device of claim 1, wherein the dielectric spacer layer comprises a material that will adhere to a surface of the adjacent semiconductor die.
11. The semiconductor device of claim 1, wherein the dielectric spacer layer comprises a polymer.
12. The semiconductor device of claim 11, wherein the polymer comprises a photoimageable polymer.
13. The semiconductor device of claim 1, wherein the dielectric spacer layer comprises at least one of a glass, a silicon dioxide, a silicon nitride, and a silicon oxynitride.
14. The semiconductor device of claim 1, wherein the dielectric spacer layer is positioned on the active surface of the semiconductor die.
15. The semiconductor device of claim 1, wherein the dielectric spacer layer is positioned on a back side of the semiconductor die.
16. The semiconductor device of claim 1, further comprising:
another dielectric spacer layer covering at least a portion of an opposite surface of the semiconductor die.
17. The semiconductor device of claim 1, further comprising:
adhesive material on an exposed surface of the dielectric spacer layer.
18. The semiconductor device of claim 1, wherein the dielectric spacer layer comprises a plurality of at least partially superimposed, contiguous, adhered sublayers.
19. A semiconductor device assembly, comprising:
a first semiconductor device including an active surface carrying bond pads that are configured to have intermediate conductive elements secured thereto;
a nonconfluent spacer layer comprising dielectric material secured to the active surface of the first semiconductor device and, prior to securing an intermediate conductive element to any of the bond pads, protruding from the active surface substantially a same distance the active surface of the first semiconductor device is to be spaced apart from a back side of a second semiconductor device; and
the second semiconductor device, including a back side secured to the nonconfluent spacer layer.
20. The semiconductor device assembly of claim 19, wherein the nonconfluent spacer layer comprises at least one void therein that communicates with a lateral periphery of the nonconfluent spacer layer.
21. The semiconductor device assembly of claim 20, wherein the at least one void facilitates lateral introduction of adhesive material between the first and second semiconductor devices.
22. The semiconductor device assembly of claim 19, wherein the nonconfluent spacer layer comprises a plurality of laterally discrete spacers.
23. The semiconductor device assembly of claim 19, wherein the nonconfluent spacer layer has a substantially uniform thickness.
24. The semiconductor device assembly of claim 19, further comprising:
at least one intermediate conductive element protruding above the active surface of the first semiconductor device and located at least partially between the first and second semiconductor devices.
25. The semiconductor device assembly of claim 24, wherein the nonconfluent spacer layer has a thickness that spaces the first and second semiconductor devices apart from one another a distance that exceeds a height the at least one intermediate conductive element protrudes above the active surface of the first semiconductor device.
26. The semiconductor device assembly of claim 24, wherein the nonconfluent spacer layer has a thickness that spaces the first and second semiconductor devices apart from one another a distance that is about the same as or less than a height the at least one discrete conductive element protrudes above the active surface of the first semiconductor device.
27. The semiconductor device assembly of claim 19, wherein the nonconfluent spacer layer comprises dielectric material.
28. The semiconductor device assembly of claim 19, wherein the nonconfluent spacer layer comprises a polymer.
29. The semiconductor device assembly of claim 28, wherein the polymer adheres to surfaces of the first semiconductor device and the second semiconductor device.
30. The semiconductor device assembly of claim 28, wherein the polymer comprises a photoimageable polymer.
31. The semiconductor device assembly of claim 19, wherein the nonconfluent spacer layer comprises a plurality of at least partially superimposed, contiguous, mutually adhered sublayers.
32. The semiconductor device assembly of claim 19, wherein the nonconfluent spacer layer comprises at least one of a glass, a silicon oxide, a silicon nitride, and a silicon oxynitride.
33. The semiconductor device assembly of claim 19, wherein the nonconfluent spacer layer comprises a pattern.
34. The semiconductor device assembly of claim 19, wherein the nonconfluent spacer layer comprises randomly arranged features.
35. The semiconductor device assembly of claim 19, further comprising:
an adhesive material securing the nonconfluent spacer layer to at least one of the active surface of the first semiconductor device and the active surface of the second semiconductor device.
36. The semiconductor device assembly of claim 35, wherein the adhesive material is located within voids in the nonconfluent spacer layer.
37. The semiconductor device assembly of claim 19, further comprising:
a substrate upon which the first semiconductor device is positioned.
38. The semiconductor device assembly of claim 37, wherein at least one bond pad of at least one of the first semiconductor device and the second semiconductor device is in communication with a corresponding contact area of the substrate.
39. The semiconductor device assembly of claim 37, wherein the substrate comprises at least one of a circuit board, an interposer, another semiconductor device, and leads.
40. The semiconductor device assembly of claim 19, further comprising:
at least one additional semiconductor device.
41. semiconductor device assembly of claim 19, wherein the nonconfluent spacer layer comprises a plurality of layers, additive thicknesses of the plurality of layers defining substantially the same distance.
42. The semiconductor device assembly of claim 41, wherein a first layer of the plurality of layers is secured to the active surface of the first semiconductor device and a second layer of the plurality of layers is configured to be secured to the back side of the second semiconductor device.
43. The semiconductor device assembly of claim 41, wherein at least some solid regions of each of the plurality of layers are at least partially superimposed relative to one another.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A substrate processing apparatus which laminates layers of resultants of at least two kinds of mutually reactive gases and forms a thin film on a surface of a substrate by performing a gas supply cycle to supply sequentially the reactive gases to the surface of the substrate in a vacuum chamber,
the substrate processing apparatus comprising:
a film deposition device to perform a film deposition process of the substrate;
a vacuum conveying chamber airtightly connected to the film deposition device;
a conveying unit disposed in the vacuum conveying chamber to convey the substrate between the film deposition device and the vacuum conveying chamber;
a heat processing device including a processing container airtightly connected to the vacuum conveying chamber and including a substrate mounting base provided therein and a unit to perform heat processing of the substrate on the mounting base;
a substrate rotating unit arranged in the vacuum conveying chamber or the heat processing device to cause the substrate on the conveying unit to rotate around a vertical axis of the substrate; and
a control unit to output a control signal so that a film deposition process of the substrate is carried out,
the film deposition device comprising:
a table arranged in the vacuum chamber;
a plurality of reactive gas supplying units arranged to face an upper surface of the table and mutually separated in a circumferential direction of the table to supply the reactive gases to the surface of the substrate respectively;
a separating gas supplying unit to supply a separating gas;
an isolation area disposed between a plurality of processing areas to which the reactive gases are respectively supplied from the plurality of reactive gas supplying units, the separating gas being supplied from the separating gas supplying unit to the isolation area so that atmospheres of the plurality of processing areas are divided by the separating gas in the isolation area;
a rotation device to rotate the plurality of reactive gas supplying units, the separating gas supplying unit and the table relative to each other around a vertical axis of the table;
a substrate mounting area arranged in the table along a direction of rotation of the rotation device so that the substrate located in the substrate mounting area is moved sequentially to the plurality of processing areas and the isolation area by the rotation of the rotation device; and
an evacuation unit to perform evacuation of the inside of the vacuum chamber,
wherein the control unit is arranged to stop the relative rotation of the plurality of reactive gas supplying units, the separating gas supplying unit and the table by the rotation device in the middle of the film deposition process, cause the conveying unit to take out the substrate from the vacuum chamber, and output a control signal that causes the substrate rotating unit to change a direction of the substrate.
2. The substrate processing apparatus according to claim 1, wherein the substrate processing apparatus is arranged so that the substrate sequentially passes through the plurality of processing areas and the isolation area by rotation of the table,
the plurality of reactive gas supplying units comprise:
a first reactive gas supplying unit to supply a first reactive gas to the substrate so that the first reactive gas is adsorbed by the substrate;
an auxiliary gas supplying unit to supply to the substrate an auxiliary gas that reacts with the first reactive gas adsorbed by the substrate to generate an intermediate product having a flowability; and
a second reactive gas supplying unit to supply to the substrate a second reactive gas that reacts with the intermediate product to generate a resultant,
the first reactive gas supplying unit, the auxiliary gas supplying unit, and the second reactive gas supplying unit being sequentially disposed at downstream positions of a conveyance opening in a direction of rotation of the table, the conveyance opening being formed to deliver the substrate between the film deposition device and the vacuum conveying chamber, and
the heat processing device is arranged so that the resultant is closely packed by performing the heat processing of the substrate.
3. The substrate processing apparatus according to claim 2, further comprising a plasma supplying unit disposed between the second reactive gas supplying unit and the conveyance opening in the direction of rotation of the table to supply a plasma to the substrate on the table.
4. The substrate processing apparatus according to claim 2, further comprising a third reactive gas supplying unit disposed between the first reactive gas supplying unit and the conveyance opening to face the substrate on the table to supply a third reactive gas to the surface of the substrate, so that the third reactive gas is adsorbed by the surface of the substrate and at least one of boron and phosphorus in the third reactive gas is mixed with the resultant.
5. The substrate processing apparatus according to claim 1, wherein the isolation area includes a top surface disposed on both sides of the separating gas supplying unit in the direction of rotation of the rotation device to form a narrow space between the top surface and the table to allow the separating gas from the isolation area to flow into the processing areas through the narrow space.
6. The substrate processing apparatus according to claim 1, further comprising a central part area disposed at a central part of the vacuum chamber to divide the atmospheres of the plurality of the processing areas, the central part area including a discharge hole formed therein to discharge the separating gas from the discharge hole to the substrate mounting surface of the table,
wherein the reactive gases are discharged by the evacuation unit together with the separating gas diffused on both sides of the isolation area and the separating gas discharged from the central part area.
7. A substrate processing method which laminates layers of resultants of at least two kinds of mutually reactive gases and fauns a thin film on a surface of a substrate by performing a gas supply cycle to supply sequentially the reactive gases to the surface of the substrate in a vacuum chamber of a film deposition device by using a substrate processing apparatus, the substrate processing method comprising:
placing the substrate in a substrate mounting area of a table arranged in the vacuum chamber;
supplying, by a plurality of reactive gas supplying units of the film deposition device, the reactive gases respectively to a surface of the substrate in the substrate mounting area of the table, the plurality of reactive gas supplying units being arranged to face an upper surface of the table and mutually separated in a circumferential direction of the table;
supplying, by a separating gas supplying unit of the film deposition device, a separating gas to an isolation area to divide atmospheres of a plurality of processing areas to which the reactive gases are respectively supplied from the plurality of reactive gas supplying units and prevent the reactive gases from entering the isolation area, the isolation area being disposed between the plurality of processing areas;
rotating, by a rotation device of the film deposition device, the plurality of reactive gas supplying units, the separating gas supplying unit and the table relative to each other around a vertical axis of the table;
performing, by the film deposition device, a film deposition process of the substrate so that the substrate located in the substrate mounting area is moved sequentially to the plurality of processing areas and the isolation area by the rotation of the rotation device;
stopping, by a control unit of the substrate processing apparatus, the relative rotation of the plurality of reactive gas supplying units, the separating gas supplying unit and the table by the rotation device in the middle of the film deposition process;
taking out, by a conveying unit of the substrate processing apparatus, the substrate from the film deposition device;
causing, by a substrate rotating unit of the substrate processing apparatus, the substrate to rotate around a vertical axis of the substrate so that a direction of the substrate is changed; and
conveying, by a conveying unit of the substrate processing apparatus, the substrate, taken out from the film deposition device after the direction of the substrate is changed, to a heat processing device of the substrate processing apparatus so that a heat processing of the substrate is performed by the heat processing device.
8. The substrate processing method according to claim 7, wherein the performing the film deposition process comprises:
rotating the table;
supplying, by a first reactive gas supplying unit of the substrate processing apparatus, a first reactive gas to the surface of the substrate so that the first reactive gas is adsorbed by the substrate;
supplying, by an auxiliary gas supplying unit of the substrate processing apparatus, to the substrate an auxiliary gas that reacts with the first reactive gas adsorbed by the substrate to generate an intermediate product having a flowability; and
supplying, by a second reactive gas supplying unit of the substrate processing apparatus, to the substrate a second reactive gas that reacts with the intermediate product to generate a resultant,
wherein the heat processing of the substrate is performed so that the resultant is closely packed.
9. A computer-readable storage medium storing a program which, when executed by a computer, causes the computer to perform the substrate processing method according to claim 7.