Author: claimsbot

1. A method comprising:
mapping a shared memory into first and second virtual address spaces, with the shared memory holding buffer data structures and non-buffer data structures, with the buffer data structures and non-buffer data structures shared between InputOutput (IO) devices which send and receive packets and a Central Processing Unit (CPU);
setting a cache attribute for the first virtual address space and utilizing the cache write through algorithm when writing cached data with addresses in the first virtual address space, where the first virtual address space is utilized only by the CPU and the CPU utilizes addresses in the first virtual address space to access only buffer data structures;
reporting addresses in the first virtual address space to code executed by the CPU which implements switching;
returning pointers to buffer data structures, which store packet data, where pointers returned point to addresses in the first virtual address space when allocating memory;
setting a non-cache attribute for the second virtual address space, where non-buffer data structures held in the shared memory are accessed utilizing addresses in the second address space;
converting a returned pointer to a buffer data structure from a pointer to an address in the first virtual address space to a converted pointer to a corresponding address in the second virtual address space prior to passing the pointer from the CPU to an IO device;
at the IO device, using the converted pointer to access packet data stored in a buffer data structure in the shared memory; and
at the CPU, invalidating the cache lines corresponding to the addresses of a received packet before accessing data in the received packet.
2. The method of claim 1 further comprising the step of:
using physical addresses of the shared IO memory in the second virtual address space.
3. The method of claim 1 further comprising the step of:
mapping the first virtual address space so that only a most significant bit is different from the physical address.
4. The method of claim 3 where said step of converting comprises the step of:
changing a bit value of the most significant bit in the address pointed to by the return pointer.
5. The method of claim 1 further comprising the steps of:
converting pointers returned to addresses of non-buffer data structures in the first virtual address space in shared IO memory to converted pointers to corresponding addresses in the second virtual address space; and
utilizing the converted pointers at the CPU to access said non-buffer data structures.
6. One or more computer readable storage media encoded with software comprising computer executable instructions and when the software is executed operable to:
map a shared to memory into first and second virtual address spaces, with the shared memory including buffer data structures and non-buffer data structures, with the buffer data structures and non-buffer data structures shared between InputOutput (IO) devices which send and receive packets and a Central Processing Unit (CPU);
set a cache attribute for the first virtual address space and utilize the cache write through algorithm when writing cached data with addresses in the first virtual address space, where the first virtual address space and utilize the cache write through algorithm when writing cached data with addresses int he first virtual address space, where the first virtual address space is utilized only by the CPU and the CPU utilizes addresses int he first virtual address space to access only buffer data structures;
report addresses in the first virtual address space to code executed by the CPU which implements switching;
return pointers to buffer data structures, which store packet data, where pointers returned point to addresses in the first virtual address space when allocating memory;
set a non-cache attribute for the second virtual address space, where non-buffer data structures held in the shared memory are accessed utilizing addresses in the second virtual address space;
convert a returned pointer to a buffer data structure from a pointer to an address in the first virtual address space to a converted pointer to a corresponding address in the second virtual address space prior to passing the pointer from the CPU to an IO device;
cause said IO device to use the converted pointer to access packet data stored in a buffer data structure in the shared memory; and
cause the CPU to invalidate cache lines corresponding to the addresses of a received packet before accessing data in the received packet.
7. The computer readable storage media of claim 6 encoded with software when executed further operable to:
use physical addresses of the shared IO memory in the second virtual address space.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A hearing aid, comprising:
an input system;
an output system;
a solid state tunneling magnetic sensor generating a magnetic field signal;
a processor configured to be programmed to process signals from the input system and provide the processed signals to the output system,
wherein the processor is configured to receive the magnetic field signal from the sensor, and is programmable to select parameters for signal processing using a first digital filter or a second digital filter, the selection of either the first digital filter or the second digital filter based at least in part on the magnetic field signal.
2. The hearing aid of claim 1, wherein the solid state tunneling magnetic sensor includes a spin dependent tunneling (SDT) device.
3. The hearing aid of claim 2, wherein the SDT device is fabricated using photolithography.
4. The hearing aid of claim 2, wherein the SDT device includes a saturation field range from 0.1 to 10 kAm.
5. The hearing aid of claim 2, wherein the SDT device is configured to be used as a hearing aid switch.
6. The hearing aid of claim 2, wherein the SDT device is configured to provide hearing aid programming signals.
7. The hearing aid of claim 2, wherein the SDT device includes a giant magnetoresistivity (GMR) material layer, and wherein the SDT device includes a conduction path perpendicular to a plane of the GMR material layer.
8. The hearing aid of claim 1, wherein the input system includes a microphone.
9. The hearing aid of claim 1, wherein the input system is configured to switch from an acoustic input to a magnetic input based on the magnetic field signal.
10. The hearing aid of claim 9, wherein the magnetic input includes a telecoil.
11. A hearing aid, comprising:
a power source;
a hearing aid circuit; and
a solid state tunneling magnetic sensor configured to connect the power source to the hearing aid circuit, wherein the sensor is configured to disconnect the power source from the hearing aid circuit when in the presence of a sufficiently strong magnetic field.
12. The hearing aid of claim 11, wherein the solid state tunneling magnetic sensor includes a spin dependent tunneling (SDT) device.
13. The hearing aid of claim 12, wherein the SDT device is fabricated using photolithography.
14. The hearing aid of claim 12, wherein the SDT device includes a saturation field range from 0.1 to 10 kAm.
15. The hearing aid of claim 11, wherein the power source is a battery.
16. The hearing aid of claim 15, wherein the battery is rechargeable.
17. The hearing aid of claim 12, wherein the SDT device includes a giant magnetoresistivity (GMR) material layer, and wherein the SDT device includes a conduction path perpendicular to a plane of the GMR material layer.
18. The hearing aid of claim 11, further comprising a filter connected to the hearing aid circuit, wherein the solid state tunneling magnetic sensor is configured to electrically disconnect the filter from the hearing aid circuit when in the presence of a sufficiently strong magnetic field.
19. The hearing aid of claim 11, wherein the solid state tunneling magnetic sensor is further configured to operate as a programming circuit to program the hearing aid.
20. The hearing aid of claim 11, further comprising at least one acoustic input connected to the hearing aid circuit, wherein the solid state tunneling magnetic sensor is configured to inhibit the acoustic input in the presence of a magnetic field.

1. A thin film transistor array panel, comprising:
a first substrate;
a gate line and a data line on the first substrate;
a storage electrode line on the first substrate, wherein a constant voltage is applied thereto;
a first thin film transistor and a second thin film transistor which are connected to the gate line and the data line;
a third thin film transistor which is connected to the gate line, the second thin film transistor and the storage electrode line;
a first subpixel electrode which is connected to the first thin film transistor; and
a second subpixel electrode which is connected to the second thin film transistor.
2. The thin film transistor array panel of claim 1, further comprising:
an auxiliary electrode which protrudes from the storage electrode line;
a first gate electrode and a second gate electrode which protrude from the gate line and are connected to each other;
a first source electrode which protrudes from the data line and overlaps the first gate electrode, and a first drain electrode which is spaced apart from the first source electrode; and
a second source electrode which is connected to the first source electrode and overlaps the second gate electrode, and a second drain electrode which is spaced apart from the second source electrode;
wherein
the first thin film transistor comprises the first gate electrode, the first source electrode and the first drain electrode;
the second thin film transistor comprises the second gate electrode, the second source electrode and the second drain electrode, and
the third film transistor comprises:
a third gate electrode which protrudes from the gate line in a same direction as the first gate electrode and the second gate electrode, and is spaced apart from the second gate electrode;
a third source electrode which is connected to the second drain electrode and overlaps the third gate electrode; and
a third drain electrode which is spaced apart from the third source electrode and overlaps the third gate electrode and the auxiliary electrode.
3. The thin film transistor array panel of claim 2, further comprising:
a connection electrode which connects the third drain electrode and the auxiliary electrode to each other.
4. The thin film transistor array panel of claim 2, wherein:
the second drain electrode and the third source electrode are between the second gate electrode and the third gate electrode which are spaced apart from each other.
5. The thin film transistor array panel of claim 4, wherein:
the first source electrode and the second source electrode are curved in a \u2018C\u2019 shape.
6. The thin film transistor array panel of claim 5, wherein:
the first drain electrode and the second drain electrode each include:
a first portion having a rod shape; and
a second portion which is connected to the first portion and is wider than the first portion,

the first portion of first drain electrode is enclosed by the first source electrode,
the first portion of the second drain electrode is enclosed by the second source electrode, and
the first portion of the second drain electrode is connected to the third source electrode via the second portion of the second drain electrode.
7. The thin film transistor array panel of claim 6, further comprising:
a gate insulating layer on the gate line, the first gate electrode, the second gate electrode and the third gate electrode; and
a passivation layer on the first, second and third source electrodes and on the first, second and third drain electrodes.
8. The thin film transistor array panel of claim 7, wherein
the passivation layer comprises:
a first contact hole which exposes a portion of the first drain electrode; and
a second contact hole which exposes a portion of the second drain electrode; and

the passivation layer and the gate insulating layer comprise a third contact hole which exposes a portion of the third drain electrode and a portion of the auxiliary electrode.
9. The thin film transistor array panel of claim 8, further comprising:
a connection electrode which is connected to the third drain electrode and the auxiliary electrode through the third contact hole,
wherein
the first subpixel electrode is connected to the first drain electrode through the first contact hole, and
the second subpixel electrode is connected to the second drain electrode through the second contact hole.
10. The thin film transistor array panel of claim 9, wherein:
the portion of the auxiliary electrode exposed by the third contact hole does not overlap the third drain electrode.
11. The thin film transistor array panel of claim 9, wherein:
the connection electrode includes a same material, and is in a same layer as the first subpixel electrode and the second subpixel electrode.
12. The thin film transistor array panel of claim 4, further comprising:
an extension electrode which extends from the third gate electrode and is spaced apart from the first gate electrode.
13. The thin film transistor array panel of claim 12, wherein:
the first drain electrode includes:
a first portion which has a rod shape, is enclosed by the first source electrode and overlaps the first gate electrode;
a second portion which is connected to the first portion, is wider than the first portion and is between the first gate electrode and the extension electrode; and
a third portion which is connected to the second portion, has a rod shape, is wider than the second portion and overlaps the extension electrode.
14. The thin film transistor array panel of claim 3, further comprising:
a dummy line which overlaps the data line.
15. The thin film transistor array panel of claim 14, wherein:
the dummy line is connected to the storage electrode line.
16. The thin film transistor array panel of claim 14, wherein:
the dummy line is connected to the connection electrode.
17. The thin film transistor array panel of claim 16, wherein:
the dummy line includes a same material and is in a same layer as the connection electrode, the first subpixel electrode and the second subpixel electrode.
18. A liquid crystal display, comprising:
a first substrate and a second substrate;
a liquid crystal layer between the first substrate and the second substrate;
a gate line, a data line and a storage electrode line on the first substrate;
a first thin film transistor and a second thin film transistor which are connected with the gate line and the data line;
a third thin film transistor which is connected to the gate line, the second thin film transistor and the storage electrode line;
a first subpixel electrode which is connected to the first thin film transistor;
a second subpixel electrode which is connected to the second thin film transistor; and
a common electrode on the second substrate, wherein the common electrode forms an electric field with the first subpixel electrode and the second subpixel electrode.
19. The liquid crystal display of claim 18, further comprising:
an auxiliary electrode which protrudes from the storage electrode line;
a first gate electrode and a second gate electrode which protrude from the gate line and are connected to each other;
a first source electrode which protrudes from the data line and overlaps the first gate electrode, and a first drain electrode which is spaced apart from the first source electrode; and
a second source electrode which is connected to the first source electrode and overlaps the second gate electrode, and a second drain electrode which is spaced apart from the second source electrode;
wherein
the first thin film transistor comprises the first gate electrode, the first source electrode and the first drain electrode;
the second thin film transistor comprises the second gate electrode, the second source electrode and the second drain electrode, and
the third film transistor comprises:
a third gate electrode which protrudes from the gate line in a same direction as the first gate electrode and the second gate electrode, and is spaced apart from the second gate electrode;
a third source electrode which is connected to the second drain electrode and overlaps the third gate electrode; and
a third drain electrode which is spaced apart from the third source electrode and overlaps the third gate electrode and the auxiliary electrode.
20. The liquid crystal display of claim 19, further comprising:
a connection electrode which connects the third drain electrode and the auxiliary electrode to each other,
wherein the second drain electrode and the third source electrode are between the second gate electrode and the third gate electrode which are spaced apart from each other.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A compound represented by the following general formula (1) wherein A represents a five- to fourteen membered aromatic group, which may be substituted, or a cycloaliphatic hydrocarbon group, which may be substituted, having from three to ten carbon atoms;
the partial structure -DE- represents a group represented by CH2CH2 or CHCH;
W represents a group represented by CH2, CH2CH2, CHCH or CH; the partial structure >XY represents a group represented by the formula >CH(CH2)n, wherein n is an integer of 0 or 1; >CCH; >CHCH2CH(OH); >CHCH2C(O); >CHO; or >CHOCO, provided that when W is CH, then XY represents the formula C(CH2)p, wherein p is an integer of 0 or 1;
Z represents a divalent aliphatic hydrocarbon group having from zero to eight carbon atoms;
R1 and R2, which may be the same or different, each represents a hydrogen atom, a hydroxyl group, a C1-6 alkoxy group or a C1-6 alkoxy-C1-6 alkoxy group, provided that when R2 represents a hydrogen atom, R1 also represents a hydrogen atom;
m is an integer of 0 or 1, and when w represents CH2 or CH, then m is 0, and when w represents (CH2)2 or CHCH, then m is 1;
with exception of the compound represented by the following formula X; or salts thereof or hydrates thereof:
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2. The compound according to claim 1, wherein A is a five- to fourteen-membered aromatic heterocyclic group, which may be substituted; or salts thereof or hydrates thereof.
3. The compound according to claim 1, wherein A is a phenyl, naphthyl, pyridyl, pyridazinyl, pyrimidinyl, pyrazinyl, thienyl, furyl, oxazolyl or thiazolyl group, each of which may be substituted; or salts thereof or hydrates thereof.
4. The compound according to claim 1, wherein A is a phenyl or pyridyl group, each of which may be substituted; or salts thereof or hydrates thereof.
5. The compound according to any one of claims 1 to 4, wherein R2 andor R1 are a hydroxyl group; or salts thereof or hydrates thereof.
6. The compound according to any one of claims 1 to 4, wherein R1 andor R2 are a C1-6 alkoxy-C1-6 alkoxy group; or salts thereof or hydrates thereof.
7. The compound according to any one of claims 1 to 6, wherein the partial structure -DE- represents a group represented by CHCH; or salts thereof or hydrates thereof.
8. The compound according to any one of claims 1 to 7, wherein W represents a group represented by CH2 or CH, and wherein m is 0; or salts thereof or hydrates thereof.
9. The compound according to any one of claims 1 to 7,wherein W represents a group represented by (CH2)2 or CHCH, and wherein m is 1; or salts thereof or hydrates thereof.
10. The compound according to any one of claims 1 to 9, wherein the partial structure >XY represents a group represented by the formula >CH(CH2)n (wherein n is an integer of 0 or 1), the formula >CCH, the formula >CHCH2CH(OH), the formula >CHCH2C(O) or the formula >CHO; or salts thereof or hydrates thereof.
11. The compound according to any one of claims 1 to 9, wherein the partial structure >XY represents a group represented by the formula >CH(CH2)n (wherein n is an integer of 0 or 1); or salts thereof or hydrates thereof.
12. The compound according to claim 1, wherein A is an aromatic or cycloaliphatic group which may have one to three groups selected from a hydroxyl group or an alkoxy group which may be substituted; or salts thereof or hydrates thereof.
13. The compound according to claim 1, wherein the compound is selected from 5-benzyl-1-cyclooctanone, 5-phenethyl-1-cyclooctanone, 5-(2-pyridylmethyl)-1-cyclooctanone, 5-2-(2-hydroxyphenyl)ethyl-1-cyclooctanone, 5-2-(2-hydroxy-4-methoxyphenyl)ethyl-1-cyclooctanone, 5-benzyl-2-cycloocten-1-one, 5-phenethyl-2-cycloocten-1-one, 5-(2-pyridylmethyl)-2-cycloocten-1-one, 5-2-(2-hydroxy-4-methoxyphenyl)ethyl-2-cycloocten-1-one, 5-benzyl-8-hydroxy-2-cycloocten-1-one, 5-benzyl-7,8-dihydroxy-2-cycloocten-1-one, 2,3-dihydroxy-5-2-(2-hydroxyphenyl)ethyl-1-cyclooctanone, 5-oxocyclooctylbenzoate, 5-oxo-3-cyclooctenylbenzoate, 5-oxocyclooctyl2-hydroxybenzoate, 5-oxo-3-cyclooctenyl2-hydroxybenzoate, 5-oxo-3-cyclooctenyl(2-methoxymethoxy)benzoate, 5-oxocyclooctyl(2-hydroxy-4-methoxy)benzoate, 5-oxo-3-cyclooctenyl(2-hydroxy-4-methoxy)benzoate, 5-oxo-3-cyclooctenyl2-nitrobenzoate, 3,4-dihydroxy-5-oxocyclooctylbenzoate, 6,7-dihydroxy-5-oxo-3-cyclooctenylbenzoate, 6,7-dihydroxy-5-oxo-3-cyclooctenyl2-hydroxybenzoate, 3,4-dihydroxy-5-oxocyclooctyl(2-methoxymethoxy)benzoate, 3,4-dihydroxy-5-oxocyclooctyl(2-hydroxy-4-methoxy)benzoate, 6,7-dihydroxy-5-oxo-3-cyclooctenyl(2-hydroxy-4-methoxy)-benzoate, 6,7-dihydroxy-5-oxo-3-cyclooctenyl2-nitrobenzoate, 6-benzyl-1-cyclodecanone, 6-phenethyl-1-cyclodecanone, 6-(2-pyridylmethyl)-1-cyclodecanone, 6-2-(2-hydroxyphenyl)ethyl-1-cyclodecanone, 6-2-(2-hydroxy-4-methoxyphenyl)ethyl1-cyclodecanone, 6-benzyl-2-cyclodecen-1-one, 6-phenethyl-2-cyclodecen-1-one, 6-(2-pyridylmethyl)-2-cyclodecen-1-one, 6-2-(2-hydroxy-4-methoxyphenyl)ethyl-2-cyclodecen-1-one, 6-benzyl-10-hydroxy-2-cyclodecen-1-one, 6-benzyl-9,10-dihydroxy-2-cyclodecen-1-one, 9,10-dihydroxy-6-phenethyl-cyclodecen-1-one, 9,10-dihydroxy-6-2-(2-hydroxyphenyl)ethylcyclodecen-1-one, 6-oxocyclodecylbenzoate, 6-oxo-4-cyclodecenylbenzoate, 6-oxocyclodecyl2-hydroxybenzoate, 6-oxo-4-cyclodecenyl2-hydroxybenzoate, 6-oxo-4-cyclodecenyl4-methoxybenzoate, 6-oxocyclodecyl(2-hydroxy-4-methoxy)benzoate, 6-oxo-4-cyclodecenyl(2-hydroxy-4-methoxy)benzoate, 6-oxocyclodecyl2-nitorobenzoate, 6-oxo-4-cyclodecenyl2-nitrobenzoate, 4,5-dihydroxy-6-oxocyclodecylbenzoate, 7,8-dihydroxy-6-oxo-4-cyclodecenylbenzoate, 7,8-dihydroxy-6-oxo-4-cyclodecenyl(2-methoxymethoxy)-benzoate, 7,8-dihydroxy-6-oxo-4-cyclodecenyl4-methoxybenzoate, 7,8-dihydroxy-6-oxo-4-cyclodecenyl(2-hydroxy-4-methoxy)-benzoate, 4,5-dihydroxy-6-oxocyclodecyl2-nitrobenzoate, or 7,8-dihydroxy-6-oxo-4-cyclodecenyl2-nitrobenzoate; or salts thereof or hydrates thereof.
14. A pharmaceutical composition comprising the compound according to claim 1 or salts thereof or hydrates thereof.
15. An agent for inhibiting cytokine production, wherein the agent comprises the compound according to claim 1.
16. An agent for inhibiting TNF- production, IL-6 production or IL-2 production, wherein the agent comprises the compound according to claim 1.
17. An agent for treating or preventing diseases which is associated with cytokine, wherein the agent comprises the compound according to claim 1.
18. An agent for treating or preventing chronic rheumatoid arthritis, ulcerative colitis, glomerulonephritis, osteoarthritis, atopic dermatitis, endotoxin shock, sepsis, diabetes, viral hepatitis, mesangial proliferative glomerulonephritis, adenoviral ophthalmia or AIDS, wherein the agent comprises the compound according to claim 1.