Author: claimsbot

1. A method of making a display device, comprising:
providing a display substrate having an array of pixels formed in rows and columns, the rows of pixels separated by row inter-pixel gaps and the columns of pixels separated by column inter-pixel gaps;
providing a transparent dielectric layer located over the display substrate, the transparent dielectric layer having a row side and an opposed column side;
providing row electrodes spaced apart by row inter-electrode gaps located on the row side of the transparent dielectric layer and column electrodes spaced apart by column inter-electrode gaps located on the column side of the transparent dielectric layer, the row and column electrodes separated by the transparent dielectric layer; and
providing ground lines located between neighboring row electrodes in the row inter-electrode gaps and between the pixels in a row inter-pixel gap.
2. The method of claim 1, wherein the display substrate has a substantially planar first display substrate side and a substantially planar second display substrate side opposed to the first display substrate side.
3. The method of claim 2, further including forming the pixels on the first display substrate side or on one or more layers on the first display substrate side and forming the row electrodes on the second display substrate side or on one or more layers on the second display substrate side.
4. The method of claim 3, further including forming the transparent dielectric layer over or on the row electrodes.
5. The method of claim 4, further including forming the column electrodes on or over the transparent dielectric layer.
6. The method of claim 4, further including providing a protective layer on or over the column electrodes.
7. The method of claim 2, further including forming the pixels on the first display substrate side or on one or more layers on the first display substrate side and forming the row electrodes on or over the pixels.
8. The method of claim 7, further including forming the transparent dielectric layer over or on the row electrodes.
9. The method of claim 8, further including forming the column electrodes on or over the transparent dielectric layer.
10. The method of claim 9, further including providing a protective layer on or over the column electrodes.
11. The method of claim 1, wherein the ground lines are electrically connected.
12. The method of claim 1, further including forming the row electrodes on the row side of the transparent dielectric layer.
13. The method of claim 1, further including forming the column electrodes on the column side of the transparent dielectric layer.
14. The method of claim 1, further including laminating the transparent dielectric layer to the display substrate.
15. The method of claim 14, further including providing a protective layer with the transparent dielectric layer between the protective layer and the display substrate.
16. The method of claim 1, further including electrically connecting the ground lines on the row side together.
17. The method of claim 1, further including electrically connecting the ground lines on the column side together.
18. The method of claim 1, further including electrically connecting the ground lines on the row side with the ground lines on the column side.
19. The method of claim 1, wherein the transparent dielectric layer is a display cover or display substrate.
20. The method of claim 1, wherein the ground lines include one more electrically connected micro-wires.
21. The method of claim 1, wherein alternating rows or columns of pixels are offset and the ground lines form a crenellated pattern.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for determining the antibiotic-resistance status of a microorganism, comprising:
(a) contacting the microorganism with a resistance-determining affinity ligand under conditions whereby a microorganismresistance-determining affinity ligand complex can be formed;
(b) separating microorganismresistance-determining affinity ligand complex formed in (a) from unbound resistance-determining affinity ligand;
(c) interrogating and determining the amount of resistance-determining affinity ligand bound to the microorganism in the microorganismresistance-determining affinity ligand complex; and
(d) comparing the amount of resistance-determining affinity ligand bound to the microorganism in the microorganismresistance-determining affinity ligand complex to the amount of resistance-determining affinity ligand bound by a known antibiotic-sensitive or antibiotic-resistant strain of the same microorganism or a population of known antibiotic-sensitive or antibiotic-resistant strains;
wherein one or more of steps (a), (b), (c), andor (d) are carried out in a sealed container; and
wherein if the microorganism in the microorganismresistance-determining affinity ligand complex binds a different amount of resistance-determining affinity ligand than is bound by the antibiotic-sensitive microorganism or the microorganism in the microorganismresistance-determining affinity ligand complex binds the same amount of resistance-determining affinity ligand as is bound by the antibiotic-resistant microorganism, the microorganism is identified as antibiotic-resistant.
2. (canceled)
3. The method of claim 1, wherein the resistance-determining affinity ligand is selected from the group consisting of antibiotics, monoclonal and polyclonal antibodies and fragments thereof, nucleic acid probes, enzyme substrates, aptamers, peptide mimetics, phage-derived binding proteins, lectins, host defense peptides, bacterocins, bacteriophages, dyes selective for nucleic acids, lipids, carbohydrates, polysaccharides, proteins, and combinations thereof.
4. The method of claim 1, wherein the resistance-determining affinity ligand is an antibiotic.
5. The method of claim 1, wherein the resistance-determining affinity ligand is a \u03b2-lactam antibiotic or a glycopeptide antibiotic.
6. The method of claim 1, wherein the resistance-determining affinity ligand comprises a detectable label and wherein said detectable label is a fluorescent, luminescent, phosphorescent, radioactive, Raman-active, mass spectrometry-reactive andor colorimetric compound label.
7. (canceled)
8. (canceled)
9. The method of claim 1, wherein the sample is from a positive blood culture.
10. The method of claim 1, wherein the sample comprising the microorganism is treated to selectively lyse any non-microbial cells that may be present in the sample prior to the separation step (b).
11. The method of claim 1, wherein said microorganism is layered on a density cushion in a container and the separation step (b) is by centrifugation of the container.
12. (canceled)
13. (canceled)
14. (canceled)
15. (canceled)
16. The method of claim 1, wherein said interrogation step is selected from the group consisting of fluorescence spectroscopy, diffuse reflectance spectroscopy, adsorption and transmission spectroscopy, infrared spectroscopy, terahertz spectroscopy, Raman spectroscopy, surface enhanced Raman spectroscopy, spacially-offset Raman spectroscopy, resonance Raman spectroscopy, mass spectrometry and any combination thereof.
17. The method of claim 1, wherein said spectroscopy is front face fluorescence spectroscopy.
18. (canceled)
19. (canceled)
20. (canceled)
21. The method of claim 1, wherein the amount of resistance-determining affinity ligand bound is determined on a per cell basis by comparing the amount bound to an intrinsic property of the microorganism.
22. (canceled)
23. The method of claim 11, wherein step (c) comprises a step of recovering the microorganism to produce a recovered microorganism.
24. The method of claim 1, wherein step (d) comprises comparing the amount of resistance-determining affinity ligand bound to the amount of resistance-determining affinity ligand bound by both an antibiotic-sensitive and antibiotic-resistant strain of the same microorganism.
25. The method of claim 1, wherein the amount bound by a known antibiotic-sensitive or antibiotic-resistant strain of the same microorganism has been previously determined.
26. (canceled)
27. (canceled)
28. A method for determining the antibiotic-resistance status of a microorganism, comprising:
(a) obtaining a test sample known to contain or that may contain microorganisms;
(b) contacting the microorganism in the test sample with a resistance-determining affinity ligand under conditions whereby a microorganismresistance-determining affinity ligand complex can be formed;
(c) optionally adding one or more fluorescent dyes that measure cell metabolism or membrane integrity;
(d) optionally selectively lysing any non-microbial cells that may be present in the sample to produce a lysed sample;
(e) separating the microorganisms from other components of said test sample, or said lysed sample, to form a pellet of microorganisms;
(f) spectroscopically interrogating the pellet to produce measurements of the microorganism;
(g) determining the antibiotic-resistance status of the microorganisms in the test sample by comparison of the measurements with measurements taken, or predicted, for antibiotic-resistant andor antibiotic-susceptible microorganisms of the same species; and
wherein one or more of steps (a), (b), (c), andor (d) are carried out in a sealed container.
29. The method of claim 28, wherein one or more fluorescent dyes are added in step (c).
30. The method of claim 28, wherein said antibiotic-resistance determination in step (g) is determined to be induced resistance.
31. (canceled)
32. The method of claim 28, wherein said spectroscopy is selected from the group consisting of fluorescence spectroscopy, diffuse reflectance spectroscopy, adsorption and transmission spectroscopy, infrared spectroscopy, terahertz spectroscopy, Raman spectroscopy, surface enhanced Raman spectroscopy, spacially-offset Raman spectroscopy, resonance Raman spectroscopy, and any combination thereof.
33. The method of claim 28, wherein said microorganism is layered on a density cushion in a container and the separation step (e) is by centrifugation of the container.
34. A system for determining the antibiotic-resistance status of a microorganism, said system comprising:
(a) a container comprising a microorganism or a sample containing the microorganism and a resistance-determining affinity ligand;
(b) a density cushion; and
(c) a spectrometer to provide a measurement;
wherein said measurement determines the antibiotic-resistance status of the microorganism that has been concentrated in said container by an in situ separation within said system.
35. (canceled)

What is claimed:

1. A method of manufacturing a semiconductor memory device, including (i) a memory cell comprised of a first MISFET and a (ii) second MISFET for a peripheral circuit, comprising the steps of:
(a) providing a semiconductor substrate, having a memory cell forming region and a peripheral circuit forming region, (i) with a first gate insulating film of said first MISFET formed on said memory cell forming region, a floating gate electrode of said first MISFET formed on said first gate insulating film, a second gate insulating film of said first MISFET formed on said floating gate electrode, and a control gate electrode of said first MISFET formed on said second gate insulating film, and (ii) with a third gate insulating film, associated with said second MISFET, formed on said peripheral circuit forming region, and a gate electrode of said second MISFET formed on said third gate insulating film;
(b) introducing an impurity into said memory cell forming region for forming a first semiconductor region in said substrate;
(c) introducing an impurity into said memory cell forming region for forming a second semiconductor region in said substrate,
wherein a dose introduced in said step (b) is higher than the dose in said step (c) such that a part of said first semiconductor region which is positioned under said floating gate electrode has an impurity concentration higher than that of a part of said second semiconductor region which is positioned under said floating gate electrode, and
wherein a channel forming region of said first MISFET is formed between said first semiconductor region and said second semiconductor region;
(d) introducing an impurity into said peripheral circuit forming region for forming a third semiconductor region in said substrate,
wherein a dose introduced in said step (b) is higher than the dose in said step (d);
(e) after said steps (b), (c), and (d), forming first side wall spacers on both of opposing side surfaces of said control gate electrode and said floating gate electrode of said first MISFET, and forming second side wall spacers on both of opposing side surfaces of said gate electrode of said second MISFET; and
(f) after said step (e), introducing an impurity into said peripheral circuit forming region for forming a fourth semiconductor region in said substrate,
wherein said first, second, third, and fourth semiconductor regions have a same conductivity type, respectively,
wherein said third and fourth semiconductor regions together serve as a drain region of said second MISFET, and
wherein carriers stored in said floating gate electrode are transferred between said floating gate electrode and said first semiconductor region by tunneling through said first gate insulating film.
2. A method of manufacturing a semiconductor memory device according to claim 1,
wherein in a writing operation hot carriers generated in said substrate are injected in said floating gate electrode, and
wherein in an erase operation said carriers stored in said floating gate electrode are transferred between said floating gate electrode and said first semiconductor region by tunneling through said first gate insulating film.
3. A method of manufacturing a semiconductor memory device according to claim 2, wherein said impurity in said step (b) is arsenic, and said impurity in said step (c) is arsenic.
4. A method of manufacturing a semiconductor memory device according to claim 1, wherein said impurity in said step (b) is arsenic, and said impurity in said step (c) is arsenic.
5. A method of manufacturing a semiconductor device according to claim 1,
wherein said first, second, third and fourth regions have the same conductivity type, respectively, taken from either an n-type or p-type conductivity.
6. A method of manufacturing a semiconductor memory device, including (i) a memory cell comprised of a first MISFET and (ii) a second MISFET for a peripheral circuit, comprising steps of:
(a) providing a semiconductor substrate, having a memory cell forming region and a peripheral circuit forming region, (i) with a first gate insulating film of said first MISFET formed on said memory cell forming region, a floating gate electrode of said first MISFET formed on said first gate insulating film, a second gate insulating film of said first MISFET formed on said floating gate electrode, and a control gate electrode of said first MISFET formed on said second gate insulating film, and (ii) with a third gate insulating film, associated with said second MISFET, formed on said peripheral circuit forming region, and a gate electrode of said second MISFET formed on said third gate insulating film;
(b) introducing an impurity into said memory cell forming region for forming a first semiconductor region in said substrate;
(c) introducing an impurity into said memory cell forming region for forming a second semiconductor region in said substrate,
wherein a dose introduced in said step (b) is higher than the dose in said step (c) such that a part of said first semiconductor region which is positioned under said floating gate electrode has an impurity concentration higher than that of a part of said second semiconductor region which is positioned under said floating gate electrode,
wherein a junction depth of said first semiconductor region is greater than a junction depth of said second semiconductor region such that an overlap area, in a plane view in parallel with a main surface of said substrate, between said floating gate electrode and said first semiconductor region is greater than an overlap area, in a plane view in parallel with said main surface, between said floating gate electrode and said second semiconductor region, and
wherein a channel forming region of said first MISFET is formed between said first semiconductor region and said second semiconductor region;
(d) introducing an impurity into said peripheral circuit forming region for forming a third semiconductor region in said substrate,
wherein a dose introduced in said step (b) is higher than the dose in said step (d);
(e) after said steps (b), (c), and (d), forming first side wall spacers on both of opposing side surfaces of said control gate electrode and said floating gate electrode of said first MISFET, and forming second side wall spacers on both of opposing side surfaces of said gate electrode of said second MISFET; and
(f) after said step (e), introducing an impurity into said peripheral circuit forming region for forming a fourth semiconductor region in said substrate,
wherein said first, second, third, and fourth semiconductor regions have a same conductivity type, respectively,
wherein said third and fourth semiconductor regions together serve as a drain region of said second MISFET, and
wherein carriers stored in said floating gate electrode are transferred between said floating gate electrode and said first semiconductor region by tunneling through said first gate insulating film.
7. A method of manufacturing a semiconductor memory device according to claim 6, wherein said impurity in said step (b) is arsenic, and said impurity in said step (c) is arsenic.
8. A method of manufacturing a semiconductor memory device according to claim 7,
wherein in a writing operation hot carriers generated in said substrate are injected in said floating gate electrode, and
wherein in an erase operation said carriers stored in said floating gate electrode are transferred between said floating gate electrode and said first semiconductor region by tunneling through said first gate insulating film.
9. A method of manufacturing a semiconductor memory device according to claim 6,
wherein in a writing operation hot carriers generated in said substrate are injected in said floating gate electrode, and
wherein in an erase operation said carriers stored in said floating gate electrode are transferred between said floating gate electrode and said first semiconductor region by tunneling through said first gate insulating film.
10. A method of manufacturing a semiconductor memory device according to claim 6,
wherein said first, second, third and fourth regions have the same conductivity type, respectively, taken from either an n-type or p-type conductivity.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A leadframe comprising:
a planar pad operable for mounting a workpiece, which has a predetermined range of operating temperature; and
a plurality of non-coplanar members operable as mechanical stabilizers configured to secure inserted objects, said members adjoining said pad.
2. The leadframe according to claim 1 wherein said members have shapes resembling elongated protrusions, dimples, or thorns, project from said leadframe at an angle and abut said pad.
3. The leadframe according to claim 1 wherein said non-coplanarity is provided by a bend in said members near their attachment to said leadframe pad.
4. The leadframe according to claim 2 wherein said angle is selected between an acute angle and a right angle.
5. An apparatus comprising:
a leadframe comprising a planar pad of a certain size, said leadframe pad operable for mounting a heat-generating workpiece, and a plurality of non-coplanar members operable as mechanical stabilizers configured to secure inserted objects, said members adjoining said pad;
a heat spreader having a planar pad of a size matching said leadframe pad size, and contours suitable for insertion of said leadframe members; and
said leadframe members inserted into said spreader contours so that said spreader pad touches said leadframe pad across said pad size.
6. The apparatus according to claim 5 wherein said heat spreader has contours, which match said leadframe members in number, location, and size so that said members fit into said contours to stabilize and secure said heat spreader relative to said leadframe during the encapsulation process.
7. The apparatus according to claim 5 wherein said spreader contours are shaped as indentations including grooves or holes.
8. The apparatus according to claim 5 further comprising an attachment of said spreader pad to said leadframe pad by a thermally conductive adhesive.
9. The apparatus according to claim 5 wherein said heat spreader is made of a material and has a size and thickness to operate as a heat sink during the first operational phase of said heat-generating workpiece.
10. A semiconductor device comprising:
a leadframe having first and second surfaces, a planar pad of a certain size, and a plurality of non-coplanar members adjoining said pad;
a heat spreader having first and second surfaces and a planar pad of a size matching said leadframe pad size, said spreader further having contours into which said leadframe members are inserted so that said first spreader pad surface touches said second leadframe pad surface across said pad size;
a semiconductor chip mounted on said first leadframe pad surface; and
encapsulation material covering said chip and uncovering said second spreader surface.
11. The device according to claim 10 wherein said second spreader surface is operable for attachment to external parts.
12. The device according to claim 10 wherein said heat spreader is made of a material and has a thickness to operate as a heat sink during the first operational phase of said semiconductor chip.
13. A method for fabricating a semiconductor device comprising the steps of:
providing a leadframe made from a planar metal sheet, said leadframe including a pad of a certain size, having first and second surfaces and a plurality of non-coplanar members operable as mechanical stabilizers configured to secure inserted objects, said members adjoining said pad;
providing a heat spreader having first and second surfaces, a planar pad of a size matching said leadframe pad size, and contours suitable for insertion of said leadframe members;
inserting said leadframe members into said spreader contours so that said first spreader pad surface touches said second leadframe pad surface across said pad size;
providing a semiconductor chip and mounting said chip on said first leadframe pad surface; and
encapsulating said mounted chip, while leaving said second spreader surface uncovered.
14. The method according to claim 13 further comprising the step of:
attaching said first spreader pad surface to said second leadframe pad surface using a thermally conductive adhesive.
15. The method according to claim 13 wherein said step of encapsulating comprises the steps of:
placing said spreader together with said inserted leadframe and the mounted chip on the bottom of the mold cavity so that said second spreader surface rests on the mold bottom;
closing said mold and transferring molding compound into said cavity, whereby movements of said spreader relative to said leadframe are inhibited by said leadframe members inserted into said spreader; and
polymerizing and hardening said molding compound.