Author: claimsbot

1. A receiving apparatus comprising:
A receiver which, in operation, receives a signal including downlink control information mapped to a first search space or a second search space, the first search space including one or a plurality of first PDCCH candidates for each of a plurality of aggregation levels, the second search space including one or a plurality of second PDCCH candidates for each of the plurality of aggregation levels and further including at least one other second PDCCH candidate for an aggregation level higher than any one of the plurality of aggregation levels, each of the first and the second PDCCH candidate being composed of a control channel element (CCE) or a plurality of aggregated CCEs of its corresponding aggregation level; and
a monitor which, in operation, monitors the one or the plurality of first PDCCH candidates included in the first search space or the one or the plurality of second PDCCH candidates and the at least one other second PDCCH candidate included in the second search space and to acquire downlink control information for the receiving apparatus.
2. The receiving apparatus according to claim 1, wherein
the one or the plurality of first PDCCH candidates included in the first search space are allocated for localized transmission; and
the one or the plurality of second PDCCH candidates and the at least one other second PDCCH candidate included in the second search space are allocated for distributed transmission.
3. The receiving apparatus according to claim 1, wherein for each of the plurality of aggregation levels, a frequency position of the one or the plurality of first PDCCH candidates included in the first search space does not overlap with a frequency position of any one of the one or the plurality of second PDCCH candidates and the at least one other second PDCCH candidate included in the second search space.
4. The receiving apparatus according to claim 1, wherein the plurality of first PDCCH candidates included in the first search space and the plurality of second PDCCH candidates and the at least one other second PDCCH candidate included in the second search space are allocated for distributed transmission.
5. The receiving apparatus according to claim 1, wherein at least one of the first search space and the second search space defines a smaller number of PDCCH candidates as an aggregation level gets higher.
6. The receiving apparatus according to claim 1, wherein both of the first search space and the second search space are UE-specific search spaces.
7. A receiving method comprising:
receiving a signal including downlink control information mapped to a first search space or a second search space, the first search space including one or a plurality of first PDCCH candidates for each of a plurality of aggregation levels, the second search space including one or a plurality of second PDCCH candidates for each of the plurality of aggregation levels and further including at least one other second PDCCH candidate for an aggregation level higher than any one of the plurality of aggregation levels, each of the first and the second PDCCH candidate being composed of a control channel element (CCE) or a plurality of aggregated CCEs of its corresponding aggregation level; and
monitoring the one or the plurality of first PDCCH candidates included in the first search space or the one or the plurality of second PDCCH candidates and the at least one other second PDCCH candidate included in the second search space and acquiring downlink control information for a receiving apparatus.
8. The receiving method according to claim 7, wherein
the one or the plurality of first PDCCH candidates included in the first search space are allocated for localized transmission; and
the one or the plurality of second PDCCH candidates and the at least one other second PDCCH candidate included in the second search space are allocated for distributed transmission.
9. The receiving method according to claim 7, wherein
for each of the plurality of aggregation levels, a frequency position of the one or the plurality of first PDCCH candidates included in the first search space does not overlap with a frequency position of any one of the one or the plurality of second PDCCH candidates and the at least one other second PDCCH candidate included in the second search space.
10. The receiving method according to claim 7, wherein the plurality of first PDCCH candidates included in the first search space and the plurality of second PDCCH candidates and the at least one other second PDCCH candidate included in the second search space are allocated for distributed transmission.
11. The receiving method according to claim 7, wherein at least one of the first search space and the second search space defines a smaller number of PDCCH candidates an aggregation level gets higher.
12. The receiving method according to claim 7, wherein both of the first search space and the second search space are UE-specific search spaces.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of making a plurality of conductive memory devices comprising:
forming a bottom electrode layer;
forming a multi-resistive state element layer;
forming a top electrode layer;
forming a hard mask layer;
patterning the hard mask layer and the top electrode layer such that the patterned top electrode and hard mask have a first cross sectional area;
forming a dielectric material layer;
etching the dielectric material to create a sidewall spacer; and
etching the multi-resistive state element layer and the bottom electrode layer using the hard mask such that the etched bottom electrode and multi-resistive state element have a second cross sectional area that is larger than the first cross sectional area.
2. A method of making a plurality of conductive memory devices, each conductive memory device operable to be reversibly placed in multiple resistive states, the method comprising:
sputtering a bottom electrode layer;
sputtering a multi-resistive state element layer;
sputtering a top electrode layer;
depositing a hard mask layer;
photo lithographically patterning the hard mask layer and the top electrode layer such that the patterned top electrode and hard mask have a first cross sectional area;
depositing a dielectric material;
etching the dielectric anisotropically to create a sidewall spacer at the edges of the top electrode; and
etching the multi-resistive state element layer and the bottom electrode layer using the hard mask such that the etched bottom electrode and multi-resistive state element have a second cross sectional area that is larger than the first cross sectional area.
3. The method of making a plurality of conductive memory devices of claim 2 wherein the multi-resistive state element layer and the top electrode layer have an interface that is modified.
4. The method of making a plurality of conductive memory devices of claim 3 wherein modification of the interface is performed by either ion implantation, in situ argon plasma treatment, in situ oxygen plasma treatment, in situ annealing in argon or in situ annealing in oxygen.
5. The method of making a plurality of conductive memory devices of claim 2 further comprising:
wet etching the multi-resistive state element layer
wherein the wet etching is performed after the etching of the multi-resistive state element layer, the etching of the multi-resistive state element layer forming multi-resistive state element sides; and
wherein the wet etching of the multi-resistive state element removes a thickness of 50-150 \u212b, thereby forming an undercut from the multi-resistive state element sides.
6. The method of making a plurality of conductive memory devices of claim 2 wherein at least one etching is performed via high temperature reactive ion etching.

1. A method for operating a compiler, the method comprising:
utilizing a computer to perform:
scanning program code to identify a first algebraic expression specified by the program code, wherein the first algebraic expression includes two or more mutually-compatible binary operations and three or more input operands, wherein the three or more input operands include two or more scalar operands and one or more array operands; and
operating on the first algebraic expression to obtain a final algebraic expression by:
(a) computing a rank vector for each of the three or more input operands, wherein the rank vector for any given one of the three or more input operands includes a first component that is based on an invariance rank of the input operand and a second component that is based on a dimension of the input operand, and
(b) performing transformations on selected subexpressions of the first algebraic expression, wherein the transformations include one or more commute transformations and one or more associate transformations, wherein each of the commute transformations exchanges input operands of a corresponding one of the two or more binary operations to order the input operands according to an ordering of possible states of the rank vector, wherein the ordering of possible states gives precedence to the first component over the second component;

wherein the final algebraic expression specifies an order of execution for the two or more binary operations such that the three or more input operands are combined in an order that agrees with the ordering of possible states of the rank vector.
2. The method of claim 1, wherein the two or more mutually-compatible binary operations are instances of a single operator.
3. The method of claim 1, wherein each of the two or more binary operations includes a first input and a second input and an output, wherein each of the first input and the second input is either one of the three or more input operands or the output of another one of the two or more binary operations, wherein said operating on the first algebraic expression includes:
after performing the commute transformation on a first one of the two or more binary operations, determining if the first binary operation satisfies a reassociate condition, wherein the reassociate condition is a logical combination of at least two subconditions, wherein the at least two subconditions includes a first subcondition that the first input of the first binary operation is the output of a second one of the two or more binary operations, and a second subcondition that the output of the second binary operation is not used an as input other than as the first input of the first binary operation; and
performing an associate transformation on the first and second binary operations in response to determining that the first binary operation satisfies the reassociate condition.
4. The method of claim 3, further comprising:
performing type propagation on the first and second binary operations after said performance of the associate transformation on the first and second binary operations.
5. The method of claim 1, wherein the rank vector for any given one of the three or more input operands also includes a third component that is based on a data size associated with a generic element of the given input operand, wherein the ordering of possible states of the rank vector gives precedence to the second component over the third component.
6. The method of claim 1, further comprising:
generating modified program code that includes the final algebraic expression;
generating executable code from the modified program code, wherein the executable code includes a portion that corresponds to the final algebraic expression, where said portion of the executable code respects the order of execution specified by the final algebraic expression.
7. A non-transitory computer-readable memory medium, wherein the memory medium stores program instructions, wherein the program instructions, when executed by a computer system, cause the computer system to:
scan program code to identify a first algebraic expression specified by the program code, wherein the first algebraic expression includes two or more mutually-compatible binary operations and three or more input operands, wherein the three or more input operands include two or more scalar operands and one or more array operands; and
operate on the first algebraic expression to obtain a final algebraic expression by:
(a) computing a rank vector for each of the three or more input operands, wherein the rank vector for any given one of the three or more input operands includes a first component that is based on an invariance rank of the input operand and a second component that is based on a dimension of the input operand, and
(b) performing transformations on selected subexpressions of the first algebraic expression, wherein the transformations include one or more commute transformations and one or more associate transformations, wherein each of the commute transformations exchanges input operands of a corresponding one of the two or more binary operations to order the input operands according to an ordering of possible states of the rank vector,
wherein the ordering of possible states gives precedence to the first component over the second component;
wherein the final algebraic expression specifies an order of execution for the two or more binary operations such that the three or more input operands are combined in an order that agrees with the ordering of possible states of the rank vector.
8. The memory medium of claim 7, wherein the two or more mutually-compatible binary operations are instances of a single operator.
9. The memory medium of claim 7, wherein the rank vector for any given one of the three or more input operands also includes a third component that is based on a data size associated with a generic element of the given input operand, wherein the ordering of possible states of the rank vector gives precedence to the second component over the third component.
10. The memory medium of claim 7, wherein the first algebraic expression specifies an initial order of execution of the two or more binary operations, wherein said operating on the first algebraic expression includes operating on the two or more binary operations in a recursive fashion starting with a particular one of the two or more binary operations that is last according to the initial order of execution.
11. The memory medium of claim 7, wherein the program code is a program representation that is intermediate between a user-specified program and machine executable code.
12. The memory medium of claim 7, wherein the program instructions, when executed by the computer system, further cause the computer system to:
generate modified program code that includes the final algebraic expression; and
display the modified program code via a display device.
13. A computer system comprising:
a processor; and
memory storing program instructions, wherein the program instructions, when executed by the processor, cause the processor to:
scan program code to identify a first algebraic expression specified by the program code, wherein the first algebraic expression includes two or more mutually-compatible binary operations and three or more input operands, wherein the three or more input operands include two or more scalar operands and one or more array operands; and
operate on the first algebraic expression to obtain a final algebraic expression by:
(a) computing a rank vector for each of the three or more input operands, wherein the rank vector for any given one of the three or more input operands includes a first component that is based on an invariance rank of the input operand and a second component that is based on a dimension of the input operand, and
(b) performing transformations on selected subexpressions of the first algebraic expression, wherein the transformations include one or more commute transformations and one or more associate transformations, wherein each of the commute transformations exchanges input operands of a corresponding one of the two or more binary operations to order the input operands according to an ordering of possible states of the rank vector, wherein the ordering of possible states gives precedence to the first component over the second component;
wherein the final algebraic expression specifies an order of execution for the two or more binary operations such that the three or more input operands are combined in an order that agrees with the ordering of possible states of the rank vector.
14. The computer system of claim 13, wherein the two or more mutually-compatible binary operations are instances of a single operator.
15. The computer system of claim 13, wherein the rank vector for any given one of the three or more input operands also includes a third component that is based on a data size associated with a generic element of the given input operand, wherein the ordering of possible states of the rank vector gives precedence to the second component over the third component.
16. The computer system of claim 13, wherein the first algebraic expression specifies an initial order of execution of the two or more binary operations, wherein said operating on the first algebraic expression includes operating on the two or more binary operations in a recursive fashion starting with a particular one of the two or more binary operations that is last according to the initial order of execution.
17. The computer system of claim 13, wherein the program code is a program representation that is intermediate between a user-specified program and machine executable code.
18. The computer system of claim 13, wherein the program instructions, when executed by the processor, further cause the processor to:
generate modified program code that includes the final algebraic expression; and
display the modified program code via a display device.
19. The computer system of claim 13, wherein the first component increases as depth of loop invariance of the input operand increases, wherein the second component decreases as dimension of the input operand increases.
20. The computer system of claim 19, wherein the rank vector also includes a third component that is based on data size associated with a generic element of the input operand, wherein the ordering of possible states of the rank vector gives precedence to the second component over the third component.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of retrofitting an injection molding machine to multishot operation, where the injection molding machine has a first stationary platen holding a stationary mold portion in communication with an injection cylinder and a second movable platen holding a movable mold portion joining with the stationary mold portion with movement of the movable platen, the injection cylinder, stationary platen and movable platen controlled by an injection molding controller, the method comprising the steps of:
(a) attaching a mounting directly to one of the movable and stationary platens; and
(b) adjustably attaching a second injection cylinder to the mounting;
(c) connecting interface electronics providing an interface between the second injection cylinder and the injection molding controller to the injection molding controller to coordinate the operation of the second injection molding cylinder with the movement of the stationary and movable platens;
wherein the second injection cylinder is attached to the movable platen to engage with the movable mold portion.
2. The method of claim 1 wherein the second injection cylinder includes at least one positioning actuator for moving the second injection cylinder along its axis and wherein the interface electronics allows the injection molding controller to control the positioning actuator in coordination with movement of the stationary and movable platens to engage by axial movement with the movable mold portion when the movable mold portion is joined with the stationary mold portion and to disengage by axial movement with the movable mold portion prior to separation of the movable mold portion and the stationary mold portion.
3. The method of claim 1 wherein the second injection molding cylinder is attached to the top of the movable platen.
4. The method of claim 1 wherein the second injection molding cylinder is attached a front surface of the movable platen holding the movable mold portion.
5. The method of claim 1 wherein the second injection molding cylinder is attached to the movable mold portion.