Author: claimsbot

1. A method of removing particles from a chamber of a plasma processing apparatus, wherein the chamber is connected to a gas exhaust port and a plasma of a processing gas is generated in the chamber to plasma process a substrate to be processed, the method comprising:
positively charging the particles at a first region of the chamber by applying a first negative voltage to a first charging electrode installed in a first portion of an inner wall of the chamber;
drift-transferring the positively charged particles towards a second region of the chamber by applying a second negative voltage to a second charging electrode installed in a second portion of the inner wall of the chamber;
guiding the drift-transferred positively charged particles towards the gas exhaust port along the inner wall of the chamber; and
discharging the guided positively charged particles from the chamber through the gas exhaust port,
wherein said applying the first negative voltage attracts positive ions toward the first charging electrode and the particles are positively charged by colliding with the positive ions,
wherein the second portion is closer to the gas exhaust port than the first portion and wherein the second negative voltage has an absolute value greater than the absolute value of the first negative voltage.
2. The method of claim 1, wherein each of the first and the second charging electrode is embedded in an insulator, and
wherein said applying the first negative voltage attracts the positive ions and the particles positively charged by colliding with the positive ions toward the first portion of the inner wall of the chamber.
3. The method of claim 1, wherein the gas exhaust port is disposed around a lower part of the inner wall of the chamber, and the positively charged particles are guided towards the gas exhaust port while moving down along the inner wall of the chamber.
4. The method of claim 3, wherein a baffle plate for providing a gas exhaust path of a low conductance is installed in the vicinity of an entrance side of the gas exhaust port, and a negative potential is applied to the baffle plate.
5. A method for performing a plasma process on a substrate to be processed by generating a plasma of a processing gas in a vacuum evacuable chamber connected to a gas exhaust port, the method comprising:
depressurizing the chamber accommodating the substrate therein;
removing particles generated in the chamber by applying a negative voltage to a charging electrode installed in an inner wall of the chamber;
processing the substrate by generating the plasma in the chamber by way of introducing the processing gas into the chamber and supplying a high frequency power into the chamber;
stopping, after said processing the substrate, said introducing the processing gas and said supplying the high frequency power;
grounding the charging electrode; and
transferring the substrate out of the chamber,
wherein said removing the particles includes:
positively charging particles generated within the chamber by attracting positive ions to an ion sheath region, the ion sheath region being formed in a region other than the vicinity of the substrate when the plasma is generated;
guiding positively charged particles towards the gas exhaust port via the ion sheath region; and
discharging the positively charged particles from the chamber through the gas exhaust port,
wherein the charging electrode is electrically divided into a plurality of regions depending on a distance from the gas exhaust port, and independent negative potentials are applied to the respective regions, and
wherein said applying the negative voltage attracts the positive ions toward the charging electrode and the particles are positively charged by colliding with the positive ions,
wherein the plurality of regions comprise a first region with a first negative voltage and a second region with a second negative voltage, wherein the second region is closer to the gas exhaust port than the first region, and wherein the second negative voltage has an absolute value greater than the absolute value of the first negative voltage.
6. A method for performing a plasma process on a substrate to be processed by generating a plasma of a processing gas in a vacuum evacuable chamber connected to a gas exhaust port, the method comprising:
depressurizing the chamber accommodating the substrate therein;
removing particles generated in the chamber;
processing the substrate by generating the plasma in the chamber by way of introducing the processing gas into the chamber and supplying a high frequency power into the chamber;
stopping, after said processing the substrate, said introducing the processing gas and said supplying the high frequency power;
grounding the charging electrode; and
transferring the substrate out of the chamber,
wherein said removing the particles includes:
positively charging the particles at a first region of the chamber by applying a first negative voltage to a first charging electrode installed in a first portion of an inner wall of the chamber;
drift-transferring the positively charged particles towards a second region of the chamber by applying a second negative voltage to a second charging electrode installed in a second portion of the inner wall of the chamber;
guiding the drift-transferred positively charged particles towards the gas exhaust port along the inner wall of the chamber; and
discharging the guided positively charged particles from the chamber through the gas exhaust port,
wherein an absolute value of the second negative voltage is greater than that of the first negative voltage, and
wherein the first portion is an inner ceiling wall of the chamber and the second portion is an inner sidewall of the chamber, and wherein the second portion is closer to the gas exhaust port than the first portion.
7. A method of removing particles from a chamber of a plasma processing apparatus, wherein the chamber is connected to a gas exhaust port and a plasma of a processing gas is generated in the chamber to plasma process a substrate to be processed, the method comprising:
positively charging the particles at a first region of the chamber by applying a first negative voltage to a first charging electrode installed in a first portion of an inner wall of the chamber;
drift-transferring the positively charged particles towards a second region of the chamber by applying a second negative voltage to a second charging electrode installed in a second portion of the inner wall of the chamber;
guiding the drift-transferred positively charged particles towards the gas exhaust port along the inner wall of the chamber; and
discharging the guided positively charged particles from the chamber through the gas exhaust port,
wherein an absolute value of the second negative voltage is greater than that of the first negative voltage, and
wherein the first portion is an inner ceiling wall of the chamber and the second portion is an inner sidewall of the chamber,
wherein the positively charged particles are generated by colliding particles with positive ions attracted to the first charging electrode, and wherein the second portion is closer to the gas exhaust port than the first portion.
8. The method of claim 1, wherein said positively charging the particles, said drift-transferring the positively charged particles, said guiding the positively charged particles and said discharging the positively charged particles are performed during plasma processing.
9. The method of claim 5, wherein said positively charging the particles, said guiding the positively charged particles and said discharging the positively charged particles are performed during plasma processing.
10. The method of claim 6, wherein said positively charging the particles, said drift-transferring the positively charged particles, said guiding the positively charged particles and said discharging the positively charged particles are performed during plasma processing.
11. The method of claim 7, wherein said positively charging the particles, said drift-transferring the positively charged particles, said guiding the positively charged particles and said discharging the positively charged particles are performed during plasma processing.
12. The method of claim 1, wherein the first charging electrode is attached to a substantial entirety of an inner ceiling wall of the chamber.
13. The method of claim 6, wherein the first charging electrode is attached to a substantial entirety of the inner ceiling wall of the chamber.
14. The method of claim 7, wherein the first charging electrode is attached to a substantial entirety of the inner ceiling wall of the chamber.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An emission current adjusting method for an optical disk device, which is irradiated with a laser beam to perform recording and reproduction of data, the laser beam is driven by emission currents including a current for generating a peak level emission intensity; a current for generating a minimum bottom level emission intensity; and a current for generating an erase level emission intensity between the peak and bottom levels, the emission current adjusting method comprising the steps of:
obtaining an ideal value of an erase current after recording is started;
measuring an erase current after recording is started; and
determining an emission current after recording is started based on,
wherein a bottom current is defined as the current which generates the minimum bottom level emission intensity, an erase current is defined by subtracting the bottom current from the current which generates the erase level emission intensity, and a peak current is defined by subtracting the erase current from the current which generates the peak level emission intensity.
2. The emission current adjusting method as claimed in claim 1, wherein a bottom current after recording is started is determined based on the measured value and the ideal value of the erase current after recording is started.
3. The emission current adjusting method as claimed in claim 1, wherein a bottom current adjustment value after recording is started is determined based on a measured value and an ideal value of the erase current after recording is started.
4. The emission current adjusting method as claimed in claim 3, wherein a value obtained by adding the adjustment value to a bottom current at starting of recording is set as a bottom current after recording is started, and the erase current ideal value is set as an erase current after recording is started.
5. The emission current adjusting method as claimed in claim 4, wherein the ideal value of the erase current is obtained by multiplying a ratio of an erase current to a peak current at starting of recording by a peak current after recording is started.
6. The emission current adjusting method as claimed in claim 4, wherein the erase current ideal value is obtained by multiplying a ratio of erase power to peak power calculated from target peak power and target erase power set before starting recording by a peak current after starting recording.
7. The emission current adjusting method as claimed in claim 1, wherein the ideal value of the erase current is obtained by multiplying a ratio of an erase current to a peak current at starting of recording by a peak current after recording is started.
8. The emission current adjusting method as claimed in claim 1, wherein the erase current ideal value is obtained by multiplying a ratio of erase power to peak power calculated from target peak power and target erase power set before starting recording by a peak current after starting recording.
9. An optical disk device, comprising:
a sample hold circuit which generates an emission intensity waveform by emission currents including a current for generating a peak level emission intensity, a current for generating a minimum bottom level emission intensity; and a current for generating an erase level emission intensity between the peak and bottom levels, and detects at least an erase level by sampling the emission intensity waveform;
a power control part which calculates an adjustment value of a bottom current after recording is started from a measured value and an ideal value of the erase current after recording is started, and calculates a set value of the bottom current on the basis of the adjustment value; and
a laser driver for generating an emission current on the basis of the set value of the bottom current,
wherein a bottom current is defined as the current which generates the minimum bottom level emission intensity, an erase current is defined by subtracting the bottom current from the current which generates the erase level emission intensity, and a peak current is defined by subtracting the erase current from the current which generates the peak level emission intensity.
10. The optical disk device as claimed in claim 9, wherein the laser driver comprises a bottom current generating digital-to-analog converter, an erase current generating digital-to-analog converter, and a peak current generating digital-to-analog converter, and
emission currents are generated by the respective converters on the basis of the set value of the bottom current determined on the basis of the bottom current adjustment value after recording is started, that is calculated from a measured value and an ideal value of the erase current after recording is started.
11. An optical disk device, comprising:
a sample hold circuit which generates an emission intensity waveform by emission currents including a current for generating a peak level emission intensity, a current for generating a minimum bottom level emission intensity; and a current for generating an erase level emission intensity between the peak and bottom levels, and detects at least an erase level by sampling the emission intensity waveform;
a power control part which calculates an adjustment value of a bottom current after recording is started from a measured value and an ideal value of the erase current after recording is started, and calculates a set value of the erase current on the basis of the adjustment value; and
a laser driver for generating an emission current on the basis of the set value of the erase current,
wherein a bottom current is defined as the current which generates the minimum bottom level emission intensity, an erase current is defined by subtracting the bottom current from the current which generates the erase level emission intensity, and a peak current is defined by subtracting the erase current from the current which generates the peak level emission intensity.
12. The optical disk device as claimed in claim 11, wherein the laser driver comprises a bottom current generating digital-to-analog converter, an erase current generating digital-to-analog converter, and a peak current generating digital-to-analog converter, and
emission currents are generated by the respective converters on the basis of the set value of the erase current determined on the basis of the bottom current adjustment value after recording is started, that is calculated from a measured value and an ideal value of the erase current after recording is started.
13. An optical disk device, comprising:
a sample hold circuit which generates an emission intensity waveform by emission currents including a current for generating a peak level emission intensity, a current for generating a minimum bottom level emission intensity; and a current for generating an erase level emission intensity between the peak and bottom levels, and detects at least an erase level by sampling the emission intensity waveform;
a power control part which calculates an adjustment value of a bottom current after recording is started from a measured value and an ideal value of the erase current after recording is started, and calculates a set value of the peak current on the basis of the adjustment value; and
a laser driver for generating an emission current on the basis of the set value of the peak current,
wherein a bottom current is defined as the current which generates the minimum bottom level emission intensity, an erase current is defined by subtracting the bottom current from the current which generates the erase level emission intensity, and a peak current is defined by subtracting the erase current from the current which generates the peak level emission intensity.
14. The optical disk device as claimed in claim 13, wherein the laser driver comprises a bottom current generating digital-to-analog converter, an erase current generating digital-to-analog converter, and a peak current generating digital-to-analog converter, and
emission currents are generated by the respective converters on the basis of the set value of the peak current determined on the basis of the bottom current adjustment value after recording is started, that is calculated from a measured value and an ideal value of the erase current after recording is started.

1. A multiple switch device for controlling and linking a plurality of switches disposed on a circuit board, comprising:
an operation button, comprising a handle and a rod fixed to the handle;
a shaft, comprising a connecting plate disposed at an end of the shaft, and a plurality of protruding plates disposed on the shaft;
wherein the rod is engaged with the connecting plate to securely connect the shaft and the operation button; and each of the protruding plates aligns with a corresponding one of the plurality of switches; and
at least one fixing base, supporting the shaft on the circuit board.
2. The multiple switch device as claimed in claim 1, wherein the rod of the operation button comprises a recessed portion, formed in a vicinity of an end of the rod.
3. The multiple switch device as claimed in claim 2, wherein the connecting plate comprises a U-shaped hole, defined in the recessed portion of the rod.
4. The multiple switch device as claimed in claim 1, wherein the at least one fixing base is L-shaped.
5. The multiple switch device as claimed in claim 1, wherein the at least one fixing base comprises a bottom portion and a slot formed therein.
6. An electronic device, comprising:
an operation button, comprising a handle and a rod fixed to the handle;
a faceplate, comprising a hole; wherein the operation button is inserted through the hole;
a shaft, comprising a connecting plate disposed at an end of the shaft, and a plurality of protruding plates disposed on the shaft; wherein the rod is engaged with the connecting plate to securely connect the shaft and the operation button;
at least one fixing base, supporting the shaft; and
a printed circuit board, comprising a plurality of switches disposed thereon; wherein each of the protruding plates aligns with a corresponding one of the plurality of switches, and when the shaft is moved by the handle, the protruding plates are controlled to operate the switches.
7. The electronic device as claimed in claim 6, wherein the rod comprises a pair of positioning pins and a recessed portion, the positioning pins are symmetrically disposed at an end of the rod in vicinity of the handle, and the recessed portion is disposed at the other end of the rod.
8. The electronic device as claimed in claim 7, wherein the faceplate further comprises at least one pair of concave portions formed in a wall encompassing the hole.
9. The electronic device as claimed in claim 7, wherein the connecting plate comprises a U-shaped hole, formed in the recessed portion of the rod.
10. The electronic device as claimed in claim 7, wherein the faceplate further comprises a restraining pin, corresponding to the positioning pins and restricting movement of the operation button in a clockwise or counterclockwise motion.
11. The electronic device as claimed in claim 6, wherein the at least one fixing base is L-shaped.
12. The electronic device as claimed in claim 6, wherein the at least one fixing base comprises a bottom portion and a slot disposed therein.
13. The electronic device as claimed in claim 7, wherein the hole of the faceplate is a threaded hole.
14. The electronic device as claimed in claim 13, further comprising a nut, inserted in the hole of the faceplate.
15. The electronic device as claimed in claim 14, wherein the nut comprises at least one pair of concave portions, receiving the positioning pins of the rod.
16. The electronic device as claimed in claim 15, wherein the nut further comprises a restraining pin, disposed between the concave portions.
17. An electronic device comprising:
a faceplate of said electronic device extending along a user-accessible side of said electronic device to cover said side of said electronic device;
at least two switches installable in said electronic device and spaced from said faceplate respectively;
an operation button installable at said faceplate and partially exposable out of said electronic device, said operation button movable through said faceplate to partially extend in said electronic device; and
a shaft extending in said electronic device beside said at least two switches and reachable to each of said at least two switches to simultaneously control switching of said at least two switches, said shaft connectively engagable with said operation button extending in said electronic device so as to move together with said operation button in order for simultaneously controlling said switching of said at least two switches based on user-drivable movement of said operation button.
18. The electronic device as claimed in claim 17, wherein said operation button comprises a positioning pin extending therefrom to engage with said faceplate for controlling said user-drivable movement of said operation button.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of manufacturing an integrated circuit device, comprising:
providing a substrate; and
forming a free magnetic tunnel junction (MTJ) layer configured to switch between at least two different magnetic orientations over the substrate;
forming an insulating MTJ barrier layer arranged over the free MTJ layer; and
forming a pinned MTJ layer having a fixed magnetic orientation over the insulating MTJ barrier layer;
wherein the insulating MTJ barrier layer and the pinned MTJ layer have substantially aligned sidewalls which are disposed on an upper surface of the free MTJ layer.
2. The method of claim 1, wherein the substantially aligned sidewalls of the insulating MTJ barrier layer and the pinned MTJ layer are spaced apart from sidewalls of the free MTJ layer.
3. The method of claim 1, further comprising:
forming a mask over the pinned MTJ layer;
etching through at least the pinned MTJ layer where the pinned MTJ layer is exposed through the mask, the etch stopping above the free MTJ layer; and
forming a first sidewall barrier layer above the free MTJ layer and covering the sidewalls of the pinned MTJ layer.
4. The method of claim 3, wherein the first sidewall barrier layer is formed in-situ after etching through at least the pinned MTJ layer.
5. The method of claim 3, further comprising a masked etch through the free MTJ layer with the first sidewall barrier layer forming part of the mask.
6. The method of claim 5, further comprising forming a second sidewall barrier layer that covers the sidewalls of the free MTJ layer exposed by the masked etch.
7. The method of claim 6, wherein the second sidewall barrier layer is formed in-situ with the masked etch through the free MTJ layer.
8. The method of claim 3, further comprising treating the free MTJ layer in a region where it is exposed past the first sidewall barrier layer, whereby a portion of the free MTJ layer corresponding to the exposed region is rendered into a non-ferromagnetic state.
9. The method of claim 3, further comprising oxidizing the free MTJ layer through its entire thickness in a region where it is exposed past the first sidewall barrier layer.
10. The method of claim 1, further comprising:
forming a transistor in the substrate; and
coupling the transistor to the free MTJ layer through a bottom electrode.
11. A method of manufacturing an integrated circuit device, comprising:
receiving a semiconductor substrate;
forming a metal interconnect layer over the semiconductor substrate;
forming an interlayer dielectric (ILD) layer over the metal interconnect layer;
forming a bottom electrode layer over the ILD layer;
forming a free layer configured to switch between at least different magnetic orientations over the ILD layer;
forming an insulating barrier layer over the free layer; and
forming a pinned layer having a fixed magnetic orientation over the insulating barrier layer;
wherein the insulating barrier layer and the pinned layer have substantially aligned sidewalls.
12. An integrated circuit device, comprising:
a substrate;
a magnetic tunneling junction (MTJ) formed over a surface of the substrate, the MTJ comprising;
a free layer configured to switch between at least two different magnetic orientations, arranged over the surface of the substrate;
an insulating barrier layer arranged over the free layer; and
a pinned layer having a fixed magnetic orientation, arranged over the insulating barrier layer, wherein the pinned layer and the insulating barrier layer have substantially aligned sidewalls.
13. The integrated circuit of claim 12, wherein the MTJ further comprises a bottom electrode arranged between the free layer and the substrate, wherein the free layer is coupled directly to the bottom electrode.
14. The integrated circuit of claim 12, wherein the MTJ further comprises a top electrode disposed over the pinned layer.
15. The integrated circuit of claim 14, wherein the insulating barrier layer, the pinned layer, and the top electrode constitute a stack having substantially aligned sidewalls.
16. The integrated circuit of claim 12:
wherein the pinned layer and the insulating barrier layer have a first width measured between the substantially aligned sidewalls; and
wherein the free layer has a second width measured between its outer sidewalls, wherein the second width is greater than the first width.
17. The integrated circuit of claim 16, further comprising:
a first set of spacers resting on outer upper edges of free layer, and extending upwardly along the substantially aligned sidewalls of the pinned layer and the insulating barrier layer.
18. The integrated circuit of claim 16, further comprising:
a bottom electrode arranged between the free layer and the substrate, wherein the bottom electrode has a third width between its outer sidewalls, the third width being greater than the second width.
19. The integrated circuit of claim 18, further comprising:
a second set of spacers resting on outer upper edges of bottom electrode, and extending upwardly along outer sidewalls of free layer.
20. The integrated circuit of claim 19, further comprising:
a first set of spacers resting on outer upper edges of free layer, and extending upwardly along the substantially aligned sidewalls of the pinned layer and the insulating barrier layer, wherein the first set of spacers separates the second set of spacers from the substantially aligned sidewalls of pinned layer and insulating barrier layer.