1. A backlight unit comprising:
a waveguide assembly comprising a first wedge and a birefringent wedge disposed adjacent to, and arranged nose-to-tail with, the first wedge, to define an interface of the waveguide assembly, wherein:
the birefringent wedge has different indices of refraction for light propagating through the waveguide assembly in first and second polarization states; and
the first wedge is configured to propagate the light in the second polarization state at a different speed than the birefringent wedge;
a liquid crystal layer extending along the waveguide assembly, the liquid crystal layer being configured to selectively switch the light between the first and second polarization states; and
an extraction grating extending laterally along the waveguide assembly, the extraction grating being configured to extract the light from the waveguide assembly at an emission angle established in accordance with an angle of incidence of the light on the extraction grating, the angle of incidence being determined by an extent to which the light encountered the interface while propagating through the waveguide assembly in the second polarization state.
2. The backlight unit of claim 1, wherein the liquid crystal layer comprises a plurality of pixels arranged in a layer having a thickness such that each pixel is configured as a quarter-wave plate when activated.
3. The backlight unit of claim 1, wherein the first wedge comprises an isotropic material.
4. The backlight unit of claim 1, wherein:
the first wedge comprises a birefringent material;
the first wedge and the birefringent wedge have first and second axes of birefringence, respectively; and
the first and second axes of birefringence are orthogonal to one another.
5. The backlight unit of claim 1, wherein both of the refractive indices of the birefringent wedge are offset from a refractive index of the first wedge.
6. The backlight unit of claim 1, wherein one of the refractive indices of the birefringent wedge is about equal to a refractive index of the first wedge.
7. The backlight unit of claim 1, further comprising a panel waveguide disposed adjacent to the waveguide assembly, extending over a viewable display area, and comprising a plurality of volume holograms responsive to the emission angle at which the light is extracted from the waveguide assembly to determine a further emission angle at which the light is emitted from the panel waveguide.
8. The backlight unit of claim 7, wherein the plurality of volume holograms are configured to amplify an extent to which the light extracted from the waveguide assembly is converging.
9. The backlight unit of claim 7, wherein the plurality of volume holograms comprises an array of volume holograms distributed over a viewable display area.
10. The backlight unit of claim 7, wherein the waveguide assembly is disposed at an end region of the panel waveguide outside of the viewable display area.
11. The backlight unit of claim 10, wherein:
the panel waveguide comprises a set of volume holograms distributed laterally across the panel waveguide in the end region; and
the waveguide assembly is disposed at the end region such that the light extracted at the emission angle is emitted into the panel waveguide for interaction with the set of volume holograms;
the set of volume holograms redirect the light toward the array of volume holograms at a panel propagation angle based on the emission angle at which the light is injected into the panel waveguide; and
each volume hologram of the array is configured to emit backlight from the panel waveguide at a convergence angle in accordance with the panel propagation angle and the emission angle.
12. A display comprising:
a backlight unit comprising:
a light source;
a waveguide assembly disposed adjacent the light source to receive light from the light source and comprising a first wedge and a birefringent wedge disposed adjacent to, and arranged nose-to-tail with, the first wedge, to define an interface of the waveguide assembly, wherein:
the birefringent wedge has different indices of refraction for light propagating through the waveguide assembly in first and second polarization states; and
the first wedge is configured to propagate the light in the second polarization state at a different speed than the birefringent wedge;
a liquid crystal layer extending along the waveguide assembly, the liquid crystal layer being configured to selectively switch the light between the first and second polarization states as the light reflectively propagates through the waveguide assembly;
an extraction grating extending laterally along the waveguide assembly, the extraction grating being configured to extract the light from the waveguide assembly at emission angles established in accordance with respective angles of incidence of the light on the extraction grating determined by an extent to which the light encountered the interface while propagating through the waveguide assembly in the second polarization state;
a liquid crystal display (LCD) assembly configured to form images, the LCD assembly being disposed relative to the backlight unit for illumination by the light extracted from the waveguide assembly;
a camera to capture camera data of a viewer of the display; and
a processor coupled to the camera to determine, based on the camera data, data indicative of pupil location for the viewer;
wherein the processor is further coupled to the backlight unit to, based on the data indicative of the pupil location, control an angle at which the light source injects the light into the waveguide assembly to adjust directionality of the illumination provided by the backlight unit, and selectively activate pixels of the liquid crystal layer to adjust convergence of the illumination.
13. The display of claim 12, wherein the backlight unit further comprises a panel waveguide disposed adjacent to the waveguide assembly, extending across a viewable area of the display, through which the illumination is provided, and comprising a plurality of volume holograms responsive to the emission angle at which the light is extracted from the waveguide assembly to determine further emission angles at which the illumination is emitted from the panel waveguide.
14. The display of claim 13, wherein the plurality of volume holograms are configured to amplify an extent to which the light extracted from the waveguide assembly is converging.
15. The display of claim 13, wherein the plurality of volume holograms comprises an array of volume holograms distributed across a viewable display area.
16. The display of claim 13, wherein the waveguide assembly is disposed at an end region of the panel waveguide outside of the viewable display area.
17. The display of claim 16, wherein:
the panel waveguide comprises a set of volume holograms distributed laterally across the panel waveguide in the end region; and
the waveguide assembly is disposed at the end region such that the light extracted at the emission angle is emitted into the panel waveguide for interaction with the set of volume holograms;
the set of volume holograms redirect the light toward the array of volume holograms at a panel propagation angle based on the emission angle at which the light is injected into the panel waveguide; and
the array of volume holograms is configured to emit backlight from the panel waveguide at a convergence angle in accordance with the emission angle.
18. The display of claim 12, wherein:
the first wedge comprises a birefringent material;
the first wedge and the birefringent wedge have first and second axes of birefringence, respectively; and
the first and second axes of birefringence are orthogonal to one another.
19. A display comprising:
a backlight unit comprising:
a light source;
an elongate waveguide assembly having an end disposed adjacent the light source to receive light from the light source;
a panel waveguide adjacent the elongate waveguide assembly, extending across an entire viewable area of the display, having an edge along which the elongate waveguide assembly extends laterally across the panel waveguide, and through which illumination from the backlight unit is provided;
a liquid crystal layer extending along the elongate waveguide assembly, the liquid crystal layer being configured to selectively switch the light between first and second polarization states as the light reflectively propagates through the waveguide assembly; and
an extraction grating extending laterally along the elongate waveguide assembly, the extraction grating being configured to extract the light from the elongate waveguide assembly;
wherein:
the elongate waveguide assembly comprises a first wedge and a birefringent wedge disposed adjacent to, and arranged nose-to-tail with, the first wedge, to define an interface of the waveguide assembly;
the birefringent wedge has different indices of refraction for light propagating through the waveguide assembly in first and second polarization states; and
the first wedge is configured to propagate the light in the second polarization state at a different speed than the birefringent wedge;
the extraction grating extracts the light at emission angles established in accordance with respective angles of incidence of the light on the extraction grating determined by an extent to which the light encountered the interface while propagating through the elongate waveguide assembly in the second polarization state;
a processor coupled to the backlight unit to control an angle at which the light source injects the light into the elongate waveguide assembly to adjust directionality of illumination provided by the backlight unit, the processor being configured to selectively activate pixels of the liquid crystal layer to adjust convergence of the illumination;
wherein the panel waveguide comprises a plurality of volume holograms responsive to the emission angles at which the light is extracted from the elongate waveguide assembly to determine further emission angles at which the illumination is emitted from the panel waveguide.
20. The display of claim 19, wherein the elongate waveguide is disposed along a front face of the panel waveguide or along a rear face of the panel waveguide.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A control voltage generation circuit for generating a control voltage for controlling a high-voltage transistor, comprising:
an input node configured to receive a first enable signal;
an output node configured to generate the control voltage;
a transferor configured to transfer a voltage of the input node to the output node in response to a transfer signal;
an enabling voltage driver configured to drive the output node with a high voltage when the first enable signal is enabled; and
a disabling voltage driver configured to drive the output node with a negative voltage when a second enable signal is enabled in a negative mode.
2. The control voltage generation circuit of claim 1, wherein, when the output node is driven with a negative voltage, the transfer signal has a negative voltage level.
3. The control voltage generation circuit of claim 2, wherein the disabling voltage driver drives the output node with a ground voltage when the second enable signal is enabled in a normal mode.
4. The control voltage generation circuit of claim 3, wherein the first enable signal is enabled, when the second enable signal is disabled, and the first enable signal is disabled, when the second enable signal is enabled.
5. The control voltage generation circuit of claim 3, wherein a disabling level of the second enable signal is a ground voltage level in the negative mode, and the disabling level of the second enable signal is a negative voltage level in the normal mode.
6. The control voltage generation circuit of claim 3, wherein the transfer signal has a positive voltage level when the first enable signal is enabled, and the transfer signal has a ground voltage level when the output node is driven with the ground voltage level.
7. The control voltage generation circuit of claim 1, wherein the high-voltage transistor is turned on when the first enable signal is enabled, and the high-voltage transistor is turned off when the second enable signal is enabled.
8. The control voltage generation circuit of claim 1, wherein the enabling voltage driver comprises:
a high-voltage PMOS transistor, coupled to a positive voltage source, which is turned onoff in response to the first enable signal; and
an NMOS transistor, coupled between the high-voltage PMOS transistor and the output node, which is turned onoff in response to the control voltage.
9. The control voltage generation circuit of claim 1, wherein the transferor comprises a first high-voltage NMOS transistor coupled between the input node and the output node and receives the transfer signal at its gate.
10. The control voltage generation circuit of claim 9, wherein the disabling voltage driver drives the output node to a negative voltage level in the negative mode, and drives the output node to a ground voltage level in the normal mode.
11. The control voltage generation circuit of claim 1, wherein the disabling voltage driver comprises:
a disabling voltage supply node which receives a disabling voltage; and
a second high-voltage NMOS transistor coupled between the output node and the disabling voltage supply node and configured to receive the second enable signal at its gate.
12. The control voltage generation circuit of claim 8, further comprising:
a transfer signal generator configured to generate the transfer signal.
13. A non-volatile memory device, comprising:
a cell block having a plurality of cells;
a plurality of global lines;
a plurality of high-voltage transistors configured to transfer voltages of the global lines to a plurality of local lines inside the cell block;
an input node configured to receive a first enable signal applied when the cell block is selected;
an output node configured to generate a control voltage for controlling the high-voltage transistors;
a transferor configured to transfer a voltage of the input node to the output node in response to a transfer signal;
an enabling voltage driver configured to drive the output node with a high voltage when the first enable signal is enabled; and
a disabling voltage driver configured to drive the output node with a negative voltage when a second enable signal is enabled in a negative mode.
14. The non-volatile memory device of claim 13, wherein, when the output node is driven with a negative voltage, the transfer signal has a negative voltage level.
15. The non-volatile memory device of claim 14, wherein the disabling voltage driver drives the output node with a ground voltage when the second enable signal is enabled in a normal mode.
16. The non-volatile memory device of claim 15, wherein the second enable signal is enabled when the cell block is not selected.
17. The non-volatile memory device of claim 15, wherein a disabling level of the second enable signal is a ground voltage level in the negative mode, and the disabling level of the second enable signal is a negative voltage level in the normal mode.
18. The non-volatile memory device of claim 15, wherein the transfer signal has a positive voltage level when the first enable signal is enabled, and the transfer signal has a ground voltage level when the output node is driven with the ground voltage level.
19. The non-volatile memory device of claim 13, wherein the high-voltage transistors are turned on when the cell block is selected, and the high-voltage transistors are turned off when the cell block is not selected.