Author: claimsbot

What is claimed is:

1. A method of manufacturing a semiconductor device in such a manner of forming an upper layer wiring on an inter-layer insulating film covering a lower layer wiring, forming a via-plug in a via-hole formed in said inter-layer insulating film, and interconnecting said lower layer wiring and said upper layer wiring through said via-plug, said method comprising:
a via-hole forming step for forming said via-hole in said inter-layer insulating film in such a manner as to expose said lower layer wiring;
a barrier film forming step for forming a barrier film throughout a surface including said via-hole;
a conductive film forming step for forming a conductive film on said barrier film;
a first polishing step for polishing and removing said conductive film on said barrier film until said barrier film is exposed by a chemical mechanical polishing method using such a polishing liquid that said conductive film may have a higher polishing rate than said barrier film; and
a second polishing step for removing said barrier film on said inter-layer insulating film by a chemical mechanical polishing method using such a polishing liquid that said conductive film may have a lower polishing rate than said barrier film, to leave said conductive film as non-removed only in said via-hole via said barrier film, thus forming said via-plug.
2. The method of manufacturing a semiconductor device according to claim 1, wherein said second polishing step is performed with a pressure of 4-10 Psi (Pounds per square inch) applied on said barrier film on said inter-layer insulating film.
3. The method of manufacturing a semiconductor device according to claim 1, wherein said second polishing step is followed by an upper layer wiring forming step for forming said upper layer wiring on said inter-layer insulating film in such a manner that said upper layer wiring may connect to said via-plug.
4. The method of manufacturing a semiconductor device according to claim 1, wherein said barrier film comprises tantalum-based metal and said conductive film comprises copper-based metal.
5. The method of manufacturing a semiconductor device according to claim 1, wherein said lower layer wiring and said upper layer wiring comprise respectively copper-based metal.
6. A method of manufacturing a semiconductor device in such a manner of forming an upper layer wiring on an inter-layer insulating film covering a lower layer wiring, forming a via-plug in a via-hole formed in said inter-layer insulating film, and interconnecting said lower layer wiring and said upper layer wiring through said via-plug, comprising:
a via-hole forming step for forming said via-hole in said inter-layer insulating film in such a manner as to expose said lower layer wiring;
a barrier film forming step for forming a barrier film throughout a surface including said via-hole;
a conductive film forming step for forming a conductive film on said barrier film;
a first polishing step for polishing and removing said conductive film on said barrier film until said barrier film is exposed by a chemical mechanical polishing method using a polishing liquid to which hydrogen peroxide is added by 1.5 weight-percent or more; and
a second polishing step for removing said barrier film on said inter-layer insulating film by a chemical mechanical polishing method using a polishing liquid to which hydrogen peroxide is added by 0.09-1.5 weight-percent, to leave said conductive film as non-removed only in said via-hole via said barrier film, thus forming said via-plug.
7. The method of manufacturing a semiconductor device according to claim 6, wherein said second polishing step is performed with a pressure of 4-10 Psi applied on said barrier film on said inter-layer insulating film.
8. The method of manufacturing a semiconductor device according to claim 6, wherein said second polishing step is followed by an upper layer wiring forming step for forming said upper layer wiring on said inter-layer insulating film in such a manner that said upper layer wiring may connect to said via-plug.
9. The method of manufacturing a semiconductor device according to claim 6, where said barrier film comprises tantalum-based metal and said conductive film comprises copper-based metal.
10. The method of manufacturing a semiconductor device according to claim 6, wherein said lower layer wiring and said upper layer wiring comprise respectively copper-based metal.
11. A method of manufacturing a semiconductor device in such a manner of forming an upper layer wiring on an inter-layer insulating film covering a lower layer wiring, forming a via-plug in a via-hole formed in said inter-layer insulating film, and interconnecting said lower layer wiring and said upper layer wiring through said via-plug, comprising:
a via-hole forming step for forming said via-hole in said inter-layer insulating film in such a manner as to expose said lower layer wiring;
a barrier film forming step for forming a barrier film throughout a surface including said via-hole;
a conductive film forming step for forming a conductive film on said barrier film;
a first polishing step for polishing and removing said conductive film on said barrier film until said barrier film is exposed by a chemical mechanical polishing method using a polishing liquid to which hydrogen peroxide is added by 1.5 weight-percent or more; and
a second polishing step for removing said barrier film on said inter-layer insulating film by a chemical mechanical polishing method using a polishing liquid containing no hydrogen peroxide, to leave said conductive film as non-removed only in said via-hole via said barrier film, thus forming said via-plug.
12. The method of manufacturing a semiconductor device according to claim 11, wherein said second polishing step is performed with a pressure of 4-10 Psi applied on said barrier film on said inter-layer insulating film.
13. The method of manufacturing a semiconductor device according to claim 11, wherein said second polishing step is followed by an upper layer wiring forming step for forming said upper layer wiring on said inter-layer insulating film in such a manner that said upper layer wiring may connect to said via-plug.
14. The method of manufacturing a semiconductor device according to claim 11, where said barrier film comprises tantalum-based metal and said conductive film comprises copper-based metal.
15. The method of manufacturing a semiconductor device according to claim 11, wherein said lower layer wiring and said upper layer wiring comprise respectively copper-based metal.
16. A method of manufacturing a semiconductor device in such a manner of forming a wiring trench in an insulating film covering a surface of a semiconductor substrate, then forming a barrier film and a conductive film sequentially throughout a surface including said wiring trench, and then sequentially polishing said conductive film and said barrier film exposed above the surface of said wiring trench utilizing a chemical mechanical polishing method to thereby form an embedded wiring, comprising:
a first chemical mechanical polishing step for polishing and removing said conductive film exposed above said surface of said wiring trench; and
a second chemical mechanical polishing step for removing said barrier film exposed above said surface of said wiring trench by using a polishing liquid to which hydrogen peroxide is added by 0.09-1.5 weight-percent, to leave said conductive film as non-removed only in said wiring trench via said barrier film, thus forming said embedded wiring.
17. The method of manufacturing a semiconductor device according to claim 16, wherein said second chemical mechanical polishing step is performed with a pressure of 4-10 Psi applied on said barrier film exposed above said surface of said wiring trench.
18. The method of manufacturing a semiconductor device according to claim 16, wherein said barrier film comprises tantalum-based metal and said conductive film comprises copper-based metal.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1-109. (canceled)
110. An instrument for fastening tissue within a body, comprising:
an elongated tube having a proximal end for extending outside of the body and a distal end for positioning proximate the tissue;
a distal member configured to fold the tissue together, the distal member comprising:
a first member having a proximal end coupled to the distal end of the tube; and
a second member pivotably coupled to the distal end of the first member, wherein the first and second members are configured to install at least one fastener; and

a grasper coupled to at least one of the first member and the second member,
wherein the second member is pivotable between an open position for receiving tissue and a closed position for folding tissue therebetween, and wherein the grasper is configured to project outward from at least one of the first member and the second member when in the open position.
111. The instrument of claim 110, wherein the elongated tube is flexible to insert in the body transorally and extend through the esophagus and into the stomach.
112. The instrument of claim 110, wherein the elongated tube includes a lumen to receive an endoscope.
113. The instrument of claim 110, wherein the grasper is rotatably coupled to at least one of the first member and the second member.
114. The instrument of claim 110, wherein the grasper is configured to project outward from the second member when in the open position.
115. The instrument of claim 110, wherein the first and second members are configured to install multiple fasteners.
116. The instrument of claim 110, wherein one or more flexible wires extend through the elongated tube for manipulating the second member relative to the first member.
117. An instrument for fastening tissue within a body, comprising:
an elongated tube having a proximal end for extending outside of the body and a distal end for positioning proximate the tissue;
a distal member configured to fold the tissue together, the distal member comprising:
a first member having a proximal end at the distal end of the tube; and
a second member pivotably coupled to the distal end of the first member and a free end configured to be positioned distally of the first member during insertion of the elongated tube in the body, wherein the first and second members are configured to receive a fastener for fastening the tissue; and

a grasper to extend from the second member and hold tissue,
wherein the second member is pivotable between an open position for receiving tissue and a closed position for folding tissue therebetween, and wherein the grasper is configured to project outward from the second member when in the open position.
118. The instrument of claim 117, wherein the elongated tube includes a lumen to receive an endoscope, the lumen terminating at an opening proximate a pivot point of the first and second members.
119. The instrument of claim 117, wherein the elongated tube is flexible to insert in the body transorally and extend through the esophagus and into the stomach.
120. The instrument of claim 117, wherein the grasper is rotatably coupled to the second member.
121. The instrument of claim 117, wherein the first and second members are configured to receive a plurality of fasteners.
122. The instrument of claim 117, wherein one or more flexible wires extend through the elongated tube for manipulating the second member relative to the first member.
123. An instrument for fastening tissue within a body, comprising:
an elongated tube having a proximal end and a distal end;
a distal member coupled proximate the distal end of the tube and configured to fold a fundus of a stomach toward an esophageal wall, the distal member including a first member and a second member pivotally coupled to the first member, the distal member being configured to install at least one fastener into the folded fundus and esophageal wall, the second member having a connected end and a free end, the second member being configured to pivot between a first position in which the free end is located distally of the connected end and a second position in which the connected end is located distally of the free end; and
a grasper configured to grasp at least a portion of the fundus or the esophageal wall; wherein the grasper is coupled to one of the elongated tube and the distal member, and wherein the second member has a first surface facing a second surface of the stationary member in the second position, the grasper being disposed between the first and second surfaces in the second position.
124. The instrument of claim 123, wherein the grasper includes a first grasping member rotatably coupled to the first member.
125. The instrument of claim 123, wherein the elongated tube is flexible to insert in the body transorally and extend through the esophagus and into the stomach.
126. The instrument of claim 123, wherein the elongated tube includes a lumen to receive an endoscope.
127. The instrument of claim 123, wherein the grasper is configured to project outward from the second member when in the second position.
128. The instrument of claim 123, wherein the first and second members are configured to install multiple fasteners.
129. The instrument of claim 123, wherein one or more flexible wires extend through the elongated tube for manipulating the second member relative to the first member.

What is claimed is:

1. A piezoelectricelectrostrictive film type device having a lower electrode, an auxiliary electrode, a piezoelectricelectrostrictive film for a sensor, and an upper electrode provided in layers on a substrate made of a ceramic material having a thin diaphragm thereof surrounded by a thick region, wherein
the lower electrode is arranged extending continuously from the thin diaphragm to the thick region, the auxiliary electrode is provided on the thick region at a location separated from the lower electrode, and the piezoelectricelectrostrictive film is arranged bridging between the lower electrode and the auxiliary electrode.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A digitally compensated digital to analog converter system comprising:
a digital to analog converter;
a storage device for storing anti-function digital coefficients corresponding to an error function of the digital to analog converter; and
an anti-function processor for applying generated anti-function digital coefficients to the digital input of the digital to analog converter for digitally compensating for the error function of the digital to analog converter, said anti-function digital coefficients providing non-linear error compensation.
2. The digitally compensated digital to analog converter system of claim 1 further including an anti-function coefficient generator system for generating said anti-function digital coefficients.
3. The digitally compensated digital to analog converter system of claim 1 or 2 wherein said anti-function coefficients are provided by an analog to digital converter measuring an analog output of said digital to analog converter to generate a digital signal supplied to said anti-function coefficient generator.
4. The digitally compensated digital to analog converter system of claim 2 in which said anti-function coefficient generator system includes an analog to digital converter with its input connected to the output of said digital to analog converter and said anti-function generator for delivering in, a calibration mode, selected codes through a switching device to said digital to analog converter and receiving from the analog to digital converter a digital representation of the analog output, from said digital to analog converter.
5. The digitally compensated digital to analog converter system of claim 4 in which said anti-function generator comprises an Arithmetic Logic Unit (ALU) and control logic with means to implement multiple digital basis functions to provide said anti-function digital coefficients.
6. The digitally compensated digital to analog converter system of claim 5 wherein said anti-function generator further comprises an optional storage device having anti-function coefficient memory.
7. The digitally compensated digital to analog converter system of claim 5 wherein said control logic comprises means for providing control signals to said anti-function coefficient generator and to a strobe signal to said analog to digital converter.
8. The digitally compensated digital to analog converter system of claim 2 in which said anti-function coefficient generator system includes an anti-function coefficient generator and a switching device for interconnecting said digital anti-function processor with said digital to analog converter in a correction mode and interconnecting said anti-function coefficient generator with said digital to analog converter in a calibration mode.
9. The digitally compensated digital to analog converter system of claim 8 in which said anti-function generator system includes a storage device for storing the generated anti-function digital coefficients.
10. The digitally compensated digital to analog converter system of claim 8 in which said anti-function generator system includes a microprocessor.
11. The digitally compensated digital to analog converter system of claim 8 wherein said system comprises means for said calibration mode to be re-run a number of times to reduce errors during said correction mode.
12. The digitally compensated digital to analog converter system of claim 1 in which the anti-function digital coefficients are generated from the error function of the digital to analog converter corresponding to the digital input data.
13. The digitally compensated digital to analog converter system of claim 12 in which the error function and a digital basis function are used to calculate the anti-function digital coefficients.
14. The digitally compensated digital to analog converter system of claim 13 in which the digital basis function is a transfer function having multi section output levels.
15. The digitally compensated digital to analog converter system of claim 13 in which the basis function is a linear transfer function.
16. The digitally compensated digital to analog converter system of claim 13 in which the digital basis function is an orthogonal basis function.
17. A digitally compensated digital to analog converter system comprising:
a digital to analog converter;
an anti-function coefficient generator system for generating anti-function digital coefficients corresponding to the error function of the digital to analog converter; and
an anti-function processor for applying the anti-function digital coefficients to the digital input to the digital to analog converter for digitally compensating for the error function of the digital to analog converter, said anti-function digital coefficients providing non-linear error compensation.
18. The digitally compensated digital to analog converter system of claim 17 in which said anti-function coefficient generator system includes an anti-function coefficient generator and a switching device for interconnecting said digital anti-function processor with said digital to analog converter in a correction mode and interconnecting said anti-function coefficient generator with said digital to analog converter in a calibration mode.
19. The digitally compensated digital to analog converter system of claim 18 in which said anti-function coefficient generator system includes an analog to digital converter with its input connected to the output of said digital to analog converter and said anti-function generator for delivering in said calibration mode selected codes through said switching device to said digital to analog converter and receiving from the analog to digital converter a digital representation of the analog output, from said digital to analog converter.
20. The digitally compensated digital to analog converter system of claim 19 in which said anti-function generator system includes a microprocessor.
21. A digitally compensated analog to digital converter system comprising:
an analog to digital converter;
a storage device for storing anti-function digital coefficients corresponding to an error function of the analog to digital converter; and
an anti-function processor for applying generated anti-function digital coefficients to the digital output of the analog to digital converter for digitally compensating for the error function of the analog to digital converter, said anti-function digital coefficients providing non-linear error compensation.
22. A digitally compensated signal converter system comprising:
a signal converter;
a storage device for storing anti-function digital coefficients corresponding to an error function of the signal converter; and
an anti-function processor for applying generated anti-function digital coefficients to a digital signal of the signal converter for digitally compensating for the error function of the signal converter, said anti-function digital coefficients providing non-linear error compensation.
23. A method of digitally compensating a digital to analog converter comprising:
receiving digital input data for a digital to analog converter;
supplying anti-function digital coefficients derived from the error function of the digital to analog converter corresponding to the digital input data; and
applying the anti-function digital coefficients to said digital input data to precondition said digital input data to compensate for the error function of said digital to analog converter, said anti-function digital coefficients providing non-linear error compensation.
24. The method of claim 23 in which supplying anti-function digital coefficients includes generating said error function.
25. The method of claim 23 in which generating said error function includes providing a digital input code to said digital to analog converter, measuring the corresponding output of said digital to analog converter and calculating said error function from said measured output of said digital to analog converter.
26. The method of claim 23 in which supplying anti-function digital coefficients includes selecting a digital basis function from a plurality of digital basis functions, and calculating from said selected digital basis function and said error function the anti-function digital coefficient corresponding to the provided digital output code.
27. The method of claim 23 comprising the further step of storing said anti-digital coefficients in a storage device.
28. The method of claim 23 comprising the further steps of: measuring an analog output of said digital to analog converter; providing an analog to digital converter to generate a digital signal from said analog output; and supplying said digital signal to an anti-function coefficient generator.
29. A method as claimed in claim 28 comprising the step of providing calibrated control signals to said anti-function coefficient generator and to a strobe signal to said analog to digital converter.
30. A method as claimed claim 29 comprising the additional step of using said calibrated control signals in a calibration mode in a calibration loop defining a calibration cycle, wherein said calibration cycle is run at least once.
31. A method of generating anti-function digital coefficients for a digital to analog converter comprising:
selecting a digital basis function from a plurality of digital basis functions;
providing a digital input code to the digital to analog converter;
measuring the output of the digital to analog converter corresponding to that input code;
calculating from the measured output the error function of the digital to analog converter; and
calculating from the error function and the selected digital basis function the anti-function digital coefficients.
32. A method of digitally compensating an analog to digital converter comprising:
receiving analog to digital converter digital signal data;
supplying anti-function digital coefficients derived from the error function of the analog to digital converter corresponding to the digital signal data; and
applying the anti-function digital coefficients to said digital input data to precondition said digital input data to compensate for the error function of said analog to digital converter, said anti-function digital coefficients providing non-linear error compensation.
33. A method of digitally compensating a signal converter comprising:
receiving digital signal data for a signal converter;
supplying anti-function digital coefficients derived from the error function of the signal converter corresponding to the digital signal data; and
applying the anti-function digital coefficients to said digital signal data to precondition said digital signal data to compensate for the error function of said signal converter, said anti-function digital coefficients providing non-linear error compensation.
34. A computer program stored on a computer readable medium, the computer program comprising program instructions for causing a computer to perform the method of any one of claims 23, 31, 32 or 33.
35. A computer program as claimed in claim 34 stored on a record medium.
36. A computer program as claimed in claim 34 stored on a read-only memory.