Author: claimsbot

1. A method for retrieving content for a client comprising:
receiving a reference to secure content accessed via a first resource;
editing the reference to the secure content to redirect requests for the secure content to a trusted agent, the edited reference to the secure content including information that identifies the first resource and the secure content of the received reference;
forwarding the edited reference to the client; and
requesting the secure content from the first resource, by the trusted agent on behalf of the client, when the client requests the edited reference.
2. The method of claim 1, wherein the secure content is web content.
3. The method of claim 2, wherein editing the reference to the secure content includes inserting a first predetermined domain in the reference to the secure content.
4. The method of claim 1, further comprising:
returning, in response to domain name lookup requests received from the client for the first predetermined domain, an address of the trusted agent.
5. The method of claim 1, wherein the reference to the secure content is a HyperText Transfer Protocol (HTTPS) link.
6. The method of claim 1, wherein the secure content is accessed via a Secure Socket Layer (SSL) connection.
7. The method of claim 1, wherein the edited reference to the secure content includes all fields of the received reference.
8. The method of claim 1, wherein the trusted agent is implemented as first and second proxy servers in a satellite network.
9. The method of claim 1, further including:
receiving a request from the first resource to store cookies at the client; and
editing domain and path attributes of the request to reference the first resource accessed via the trusted agent.
10. A device for retrieving content for a client comprising:
means for receiving a reference to secure content accessed via a first resource;
means for editing the reference to the secure content to redirect requests for the secure content to a trusted agent, the edited reference to the secure content including information that identifies the first resource;
means for forwarding the edited reference to the client; and
means for requesting the secure content from the first resource, by the trusted agent on behalf of the client, when the client requests the edited reference.
11. The device of claim 10, wherein the secure content is web content.
12. The device of claim 11, wherein the means for editing the reference to the secure content inserts a first predetermined domain in the reference to the secure content.
13. The device of claim 10, wherein the reference to the secure content is a secure HyperText Transfer Protocol (HTTPS) link.
14. The device of claim 10, wherein the secure content is accessed via a Secure Socket Layer (SSL) connection.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of operating a synchronous memory device having a plurality of memory cell array banks, the method comprising:
receiving an external refresh bank address;
performing an auto-refresh operation on a current row of a memory cell array bank corresponding to the external refresh bank address;
responding to a power-down command by entering a self-refresh mode; and
completing auto-refresh operation for the current row for all memory cell array banks prior to updating the current row to a new row for the first time in the self-refresh mode.
2. The method of claim 1, wherein completing an auto-refresh operation for the current row for all memory cell array banks comprises sequencing through all memory cell array banks and performing a refresh operation for the current row in each bank.
3. The method of claim 2, further comprising, during sequencing through all memory cell array banks prior to updating the current row to a new row for the first time in self-refresh mode, clocking refresh operations at a faster rate than the refresh rate used after updating the current row to a new row for the first time in self-refresh mode.
4. The method of claim 1, wherein completing an auto-refresh operation for the current row for all memory cell array banks comprises initiating a simultaneous refresh operation to the current row in all memory cell array banks.
5. The method of claim 4, further comprising after updating the current row to a new row for the first time in self-refresh mode, performing a simultaneous self-refresh operation to the new current row in all memory cell array banks for each subsequent row.
6. The method of claim 5, wherein performing a simultaneous self-refresh operation comprises enabling a bank address signal for each bank during each self-refresh operation.
7. The method of claim 4, wherein performing a simultaneous self-refresh operation comprises enabling a bank address signal for each bank during each self-refresh operation.
8. The method of claim 4, further comprising after updating the current row to a new row for the first time in self-refresh mode, performing sequential self-refresh operations to the memory cell array banks for each subsequent row.
9. The method of claim 1, wherein completing an auto-refresh operation for the current row and all memory cell array banks comprises:
accepting additional external refresh bank addresses after entering self-refresh mode without leaving self-refresh mode, until a refresh operation has been performed for the current row in each memory cell array bank; and
performing self-refresh operations after the current row is updated to a new row for the first time in the self-refresh mode.
10. The method of claim 9, wherein the number of additional external refresh bank addresses accepted after entering self-refresh mode is equal to the number of memory cell array banks.
11. The method of claim 9, wherein the number of additional external refresh bank addresses accepted after entering self-refresh mode is equal to the number of memory cell array banks that have not yet had a refresh operation performed for the current row.
12. The method of claim 1, wherein completing an auto-refresh operation for the current row and all memory cell array banks prior to updating the current row to a new row for the first time in the self-refresh mode comprises initiating a simultaneous refresh operation to the current row in all memory cell array banks that have not yet had a refresh operation performed for the current row.
13. A method of operating a synchronous memory device having a plurality of memory cell array banks, the method comprising:
receiving an external refresh bank address;
performing an auto-refresh operation on a current row of a memory cell array bank corresponding to the external refresh bank address;
responding to a power-down command by entering a self-refresh mode;
in self-refresh mode, sequencing through all memory cell array banks and performing a refresh operation for the current row in each bank; and
subsequently updating the current row to a new row for the first time in the self-refresh mode.
14. A method of operating a synchronous memory device having a plurality of memory cell array banks, the method comprising:
receiving an external refresh bank address;
performing an auto-refresh operation on a current row of a memory cell array bank corresponding to the external refresh bank address;
responding to a power-down command by entering a self-refresh mode;
in self-refresh mode, initiating a simultaneous refresh operation to the current row in all memory cell array banks; and
subsequently updating the current row to a new row for the first time in the self-refresh mode.
15. A method of operating a synchronous memory device having a plurality of memory cell array banks, the method comprising:
receiving an external refresh bank address;
performing an auto-refresh operation on a current row of a memory cell array bank corresponding to the external refresh bank address;
responding to a power-down command by entering a self-refresh mode;
in self-refresh mode, initiating a simultaneous refresh operation to the current row in all memory cell array banks;
subsequently updating the current row to a new row for the first time in the self-refresh mode; and
performing sequential self-refresh operations to the memory cell array banks for each subsequent row.
16. A method of operating a synchronous memory device having a plurality of memory cell array banks, the method comprising:
receiving an external refresh bank address;
performing an auto-refresh operation on a current row of a memory cell array bank corresponding to the external refresh bank address;
responding to a power-down command by entering a self-refresh mode;
in self-refresh mode, accepting additional external refresh bank addresses without leaving self-refresh mode, until a refresh operation has been performed for the current row in each memory cell array bank;
subsequently updating the current row to a new row for the first time in the self-refresh mode; and
performing self-refresh operations after the current row is updated to a new row.
17. A method of operating a synchronous memory device having a plurality of memory cell array banks, the method comprising:
receiving an external refresh bank address;
performing an auto-refresh operation on a current row of a memory cell array bank corresponding to the external refresh bank address;
responding to a power-down command by entering a self-refresh mode;
in self-refresh mode, initiating a simultaneous refresh operation to the current row in all memory cell array banks that have not yet had a refresh operation performed for the current row;
subsequently updating the current row to a new row for the first time in the self-refresh mode; and
performing self-refresh operations after the current row is updated to a new row.
18. A method of operating a synchronous memory device having a plurality of memory cell array banks, the method comprising:
receiving an external refresh request;
performing an auto-refresh operation on a current row of a memory cell array bank in response to the external refresh request;
responding to a power-down command by entering a self-refresh mode;
in self-refresh mode, accepting additional external refresh requests without leaving self-refresh mode, and performing corresponding auto-refresh operations until a refresh operation has been performed for the current row in each memory cell array bank;
subsequently updating the current row to a new row for the first time in the self-refresh mode; and
performing self-refresh operations after the current row is updated to a new row.
19. A method of operating a memory controller, the method comprising:
issuing auto-refresh bank addresses, to a memory unit having n memory cell array banks, in a sequence that addresses all n banks, and then addresses all n banks again, such that the memory unit can sequentially refresh a current row in all n banks according to the auto-refresh bank address sequence before refreshing another row in one of the banks;
issuing a power-down command to the memory unit; and
without waking the memory unit, issuing additional auto-refresh bank addresses to the memory unit to allow the memory unit to complete refresh operations for the current row before beginning self-refresh operations.
20. The method of claim 19, wherein the number of additional auto-refresh bank addresses issued after the power-down command is equal to n.
21. The method of claim 19, wherein the number of additional auto-refresh bank addresses issued after the power-down command is equal to the number of memory cell array banks that have not yet had a refresh operation performed for the current row.
22. A memory system comprising:
at least one memory unit having n memory banks and a bank-addressable auto-refresh operation, the memory unit comprising auto-refresh circuitry that addresses auto-refresh operations to a refresh row in each addressed bank until each of the n banks have been addressed in at least one auto-refresh operation, the memory unit having circuitry for completing refresh operations for the refresh row in each not-yet-addressed bank upon entering a self-refresh mode; and
a controller to assert active commands and supply external refresh bank address signals to the memory unit, the controller having a normal auto-refresh mode that supplies all n bank address signals in n successive auto-refresh operations for a refresh row, and supplies all n bank address signals in the following n successive auto-refresh operations for a next refresh row, wherein the controller can signal the memory unit to enter self-refresh mode without completing n successive auto-refresh operations for a current refresh row.
23. The memory system of claim 22, further comprising an external refresh signal line connected between the memory unit and the controller to allow the controller to initiate auto-refresh operations on the memory unit.
24. The memory system of claim 23, wherein the memory unit responds to auto-refresh operations signaled on the external refresh signal line after entering self-refresh mode, until each bank has been addressed in at least one auto-refresh operation for the refresh row.
25. The memory system of claim 22, further comprising command signal lines connected between the memory unit and the controller, the controller requesting that the memory unit perform active commands, auto-refresh commands, and self-refresh commands by placing appropriate signaling on the command signal lines.
26. A synchronous memory device comprising:
a plurality n of independently addressable memory cell array banks;
a-refresh address generator to specify a current refresh row to all memory cell array is banks;
bank address circuitry to receive an externally supplied bank address for a refresh operation and apply the refresh operation to the memory cell array bank corresponding to the bank address;
a refresh bank address counter to signal the refresh address generator to generate a new refresh row when refresh operations have been addressed to the current refresh row in each of the plurality of memory cell array banks; and
self-refresh circuitry to apply refresh operations to the memory cell array banks in a self-refresh mode, the self-refresh circuitry comprising circuitry to complete refresh operations for the current refresh row in all memory cell array banks upon entering self-refresh mode and before updating the current refresh row to a new row.
27. The memory device of claim 26, wherein the self-refresh circuitry comprises:
a bank address generator to generate a self-refresh bank address in a self-refresh mode; and
a first switch to select either the externally supplied bank address or the self-refresh bank address for a refresh operation.
28. The memory device of claim 27, wherein the first switch selects the self-refresh bank address in a self-refresh mode.
29. The memory device of claim 28, wherein the bank address generator sequentially generates a self-refresh bank address for each memory cell array bank upon entering self-refresh mode, prior to updating the current refresh row.
30. The memory device of claim 28, wherein the bank address generator sequentially generates a self-refresh bank address for each memory cell array bank that has not been addressed in a refresh operation for the current row upon entering self-refresh mode, prior to updating the current refresh row.
31. The memory device of claim 28, further comprising a set circuit to select all memory cell array banks for a first refresh operation upon entering self-refresh mode.
32. The memory device of claim 28, further comprising a set circuit to select all memory cell array banks that have not been addressed in a refresh operation for the current row for a first refresh operation upon entering self-refresh mode.
33. The memory device of claim 27, wherein the first switch selects the self-refresh bank address once the current refresh row is updated to a new row in self-refresh mode.
34. The memory device of claim 33, wherein prior to the first switch selecting the self-refresh bank address in self-refresh mode, the memory device continues to receive externally supplied bank addresses for refresh operations.
35. The memory device of claim 34, wherein the memory device continues to receive externally supplied bank addresses for refresh operations until all memory cell array banks that were not addressed in a refresh operation for the current row prior to entering self-refresh mode have been addressed in a refresh operation.
36. The memory device of claim 34, wherein the memory device receives n externally supplied bank addresses for refresh operations after entering self-refresh mode.
37. The memory device of claim 33, wherein the first switch operates in response to the output of the refresh bank address counter.
38. The memory device of claim 27, the self-refresh clock circuitry further comprising a self-refresh clock generator to supply a refresh clock signal for refresh operations in self-refresh mode, the self-refresh clock generator supplying refresh clock signals at a first rate until refresh operations for the current refresh row are completed for all memory cell banks, and supplying refresh clock signals at a second rate once the current refresh row is updated to a new row.
39. The memory device of claim 38, wherein the self-refresh clock generator comprises an auto refresh clock generator that is enabled upon entry to self-refresh mode and disabled once the current refresh row is updated to a new row, and a self refresh clock generator that is enabled in self-refresh mode once the auto refresh clock generator is disabled, the auto refresh clock generator having an output clock signal at the first rate, the self-refresh clock generator having an output clock signal at the second rate, the self-refresh clock generator having an output stage that ORs the output clock signals of the auto refresh clock generator and the self-refresh clock generator.
40. The memory device of claim 26, wherein the self-refresh circuitry comprises a set circuit to select all memory cell array banks for refresh operations after entering self-refresh mode.
41. The memory device of claim 35, wherein the set circuit comprises a delay circuit to delay a self-refresh clock, a NOR gate to receive the self-refresh clock and the delayed self-refresh clock, and a drive circuit to drive bank address lines for all memory cell array banks in response to the NOR gate output.
42. The memory device of claim 26, wherein the self-refresh circuitry comprises a set circuit to select all memory cell array banks that have not been addressed in a refresh operation for the current row for a first refresh operation upon entering self-refresh mode.

1. An oral dosage form comprising:
(a) an effective amount of an alkalizing agent; and
(b) multiparticulates wherein said multiparticulates comprise (i) about 20% to about 75% azithromycin, and (ii) about 25% to about 80% of a glyceride which comprises glyceryl monobehenate, glyceryl dibehenate, glyceryl tribehenate or a mixture thereof; and (iii) a poloxamer.
2. An oral dosage form of claim 1 wherein the poloxamer comprises poloxamer 407.
3. An oral dosage form of claim 1 wherein the alkalizing agent comprises a bicarbonate, a phosphate, a metal hydroxide, a metal oxide or a combination thereof.
4. An oral dosage form of claim 3 wherein the alkalizing agent comprises tribasic sodium phosphate and magnesium hydroxide.
5. An oral dosage form of claim 3 further comprising about 250 mgA to about 7 gA of azithromycin.
6. An oral dosage form of claim 5 further comprising about 1.5 gA to about 4 gA of azithromycin.
7. An oral dosage form of claim 5 further comprising 1.8 to 2.2 gA of azithromycin.
8. An azithromycin oral dosage form, comprising:
(a) at least about 200 mg of tribasic sodium phosphate; and
(b) multiparticulates, wherein said multiparticulates comprise (i) azithromycin, (ii) a mixture of glyceryl monobehenate, glyceryl dibehenate and glyceryl tribehenate, and (iii) poloxamer 407, and wherein said dosage form contains about 1.5 gA to about 4 gA of azithromycin.
9. An oral dosage form of claim 8, further comprising at least about 100 mg of magnesium oxide.
10. An oral dosage form of claim 8, comprising:
(a) 300 mg to 400 mg of tribasic sodium phosphate;
(b) 200 mg to 300 mg of magnesium hydroxide; and
(c) multiparticulates, wherein said multiparticulates comprise (i) azithromycin, (ii) a mixture of glyceryl monobehenate, glyceryl dibehenate and glyceryl tribehenate, and (iii) poloxamer 407,
and wherein said dosage form contains about 1.5 gA to about 4 gA of azithromycin.
11. An oral dosage form of claim 8 further comprising 1.8 to 2.2 gA of azithromycin.
12. An oral dosage form of claim 11 wherein said azithromycin is azithromycin dihydrate.
13. An oral dosage form of claim 1 wherein said azithromycin is azithromycin dihydrate.
14. An oral dosage form of claim 3 wherein said azithromycin is at least 70 wt % crystalline.
15. An oral dosage form of claim 3 wherein said oral dosage form is a powder for oral suspension, a unit dose packet, an oral suspension, a tablet or a capsule.
16. A method for reducing the frequency of gastrointestinal side effects, associated with administering azithromycin to a mammal, comprising contiguously administering oral dosage form of claim 1 to said mammal wherein the frequency of gastrointestinal side effects is reduced as compared to the frequency experienced when administering an equal dose of azithromycin without said alkalizing agent.
17. A method of claim 16 wherein said mammal is a human.
18. A method of claim 17 further comprising administering between about 250 mgA and about 7 gA of azithromycin to said human.
19. A method of claim 18 wherein the azithromycin is administered in a single dose.
20. A method of claim 19 further comprising administering between about 1.5 and about 4 gA of azithromycin.
21. A method of claim 19 further comprising administering between about 1.5 and about 3 gA of azithromycin.
22. A method of claim 19 further comprising administering between 1.8 and 2.2 gA of azithromycin to said human in a single dose.
23. A method of claim 17 further comprising administering between 30 mgAkg and 90 mgAkg of azithromycin to a human, wherein said human is a child weighing 30 kg or less.
24. A method of claim 23 wherein the azithromycin is administered in a single dose.
25. A method of claim 24 further comprising administering between 45 mgAkg and 75 mgAkg of azithromycin to a child weighing 30 kg or less.
26. A method of claim 24 further comprising administering about 60 mgAkg of azithromycin to a child weighing 30 kg or less.
27. A method of claim 16 wherein the alkalizing agent further comprises a bicarbonate, a phosphate, a metal hydroxide, a metal oxide, or a combination thereof.
28. A method of claim 27 wherein the alkalizing agent comprises tribasic sodium phosphate and magnesium hydroxide.
29. A method of claim 27 wherein said azithromycin comprises an immediate release form of azithromycin.
30. A method of claim 27 wherein said azithromycin comprises a sustained release form of azithromycin.
31. A method of claim 27 wherein said azithromycin comprises azithromycin multiparticulates.
32. A method of claim 31 wherein said azithromycin multiparticulates comprise:
(a) azithromycin; and
(b) a pharmaceutically acceptable carrier.
33. A method of treating a bacterial or protozoal infection in a mammal in need thereof comprising administering to said mammal a single dose of an oral dosage form of claim 1.
34. A method of claim 33 wherein said mammal is a human.
35. A method of claim 34 further comprising administering between about 250 mgA and about 7 gA of azithromycin to said human.
36. A method of claim 35 wherein the azithromycin is administered in a single dose.
37. A method of claim 36 further comprising administering between about 1.5 and about 4 gA of azithromycin to said human.
38. A method of claim 36 further comprising administering between about 1.5 and about 3 gA of azithromycin to said human.
39. A method of claim 36 further comprising administering 1.8 gA to 2.2 gA of azithromycin to said human.
40. A method of claim 34 further comprising administering between 30 mgAkg and 90 mgAkg of azithromycin to said human, wherein said human is a child weighing 30 kg or less.
41. A method of claim 34 wherein the azithromycin is administered in a single dose.
42. A method of claim 41 further comprising administering between 45 mgAkg and 75 mgAkg of azithromycin to a child weighing 30 kg or less.
43. A method of claim 41 further comprising administering 60 mgAkg of azithromycin to a child weighing 30 kg or less.
44. A method of claim 33 wherein the alkalizing agent comprises a bicarbonate, a phosphate, a metal hydroxide, a metal oxide, or a combination thereof.
45. A method of claim 44 wherein the alkalizing agent comprises tribasic sodium phosphate.
46. A method of claim 45 wherein the alkalizing agent further comprises magnesium hydroxide.
47. A method of claim 44 wherein said azithromycin comprises an immediate release form of azithromycin.
48. A method of claim 44 wherein said azithromycin comprises a sustained release form of azithromycin.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for verifying a circuit design, the method comprising:
automatically analyzing a description of the circuit design to determine a receiving register receiving a clock domain crossing signal on at least one input;
automatically generating a metastability effects generator for injecting metastability effects onto an output of said receiving register based on the analysis; and
controlling said metastability effects generator to inject metastability effects during a simulation test.
2. The method of claim 1, further comprising automatically identifying a transmit clock domain associated with a transmit clock and a receive clock domain associated with a receive clock, said receive clock clocking said receiving register.
3. The method of claim 2, further comprising automatically identifying a clock domain crossing signal that crosses from said transmit clock domain to said receive clock domain and is applied as an input to said receiving register.
4. The method of claim 3, further comprising associating said metastability effects generator with said transmit clock and said receive clock.
5. The method of claim 4, further comprising associating said metastability effects generator with an input of a transmitting register in said transmit domain, said clock domain crossing signal and said output of said receiving register.
6. The method of claim 5, further comprising causing said metastability effects generator to force metastability effects onto said output of said receiving register when said transmit clock and said receive clock are aligned and said clock domain crossing signal is changing value at said input of said receiving register.
7. The method of claim 6 further comprising specifying a window of simulated time used to determine when said transmit clock and said receive clock are aligned.
8. The method of claim 7, wherein the duration of said window is selectable.
9. The method of claim 6 wherein said metastability effects generator is configured to pseudo-randomly force metastability effects.
10. The method of claim 9 wherein said metastability effects generator is configured to generate identical metastability effects when simulation of said simulation test is repeated.
11. The method of claim 6 wherein said metastability effects generator is configured to force metastability effects by inverting the logic value of said output of said receiving register.
12. The method of claim 6 wherein said metastability effects generator forces metastability effects after a delay following an active edge of said receive clock.
13. The method of claim 6 wherein said metastability effects generator forces metastability effects in accordance with a pre-determined algorithm.
14. The method of claim 5 wherein a separate metastability effects generator is associated with each individual bit of a multi-bit register in said circuit under verification.
15. The method of claim 5, further comprising automatically creating a netlist for said input to said transmitting register, said netlist used to generate a logic expression that determines, during said simulation test, when said clock domain crossing signal changes value.
16. The method of claim 1 further comprising selectively disabling at least one metastability effects generator prior to executing said simulation test.
17. The method of claim 1 further comprising using an assertion to detect incorrect behavior of said circuit design during said simulation test.
18. The method of claim 17 wherein said assertion is automatically generated.
19. The method of claim 1, wherein code for the metastability effects generator is automatically determined and stored in a separate file from a file storing the circuit description.
20. The method of claim 1, wherein code for the metastability effects generator is not found in the description of the circuit design before the analyzing of the description of the circuit design.
21. A method for verifying a circuit design, said circuit design containing a receiving register receiving a clock domain crossing signal on at least one input, the method comprising:
automatically generating a metastability effects generator for injecting metastability effects onto an output of said receiving register;
controlling said metastability effects generator to inject metastability effects during a simulation test;
generating a coverage report at the conclusion of said simulation test, wherein said coverage report comprises at least one of the following statistics acquired during simulation of said simulation test:
number of times a clock in a transmit clock domain is aligned with a clock in a receive clock domain,
number of times an input of a register receiving a clock domain crossing signal is changing when a clock in a transmit clock domain is aligned with a clock in a receive clock domain, and
number of times metastability effects are forced onto the output of a register receiving a clock domain crossing signal.
22. The method of claim 21 wherein said coverage report comprises at least one of the following statistics acquired during simulation of said simulation test:
when during simulation was a clock in a transmit clock domain aligned with a clock in a receive clock domain,
when during simulation was an input of a register receiving a clock domain crossing signal changing when a clock in a transmit clock domain was aligned with a clock in a receive clock domain, and
when during simulation were metastability effects forced onto the output of a register receiving a clock domain crossing signal.
23. A method of verifying a circuit design comprising:
automatically identifying a transmit clock domain associated with a transmit clock and a receive clock domain associated with a receive clock;
automatically identifying a clock domain crossing signal that originates at an output of a transmitting register in said transmit clock domain and is applied as an input to a receiving register in said receive clock domain by analyzing the circuit design;
automatically associating a metastability effects generator with said transmit clock and said receive clock and an input and an output of said receiving register based on the analysis; and
causing said metastability effects generator to inject metastability effects onto an output of said receiving register when said transmit clock and said receive clock are aligned and a signal on said input of said receiving register is changing during a simulation test.
24. The method of claim 23 further comprising specifying a window of simulated time used to determine when said transmit clock and said receive clock are aligned.
25. The method of claim 24 wherein the duration of said window is selectable.
26. The method of claim 23 wherein said metastability effects generator is configured to pseudo-randomly force metastability effects.
27. The method of claim 26 wherein said metastability effects generator is configured to generate identical metastability effects when simulation of said simulation test is repeated.
28. The method of claim 23 wherein said metastability effects generator is configured to force metastability effects by inverting the logic value of said output of said receiving register.
29. The method of claim 23 further comprising creating a logic expression that determines, during simulation of said simulation test, when said clock domain crossing signal changes value.
30. The method of claim 23 further comprising selectively disabling at least one metastability effects generator prior to executing said simulation test.
31. The method of claim 23 further comprising selectively removing at least one metastability effects generator prior to executing said simulation test.
32. The method of claim 23 wherein a separate metastability effects generator is associated with each individual bit of a multi-bit register in said circuit under verification.
33. The method of claim 23 further comprising using an assertion to detect incorrect behavior of said circuit design during said simulation test.
34. The method of claim 33 wherein said assertion is automatically generated.
35. The method of claim 23 further comprising generating a coverage report at the conclusion of said simulation test.
36. A system for simulating a circuit under verification by executing a simulation test, said circuit under verification having a transmit clock domain and a receive clock domain, wherein clock edges in said transmit clock domain occur asynchronously with respect to clock edges in said receive clock domain, said system comprising:
a first detector for monitoring a transmit clock in said transmit clock domain and a receive clock in said receive clock domain, said first detector adapted to detect when said clocks are aligned and to generate a signal in response to said detection;
a receiving register in said receive clock domain having an input coupled to an output of a transmitting register in said transmit clock domain;
a second detector adapted to detect a change in logic value on said input and to generate a signal in response thereto;
a metastability injector, in response to a signal generated by said first detector and a signal generated by said second detector, adapted to force the effects of metastability onto an output of said receiving register, the metastability injector automatically generated based on an analysis of the circuit under verification; and
means for verifying correct simulated operation of said circuit under verification.
37. The system of claim 36 wherein said metastability injector is configured to pseudo-randomly force the effects of metastability onto said output of said receiving register when said transmit clock and said receive clock are aligned and said input of said receiving register changes logic value.
38. The system of claim 36 wherein said first detector is configured to determine that said clocks are aligned when the active edge of said transmit clock occurs during a window of simulated time defined relative to the active edge of said receive clock.
39. The system of claim 38 wherein the width of said window is selectable.
40. The system of claim 36 further comprising a user interface adapted to selectively disable at least one of said metastability injectors simulating said circuit under verification.
41. The system of claim 36 wherein said circuit under verification contains at least one multi-bit register and a separate metastability injector is associated with each individual bit of said multi-bit register.
42. The system of claim 36 wherein said verifying means includes a user interface for presentation of a coverage report in response to said simulating of said circuit under verification.
43. A system for simulating a circuit under verification by executing a simulation test, said circuit under verification having a transmit clock domain and a receive clock domain, wherein clock edges in said transmit clock domain occur asynchronously with respect to clock edges in said receive clock domain, said system comprising:
a first detector for monitoring a transmit clock in said transmit clock domain and a receive clock in said receive clock domain, said first detector adapted to detect when said clocks are aligned and to generate a signal in response to said detection;
a receiving register in said receive clock domain having an input coupled to an output of a transmitting register in said transmit clock domain;
a second detector adapted to detect a change in logic value on said input and to generate a signal in response thereto;
a metastability injector, in response to a signal generated by said first detector and a signal generated by said second detector, adapted to force the effects of metastability onto an output of said receiving register; and
means for verifying correct simulated operation of said circuit under verification, wherein said first detector further includes:
means for recording the simulated time of an active edge of said receive clock and an active edge of said transmit clock; and
means for determining if said active edge of said transmit clock occurred during a window of simulated time defined relative to said active edge of said receive clock.
44. The system of claim 43 further comprising:
means for selecting the width of said window of simulated time.
45. A method for verifying a circuit design comprising:
automatically creating a netlist of a portion of said circuit design;
automatically identifying a clock domain crossing signal from said netlist based on an analysis of the circuit design;
automatically generating a metastability generator circuit for injecting the effects of metastability onto a node of said circuit during simulation based on the analysis;
executing a simulation test to verify said circuit design operates correctly; and
re-simulating said simulation test with said metastability generator enabled to inject metastability effects to verify said circuit design operates correctly when subjected to metastability effects.
46. A method for verifying a circuit design comprising:
automatically creating a netlist of a portion of said circuit design;
automatically identifying a clock domain crossing signal from said netlist;
automatically generating a metastability generator circuit for injecting the effects of metastability onto a node of said circuit during simulation;
executing a simulation test to verify said circuit design operates correctly; and
re-simulating said simulation test with said metastability generator enabled to inject metastability effects to said circuit design operates correctly when subjected to metastability effects;
measuring the number of times a transmit clock in a transmit domain is aligned with a receive clock in a receive clock domain during said re-simulating step; and
measuring the number of times a metastability effect is forced during said re-simulating step.
47. The method of claim 46 further comprising specifying a window of simulated time relative to an active edge of said receive clock to define when said receive clock and said transmit clock are aligned.
48. The method of claim 46 further comprising acquiring a plurality of statistics relating to the injection of the metastability effects and generating a coverage report.
49. The method of claim 46 further comprising using an assertion to automatically detect incorrect behavior of said circuit design related to the injection of metastability effects during said re-simulating step.