Author: claimsbot

1. A storage device for protecting content, comprising:
a memory device; and
a controller that controls the memory device to store encrypted content, a control file for controlling usage of the encrypted content, a security information file including information on the control file, and a title key needed for decryption of the encrypted content,
wherein the storage device is configured to send the security information file, the control file, the encrypted content and the title key to a host device, and the security information file includes an identifier indicating where the control file is stored in the storage device,
wherein the security information file, the control file, and the encrypted content are stored and sent as separate files, and
wherein the security information file further includes an initialization vector which is a value used in an encryption algorithm, the encrypted content is generated by encrypting content using the initialization vector, and the encrypted content is decrypted using the initialization vector.
2. The storage device of claim 1, wherein the security information file further includes a name of the control file.
3. The storage device of claim 1, wherein the security information file has a same name as a name of the encrypted content.
4. The storage device of claim 1, wherein the identifier includes an address where the control file is stored.
5. The storage device of claim 1, wherein the security information file has a first filename extension and the control file has a second filename extension different from the first filename extension.
6. A host device for protecting content, comprising:
a content recording device configured to:
write a control file for controlling usage of encrypted content to a storage device;
read an address of a protected area in the storage device, wherein access to the protected area is available after passing authentication;
write a title key needed for decryption of the encrypted content to the protected area at the read address;
write the encrypted content to the storage device; and
write, to the storage device, a security information file including information an identifier indicating where the control file is stored in the storage device,
wherein the security information file, the control file, and the encrypted content are stored as separate files in the storage device, and
wherein the security information file further includes an initialization vector which is a value used in an encryption algorithm, the encrypted content is generated by encrypting content using the initialization vector, and the encrypted content is decrypted using the initialization vector.
7. The host device of claim 6, wherein the security information file further includes a name of the control file.
8. The host device of claim 6, wherein the security information file has a same name as a name of the encrypted content.
9. The host device of claim 6, wherein the identifier includes an address where the control file is stored.
10. The host device of claim 6, wherein the security information file has a first filename extension and the control file has a second filename extension different from the first filename extension.
11. A host device for protecting content, comprising:
a content decryption device configured to:
read a security information file including information in a control file from a storage device;
read the control file for controlling usage of encrypted content from the storage device using the security information file;
read the encrypted content from the storage device; and
decrypt the encrypted content,
wherein the security information file includes an identifier indicating where the control file is stored in the storage device,
wherein the security information file, the control file, the encrypted content and a title key needed for decryption of the encrypted content are stored in the storage device,
wherein the security information file, the control file and the encrypted content are stored and read as separate files, and
wherein the security information file further includes an initialization vector which is a value used in an encryption algorithm, the encrypted content is generated by encrypting content using the initialization vector, and the encrypted content is decrypted using the initialization vector.
12. The host device of claim 11, wherein the security information file further includes a name of the control file.
13. The host device of claim 11, wherein the security information file has a same name as a name of the encrypted content.
14. The host device of claim 11, wherein the identifier includes an address where the control file is stored.
15. The host device of claim 11, wherein the security information file has a first filename extension and the control file has a second filename extension different from the first filename extension.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of mitigating soft errors in an asynchronous digital circuit having a stage comprising duplicate asynchronous circuit elements, each of said duplicate asynchronous digital circuit elements having at least one input terminal and at least one output terminal, each of said duplicate asynchronous digital circuit elements providing the same logic operation, comprising the steps of:
(a) asserting a digital signal at corresponding ones of each of said at least one input terminals of said duplicate asynchronous digital circuit elements;
(b) inhibiting a variation of said asserted digital signal asserted at corresponding ones of each of said at least one input terminals of said duplicate asynchronous digital circuit elements;
(c) comparing an output signal appearing at said at least one output terminal of one of said duplicate asynchronous digital circuit elements with a corresponding output signal appearing at said at least one output terminal of the other of said duplicate asynchronous digital circuit elements; and
based on the result of the comparison of the output signals:
(d) if said output signals are not deemed equivalent:
(1) inhibiting a resultant signal from being provided as output from the stage;
(2) maintaining the step of inhibiting a variation of said asserted digital signal asserted at corresponding ones of each of said at least one input terminals of said duplicate asynchronous digital circuit elements;
(3) continuing to compare an output signal appearing at said at least one output terminal of one of said duplicate asynchronous digital circuit elements with a corresponding output signal appearing at said at least one output terminal of the other of said duplicate asynchronous digital circuit elements; and
(4) continuing steps (d)(1), (d)(2) and (d)(3) until said output signals are deemed equivalent; and

(e) if said output signals are deemed equivalent:
(1) providing at least one resultant signal as output from the stage; and
(2) permitting a variation of the asserted digital signal asserted at corresponding ones of each of said at least one input terminals of said duplicate
asynchronous digital circuit elements;
whereby the stage comprising duplicate asynchronous digital circuit elements is active in the absence of soft errors and is prevented from being active during the presence of soft errors, thereby eliminating soft errors from propagating in the asynchronous digital circuit.
2. The method of mitigating soft errors in an asynchronous digital circuit having a stage comprising duplicate asynchronous circuit elements of claim 1, wherein said method employs three or more stages comprising duplicate asynchronous circuit elements.
3. The method of mitigating soft errors in an asynchronous digital circuit having a stage comprising duplicate asynchronous circuit elements of claim 1, wherein the step of comparing an output signal appearing at said at least one output terminal of one of said duplicate asynchronous digital circuit elements with a corresponding output signal appearing at said at least one output terminal of the other of said duplicate asynchronous digital circuit elements is performed by a c-element.
4. The method of mitigating soft errors in an asynchronous digital circuit having a stage comprising duplicate asynchronous circuit elements of claim 1, wherein the step of inhibiting a variation of said asserted digital signal asserted at corresponding ones of each of said at least one input terminals of said duplicate asynchronous digital circuit elements is performed by a c-element.
5. The method of mitigating soft errors in an asynchronous digital circuit having a stage comprising duplicate asynchronous circuit elements of claim 1, wherein the step of inhibiting a resultant signal from being provided as output from the stage is performed by a c-element.
6. The method of mitigating soft errors in an asynchronous digital circuit having a stage comprising duplicate asynchronous circuit elements of claim 1, wherein said method corrects a plurality of soft errors using a weak c-element.
7. An asynchronous digital circuit configured to mitigate soft error propagation, comprising:
a stage comprising duplicate asynchronous circuit elements, each of said duplicate asynchronous digital circuit elements having at least one input terminal and at least one output terminal, each of said duplicate asynchronous digital circuit elements providing the same logic operation;
a first comparison element having two input terminals and a first output, a selected one of said two input terminals connected to each of said at least one output terminal of each of said duplicate asynchronous digital circuit elements, and a second comparison element having two input terminals and a second output, a selected one of said two input terminals connected to each of said at least one output terminal of each of said duplicate asynchronous digital circuit elements; and
a control element in electrical communication with said first output of said first comparison element and said second output of said second comparison element, said control element configured to provide control signals based on the equivalence or lack of equivalence of signals appearing at said first output of said first comparison element and said second output of said second comparison element:
in the event that the signals appearing at said first and second outputs are not equivalent:
said control element provides a control signal to inhibit a resultant signal from appearing as output at an output terminal of the stage; and
said control element provides a control signal to inhibit a variation of said asserted digital signal asserted at corresponding ones of each of said at least one input terminals of said duplicate asynchronous digital circuit elements; and

in the event that the signals appearing at said first and second outputs are equivalent:
said control element provides a control signal to allow at least one resultant signal as output at said output terminal the stage; and
said control element provides a control signal to permit a variation of the asserted digital signal asserted at corresponding ones of each of said at least one input terminals of said duplicate asynchronous digital circuit elements;
so that the stage comprising duplicate asynchronous digital circuit elements is active to provide a signal representing said logic operation in the absence of soft errors and is prevented from being active during the presence of soft errors, thereby eliminating soft errors from propagating in the asynchronous digital circuit.
8. The asynchronous digital circuit configured to mitigate soft error propagation of claim 7, wherein said asynchronous digital circuit comprises three or more stages comprising duplicate asynchronous circuit elements.
9. The asynchronous digital circuit configured to mitigate soft error propagation of claim 7, wherein said first comparison element is a c-element.
10. The asynchronous digital circuit configured to mitigate soft error propagation of claim 7, wherein said control element is combined with said comparison element.
11. The asynchronous digital circuit configured to mitigate soft error propagation of claim 7, wherein said circuit is a field programmable gate array.
12. The asynchronous digital circuit configured to mitigate soft error propagation of claim 7, wherein said circuit comprises dual interlocked programmable bits.
13. The asynchronous digital circuit configured to mitigate soft error propagation of claim 7, wherein said circuit comprises a pre-charged half buffer.
14. The asynchronous digital circuit configured to mitigate soft error propagation of claim 7, wherein said circuit comprises a weak c-element.

1. A retractable headrest incorporated into a seatback pivotally associated with a seat bottom, said headrest comprising:
a plate shaped support contained within the seatback;
a scissor linkage exhibiting a plurality of interconnecting and overlapping link arms and pivotally secured at one end to said support;
a spring biased rivet at an overlapping location of said link arms for travel along a linear extending channel defined in said support;
a carriage connecting to the other end of said scissor linkage and which is linearly displaceable along said support;
a headrest support rod connected to said carriage and extending from the seatback;
a pawl pivotally supported proximate said one end of said scissor linkage, said pawl including a catch location which is biased in a first direction to engage a first pin extending from said support;
a first cable connected to said pawl and a second cable connected to said carriage; and
during rotation of the seatback from an upright design position to a forward dump position, actuation of said first cable pivoting said pawl against its bias to unseat said catch location from said pin, concurrent actuation of said second cable exerting a pulling force to compress said scissor linkage to a retracted position.
2. The invention as described in claim 1, further comprising a shingled headrest bun secured over said support rod.
3. The invention as described in claim 1, said plurality of interconnecting and overlapping link arms further comprising first, second and third pairs of individually overlapping and end-to-end pivotally connected link arms.
4. The invention as described in claim 1, further comprising a stop pin extending from a location of a selected link arm and engaging a shoulder location of said pawl at a maximum pivoted location.
5. The invention as described in claim 1, further comprising a main clock spring supported about said spring biased rivet, an outer curled projecting end of said spring engaging a further pin extending from a selected one of said overlapping link arms.
6. The invention as described in claim 5, further comprising a secondary clock spring having a first end engaged with a base link arm and an opposite end engaging said pawl into contact with said first pin.
7. The invention as described in claim 1, further comprising a seatback release lever situated on a surface of the seat back and to which remote locations of each of said first and second cables extend.
8. The invention as described in claim 7, each of said cables further comprising an outer fixed sheath through which extends an inner displaceable wire between said lever and said respective pawl and carriage.
9. The invention as described in claim 8, further comprising brackets secured to said support and in turn supporting extending ends of said outer sheath associated with each of said first and second cables.
10. A retractable headrest, comprising:
a plate shaped support embedded within a seatback;
a scissor linkage exhibiting a plurality of interconnecting link arms pivotally secured at one end to said support and at the other end to a carriage linearly displaceable along said support, said linkage exerting an extending bias against said carriage;
a rivet disposed at an overlapping intermediate location of a selected pair of said link arms for travel along a linear extending channel defined in said support;
a headrest support rod connected to said carriage and extending from the seatback; and
a pawl pivotally supported proximate a base end of the scissor linkage, said pawl including a catch location which is biased in a first direction to engage a first pin extending from a location of said plate shaped support proximate a base link arm selected from said plurality of interconnecting link arms;
a first cable connected to said pawl and a second cable connected to said carriage; and
during rotation of the seatback from an upright design position to a forward dump position, actuation of said first cable pivoting said pawl against its bias to unseat said catch location from said pin, concurrent actuation of said second cable exerting a pulling force to compress said scissor linkage to a retracted position.
11. The invention as described in claim 10, further comprising a shingled headrest bun secured over said support rod.
12. The invention as described in claim 10, said plurality of interconnecting link arms further comprising first, second and third pairs of individually overlapping and end-to-end pivotally connected link arms.
13. The invention as described in claim 10, further comprising a stop pin extending from a location of said base link arm and engaging a shoulder location of said pawl at a maximum pivoted location.
14. The invention as described in claim 10, further comprising a main clock spring supported about said rivet, an outer curled projecting end of said spring engaging a further pin extending from a selected one of said overlapping link arms and in order to exert an extensible biasing force to said scissor linkage.
15. The invention as described in claim 10, further comprising a secondary clock spring having a first end engaged with said selected link arm and an opposite end engaging said pawl into contact with said first pin.
16. The invention as described in claim 10, further comprising a seatback release lever situated on a surface of the seat back and to which remote locations of each of said first and second cables extend.
17. The invention as described in claim 16, each of said cables further comprising an outer fixed sheath through which extends an inner displaceable wire between said lever and said respective pawl and carriage.
18. The invention as described in claim 17, further comprising brackets secured to said support and in turn supporting extending ends of said outer sheath associated with each of said first and second cables.
19. A retractable headrest incorporated into a pivotal seatback, said headrest comprising:
a plate shaped support embedded within a seatback;
a scissor linkage exhibiting a plurality of interconnecting link arms pivotally secured at one end to said support and at the other end to a carriage linearly displaceable along said support;
a linearly displaceable rivet disposed at an overlapping intermediate location of a selected pair of said link arms for travel along a linear extending channel defined in said support;
a clock spring secured about said linearly displaceable pin and exhibiting a curled end engaging a selected of said overlapping link arms such that said linkage is biased in an extensible direction;
a headrest support rod connected to said carriage and extending from the seatback for receiving a headrest bun;
a pawl pivotally supported proximate a base end of the scissor linkage, said pawl including a catch location which is biased in a first direction to engage a first pin extending from a location of said plate shaped support proximate a base link arm selected from said plurality of interconnecting link arms;
a first cable extending from a first remote location and connected to said pawl, a second cable extending from a second remote location and connected to said carriage; and
during rotation of the seatback from an upright design position to a forward dump position, actuation of said first cable pivoting said pawl against its bias to unseat said catch location from said pin, concurrent actuation of said second cable exerting a pulling force to compress said scissor linkage to a retracted position.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An electronic circuit comprising:
a first substrate on which first and second antennas are formed at a predetermined interval; and
a second substrate which has the same external shape as that of the first substrate, and on which a third antenna is formed at a position of the first antenna formed on the first substrate and a fourth antenna is formed at position of the second antenna formed on the first substrate, and which is stacked and mounted on the first substrate so as to carry out wireless communications between the first antenna and the fourth antenna and have a portion not overlapping the first substrate.
2. The electronic circuit according to claim 1, wherein the first substrate and the second substrate are stacked and mounted in directions 90 degrees or 180 degrees different from each other.
3. An electronic circuit according to claim 1, further comprising:
a first substrate on which first and second antennas are formed at a predetermined interval;
a second substrate which has the same external shape as that of the first substrate, and on which third and fourth antennas are formed at positions of the first and second antennas formed on the first substrate, and which is stacked and mounted on the first substrate so as to carry out wireless communications between the first antenna and the fourth antenna and have a portion not overlapping the first substrate; and
a means for giving information on the layer positions of the first and second substrates to the substrates from the outside.
4. An electronic circuit comprising:
a first substrate on which first and second antennas are formed at a predetermined interval;
a second substrate which has the same external shape as that of the first substrate, and on which third and fourth antennas are formed at positions of the first and second antennas formed on the first substrate, and which is stacked and mounted on the first substrate so as to carry out wireless communications between the first antenna and the fourth antenna and have a portion not overlapping the first substrate; and
a control substrate which includes a control antenna for communicating with the first and fourth antennas, and controls data communications between the first substrate and the second substrate or data communications between the first and second substrates and the outside.
5. The electronic circuit according to claim 4, wherein the control substrate has the same external shape as that of the first and second substrates.
6. The electronic circuit according to claim 4, wherein the control substrate controls data communications with the outside by randomly accessing the first and second substrates.
7. The electronic circuit according to claim 4, wherein the control substrate controls random access data communications between the first and the second substrates.
8. The electronic circuit according to claim 1, further comprising:
a third substrate which has the same external shape as that of the first and second substrates, on which fifth and sixth antennas are formed at the positions of the first and second antennas formed on the first substrate, and which carries out wireless communications between the third antenna and the sixth antenna, and is stacked and mounted on the second substrate so as to have the second substrate to be sandwiched by the first substrate and the third substrate and have a portion not overlapping the second substrate, wherein
the electronic circuit carries out successive data transfer from the first substrate to the second substrate according to control by the first substrate and from the second substrate to the third substrate according to control by the second substrate.
9. The electronic circuit according to claim 4, further comprising:
a third substrate which has the same external shape as that of the first and second substrates, on which fifth and sixth antennas are formed at the positions of the first and second antennas formed on the first substrate, and which carries out wireless communications between the third antenna and the sixth antenna, and is stacked and mounted on the second substrate so as to have the second substrate to be sandwiched by the first substrate and the third substrate and have a portion not overlapping the second substrate, wherein
the electronic circuit carries out successive data transfer from the first substrate to the second substrate and from the second substrate to the third substrate according to control by the control substrate.
10. The electronic circuit according to claim 1, wherein two or more first substrates and second substrates are alternately stacked and mounted, the first and fourth antennas of the substrates are disposed so as to overlap each other, and a plurality of communications are simultaneously carried out via the antennas separated so as not to cause interference.
11. The electronic circuit according to claim 1, wherein the antennas consist of coils, and include a first coil which transmits a signal to a second coil, the second coil which receives the signal and a third coil which overlaps the first and second coils and is for transmission separately in synchronization with the first coil, and the diameters of the first to third coils are not less than a predetermined diameter corresponding to a distance between the first coil and the second coil, and less than a predetermined diameter by which reception of a signal by the second coil from the third coil remains at an intensity having no influence on reception of a signal from the first coil and which depends on a distance between the second coil and the third coil.