Author: claimsbot

1. An organic thin film transistor comprising a substrate having thereon at least three terminals of a gate electrode, a source electrode and a drain electrode, an insulator layer and an organic semiconductor layer, with a current between a source and a drain being controlled upon application of a voltage to the gate electrode, wherein the organic semiconductor layer includes an organic compound having a structure of the following general formula (a):
wherein A represents a divalent aromatic hydrocarbon group having from 6 to 60 carbon atoms or a divalent aromatic heterocyclic group having from 1 to 60 carbon atoms; and R1 to R10 each independently represents a hydrogen atom, a halogen atom, a cyano group, an alkyl group having from 1 to 30 carbon atoms, a haloalkyl group having from 1 to 30 carbon atoms, an alkoxyl group having from 1 to 30 carbon atoms, a haloalkoxyl group having from 1 to 30 carbon atoms, an alkylthio group having from 1 to 30 carbon atoms, a haloalkylthio group having from 1 to 30 carbon atoms, an alkylamino group having from 1 to 30 carbon atoms, a dialkylamino group having from 2 to 60 carbon atoms, wherein the alkyl groups of said dialkylamino group are optionally bonded to each other to form a nitrogen atom-containing cyclic structure, an alkylsulfonyl group having from 1 to 30 carbon atoms, a haloalkylsulfonyl group having from 1 to 30 carbon atoms, an aromatic hydrocarbon group having from 6 to 60 carbon atoms or an aromatic heterocyclic group having from 1 to 60 carbon atoms; each of these groups being optionally substituted; and each of these groups being optionally connected to each other to form an aromatic hydrocarbon group having from 6 to 60 carbon atoms or an aromatic heterocyclic group having from 1 to 60 carbon atoms.
2. The organic thin film transistor according to claim 1, wherein in formula (a), A is a group containing a benzene ring.
3. The organic thin film transistor according to claim 1, wherein in formula (a), A is an aromatic heterocyclic group containing a nitrogen atom.
4. The organic thin film transistor according to claim 1, wherein in formula (a), A is a divalent residue of chrysene.
5. The organic thin film transistor according to claim 1, wherein in formula (a), A is an aromatic heterocyclic group containing a 5-membered ring aromatic heterocyclic ring and a benzene ring.
6. The organic thin film transistor according to claim 4, wherein in formula (a), A is an aromatic heterocyclic group containing a 5-membered ring aromatic heterocyclic ring and a benzene ring.
7. The organic thin film transistor according to claim 5, wherein the 5-membered ring aromatic heterocyclic ring has one or more oxygen atoms or sulfur atoms, and an olefin group is connected to the benzene ring.
8. The organic thin film transistor according to claim 1, wherein in formula (a), the two butadienylene groups are substituted at a symmetric position relative to A.
9. The organic thin film transistor according to claim 1, wherein in formula (a), R1, R5, R6 and R10 are each independently a hydrogen atom or a fluorine atom.
10. The organic thin film transistor according to claim 1, wherein in formula (a), R1 to R10 are each independently a hydrogen atom or an alkyl group having from 1 to 30 carbon atom.
11. The organic thin film transistor according to claim 1, wherein in formula (a), R1 to R10 are each independently a hydrogen atom, a halogen atom, a cyano group or a haloalkyl group having from 1 to 30 carbon atoms.
12. The organic thin film transistor according to claim 1, comprising a buffer layer between each of the source and drain electrodes and the organic semiconductor layer.
13. An organic thin film light emitting transistor, wherein in the organic thin film transistor according to claim 1, light emission is obtained utilizing a current flowing between the source and the drain, and the light emission is controlled upon application of a voltage to the gate electrode.
14. The organic thin film light emitting transistor according to claim 13, wherein at least one of the source and the drain is composed of a material having a work function of 4.2 eV or more, andor at least one of them is composed of a material having a work function of not more than 4.3 eV.
15. The organic thin film light emitting transistor according to claim 13, comprising a buffer layer between each of the source and drain electrode and the organic semiconductor layer.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A dense wavelength division multiplexer for separating an optical signal into optical channels, comprising:
at least one birefringent plate for separating a plurality of optical channels of the optical signal, wherein the separating is based on the polarity of the plurality of optical channels; and
a non-linear interferometer optically coupled to the at least one birefringent plate for introducing a phase difference between at least two of the plurality of optical channels.
2. The dense wavelength division multiplexer of claim 1, further comprising a means for inputting the optical signal, comprising:
at least one lens optically coupled to the at least one birefringent plate; and
at least one optic fiber optically coupled to the lens.
3. The dense wavelength division multiplexer of claim 1, further comprising a means for outputting the optical signal, comprising:
at least one lens optically coupled to the at least one birefringent plate; and
at least two optic fibers optically coupled to the lens.
4. The dense wavelength division multiplexer of claim 1, comprising:
a first birefringent plate;
a first and second half-wave plates, each partially optically coupled to the first birefringent plate, such that the first and second half-wave plates each is capable of intercepting approximately one-half of a signal from the first birefringent plate;
a second birefringent plate optically coupled to the first birefringent plate and to the first and second half-wave plates on a side opposite to the first birefringent plate;
a lens optically coupled to the second birefringent plate on a side opposite to the first and second half-wave plates; and
the non-linear interferometer optically coupled to the lens and disposed at a distance equal to the focal length of the lens on a side opposite to the second birefringent plate.
5. The dense wavelength division multiplexer of claim 4, wherein the nonlinear interferometer comprises:
a first glass plate optically coupled to a second glass plate, forming a cavity;
a first reflective coating residing inside the cavity and on the second glass plate;
a second reflective coating residing inside the cavity and on the first glass plate;
a first waveplate residing inside the cavity between the first and second glass plates; and
a second waveplate residing outside the cavity and optically coupled to the first glass plate.
6. The dense wavelength division multiplexer of claim 5, wherein the first reflective coating comprises a reflective coating with a reflectivity of 100%.
7. The dense wavelength division multiplexer of claim 5, wherein the second reflective coating comprises a reflective coating with a reflectivity of approximately 18%.
8. The dense wavelength division multiplexer of claim 5, wherein the first waveplate comprises a 4 waveplate.
9. The dense wavelength division multiplexer of claim 5, wherein the second waveplate comprises a 8 waveplate.
10. The dense wavelength division multiplexer of claim 4 wherein the second birefringent plate comprises a thickness which provides an offset of an optical signal passing through it equal to the center-to-center distance between a fiber of a means for inputting the optical signal and a fiber of a means for outputting the separated plurality of optical channels.
11. The dense wavelength division multiplexer of claim 1, comprising:
a birefringent plate;
a first and second half-wave plates, each partially optically coupled to the birefringent plate, such that the first and second half-wave plates each is capable of intercepting approximately one-half of a signal from the birefringent plate;
a lens optically coupled to the birefringent plate and to the first and second half-wave plates on a side opposite to the birefringent plate;
a birefringent wedge optically coupled to the lens on a side opposite to the first and second half-wave plates; and
the non-linear interferometer optically coupled to the birefringent wedge on a side opposite to the lens.
12. The dense wavelength division multiplexer of claim 11, wherein the lens is disposed such that the optical signal passing through the lens and the separated optical channels passing through the lens are not equidistant from the center of the lens.
13. The dense wavelength division multiplexer of claim 11, wherein the birefringent wedge is shaped and oriented such that a deflection of signals passing through it is equal and opposite to a deflection induced by the lens.
14. The dense wavelength division multiplexer of claim 11, wherein the nonlinear interferometer comprises:
a first glass plate optically coupled to a second glass plate, forming a cavity;
a first reflective coating residing inside the cavity and on the second glass plate;
a second reflective coating residing inside the cavity and on the first glass plate;
a first waveplate residing inside the cavity between the first and second glass plates; and
a second waveplate residing outside the cavity and optically coupled to the first glass plate.
15. The dense wavelength division multiplexer of claim 14, wherein the first reflective coating comprises a reflective coating with a reflectivity of 100%.
16. The dense wavelength division multiplexer of claim 14, wherein the second reflective coating comprises a reflective coating with a reflectivity of approximately 18%.
17. The dense wavelength division multiplexer of claim 14, wherein the first waveplate comprises a 4 waveplate.
18. The dense wavelength division multiplexer of claim 14, wherein the second waveplate comprises a 8 waveplate.
19. The dense wavelength division multiplexer of claim 1, comprising:
a birefringent plate;
a half-wave plate partially optically coupled to the birefringent plate, such that the half-wave plate is capable of intercepting one-half of a signal from the birefringent plate;
a polarization beam-splitter optically coupled to the birefringent plate and the half-wave plate on a side opposite to the birefringent plate;
a prism optically coupled to the birefringent plate and the half-wave plate on a side opposite to the birefringent plate and also optically coupled to the polarization beam-splitter;
a lens optically coupled to the polarization beam splitter on a side opposite to the half-wave plate; and
the non-linear interferometer optically coupled to the lens disposed at a distance equal to the focal length of the lens and on a side opposite to the polarization beam-splitter.
20. The dense wavelength division multiplexer of claim 19, wherein the prism is disposed such that sub-signals of the optical signal which enter the prism are deflected and intercepted by the polarization beam-splitter.
21. The dense wavelength division multiplexer of claim 19, wherein the nonlinear interferometer comprises:
a first glass plate optically coupled to a second glass plate, forming a cavity;
a first reflective coating residing inside the cavity and on the second glass plate;
a second reflective coating residing inside the cavity and on the first glass plate;
a first waveplate residing inside the cavity between the first and second glass plates; and
a second waveplate residing outside the cavity and optically coupled to the first glass plate.
22. The dense wavelength division multiplexer of claim 21, wherein the first reflective coating comprises a reflective coating with a reflectivity of 100%.
23. The dense wavelength division multiplexer of claim 2 1, wherein the second reflective coating comprises a reflective coating with a reflectivity of approximately 18%.
24. The dense wavelength division multiplexer of claim 21, wherein the first waveplate comprises a 4 waveplate.
25. The dense wavelength division multiplexer of claim 21, wherein the second waveplate comprises a 8 waveplate.
26. A dense wavelength division multiplexer for separating an optical signal into optical channels, comprising:
means for inputting an optical signal, the optical signal comprising a plurality of optical channels;
a first birefringent plate optically coupled to the inputting means and an outputting means;
a first and second half-wave plates, each partially optically coupled to the first birefringent plate on a side opposite to the inputting and outputting means, such that the first and second half-wave plates each is capable of intercepting approximately one-half of a signal from the first birefringent plate;
a second birefringent plate optically coupled to the first birefringent plate and to the first and second half-wave plates on a side opposite to the first birefringent plate;
a lens optically coupled to the second birefringent plate on a side opposite to the first and second half-wave plates;
a non-linear interferometer optically coupled to the lens and disposed at a distance equal to the focal length of the lens on a side opposite to the second birefringent plate; and
means for outputting the separated plurality of optical channels along a plurality of optical paths.
27. The dense wavelength division multiplexer of claim 26, wherein the inputting means comprises:
at least one lens optically coupled to the first birefringent plate; and
at least one optic fiber optically coupled to the lens.
28. The dense wavelength division multiplexer of claim 26, wherein the outputting means comprises:
at least one lens optically coupled to the first birefringent plate; and
at least two optic fibers optically coupled to the lens.
29. The dense wavelength division multiplexer of claim 26, wherein the second birefringent plate comprises a thickness which provides an offset of an optical signal passing through it equal to the center-to-center distance between a fiber of the inputting means and a fiber of the outputting means.
30. The dense wavelength division multiplexer of claim 26, wherein the nonlinear interferometer comprises:
a first glass plate optically coupled to a second glass plate, forming a cavity;
a first reflective coating residing inside the cavity and on the second glass plate;
a second reflective coating residing inside the cavity and on the first glass plate;
a first waveplate residing inside the cavity between the first and second glass plates; and
a second waveplate residing outside the cavity and optically coupled to the first glass plate.
31. The dense wavelength division multiplexer of claim 30, wherein the first reflective coating comprises a reflective coating with a reflectivity of 100%.
32. The dense wavelength division multiplexer of claim 30, wherein the second reflective coating comprises a reflective coating with a reflectivity of approximately 18%.
33. The dense wavelength division multiplexer of claim 30, wherein the first waveplate comprises a 4 waveplate.
34. The dense wavelength division multiplexer of claim 30, wherein the second waveplate comprises a 8 waveplate.
35. A dense wavelength division multiplexer for separating an optical signal into optical channels, comprising:
means for inputting an optical signal, the optical signal comprising a plurality of optical channels;
a birefringent plate optically coupled to the inputting means and an outputting means;
a first and second half-wave plates, each partially optically coupled to the birefringent plate on a side opposite than the inputting and outputting means, such that the first and second half-wave plates each is capable of intercepting approximately one-half of a signal from the birefringent plate;
a lens optically coupled to the birefringent plate and to the first and second half-wave plates on a side opposite to the birefringent plate;
a birefringent wedge optically coupled to the lens on a side opposite to the first and second half-wave plates; and
a non-linear interferometer optically coupled to the birefringent wedge on a side opposite to the lens; and
means for outputting the separated plurality of optical channels along a plurality of optical paths.
36. The dense wavelength division multiplexer of claim 35, wherein the inputting means comprises:
at least one lens optically coupled to the birefringent plate; and
at least one optic fiber optically coupled to the lens.
37. The dense wavelength division multiplexer of claim 35, wherein the outputting means comprises:
at least one lens optically coupled to the birefringent plate; and
at least two optic fibers optically coupled to the lens.
38. The dense wavelength division multiplexer of claim 35, wherein the lens is disposed such that a signal passing through the lens from the inputting means and a signal passing through the lens towards the outputting means are not equidistant from the center of the lens.
39. The dense wavelength division multiplexer of claim 35, wherein the birefringent wedge is shaped and oriented such that a deflection of signals passing through it is equal and opposite to a deflection induced by the lens.
40. The dense wavelength division multiplexer of claim 35, wherein the nonlinear interferometer comprises:
a first glass plate optically coupled to a second glass plate, forming a cavity;
a first reflective coating residing inside the cavity and on the second glass plate;
a second reflective coating residing inside the cavity and on the first glass plate;
a first waveplate residing inside the cavity between the first and second glass plates; and
a second waveplate residing outside the cavity and optically coupled to the first glass plate.
41. The dense wavelength division multiplexer of claim 40, wherein the first reflective coating comprises a reflective coating with a reflectivity of 100%.
42. The dense wavelength division multiplexer of claim 40, wherein the second reflective coating comprises a reflective coating with a reflectivity of approximately 18%.
43. The dense wavelength division multiplexer of claim 40, wherein the first waveplate comprises a 4 waveplate.
44. The dense wavelength division multiplexer of claim 40, wherein the second waveplate comprises a 8 waveplate.
45. A dense wavelength division multiplexer for separating an optical signal into optical channels, comprising:
means for inputting an optical signal, the optical signal comprising a plurality of optical channels;
a birefringent plate optically coupled to the inputting means and an outputting means;
a half-wave plate partially optically coupled to the birefringent plate on a side opposite to the inputting and outputting means, such that the half-wave plate is capable of intercepting approximately one-half of a signal from the birefringent plate;
a polarization beam-splitter optically coupled to the birefringent plate and the half-wave plate on a side opposite to the birefringent plate;
a prism optically coupled to the birefringent plate and the half-wave plate on a side opposite to the birefringent plate and also optically coupled to the polarization beam-splitter;
a lens optically coupled to the polarization beam splitter on a side opposite to the half-wave plate; and
a non-linear interferometer optically coupled to the lens disposed at a distance equal to the focal length of the lens and on a side opposite to the polarization beam-splitter; and
means for outputting the separated plurality of optical channels along a plurality of optical paths.
46. The dense wavelength division multiplexer of claim 45, wherein the inputting means comprises:
at least one lens optically coupled to the birefringent plate; and
at least one optic fiber optically coupled to the lens.
47. The dense wavelength division multiplexer of claim 45, wherein the outputting means comprises:
at least one lens optically coupled to the birefringent plate; and
at least two optic fibers optically coupled to the lens.
48. The dense wavelength division multiplexer of claim 45, wherein the prism is disposed such that sub-signals of the optical signal which enter the prism are deflected and intercepted by the polarization beam-splitter.
49. The dense wavelength division multiplexer of claim 45, wherein the nonlinear interferometer comprises:
a first glass plate optically coupled to a second glass plate, forming a cavity;
a first reflective coating residing inside the cavity and on the second glass plate;
a second reflective coating residing inside the cavity and on the first glass plate;
a first waveplate residing inside the cavity between the first and second glass plates; and
a second waveplate residing outside the cavity and optically coupled to the first glass plate.
50. The dense wavelength division multiplexer of claim 49, wherein the first reflective coating comprises a reflective coating with a reflectivity of 100%.
51. The dense wavelength division multiplexer of claim 49, wherein the second reflective coating comprises a reflective coating with a reflectivity of approximately 18%.
52. The dense wavelength division multiplexer of claim 49, wherein the first waveplate comprises a 4 waveplate.
53. The dense wavelength division multiplexer of claim 49, wherein the second waveplate comprises a 8 waveplate.
54. A method for separating an optical signal into optical channels, comprising the steps of:
(a) splitting the optical signal into a plurality of optical channels;
(b) introducing a phase difference between at least two of the plurality of optical channels;
(c) reflecting the plurality of optical channels; and
(d) combining at least two of the reflected optical channels.
55. The method of claim 54, wherein the splitting step (a) and the combining step (d) are performed by at least one birefringent plate.
56. The method of claim 54, wherein the introducing step (b) and reflecting step (c) are performed by a non-linear interferometer.
57. A system for separating an optical signal into optical channels, comprising:
a plurality of optical fibers for carrying the optical signal of a portion thereof; and
a dense wavelength division multiplexer coupled to the plurality of optical fibers, comprising a plurality of separators at least partly arranged in a multi-stage parallel cascade configuration, each separator comprising:
at least one birefringent plate for separating a plurality of optical channels of the optical signal, wherein the separating is based on the polarity of the plurality of optical channels; and
a non-linear interferometer optically coupled to the at least one birefringent plate for introducing a phase difference between at least two of the plurality of optical channels.
58. The system of claim 57, wherein each separator comprises:
a first birefringent plate;
a first and second half-wave plates, each partially optically coupled to the first birefringent plate, such that the first and second half-wave plates each is capable of intercepting approximately one-half of a signal from the first birefringent plate;
a second birefringent plate optically coupled to the first birefringent plate and to the first and second half-wave plates on a side opposite to the first birefringent plate;
a lens optically coupled to the second birefringent plate on a side opposite to the first and second half-wave plates; and
the non-linear interferometer optically coupled to the lens and disposed at a distance equal to the focal length of the lens on a side opposite to the second birefringent plate.
59. The system of claim 57, wherein each separator comprises:
a birefringent plate;
a first and second half-wave plates, each partially optically coupled to the birefringent plate, such that the first and second half-wave plates each is capable of intercepting approximately one-half of a signal from the birefringent plate;
a lens optically coupled to the birefringent plate and to the first and second half-wave plates on a side opposite to the birefringent plate;
a birefringent wedge optically coupled to the lens on a side opposite to the first and second half-wave plates; and
the non-linear interferometer optically coupled to the birefringent wedge on a side opposite to the lens.
60. The system of claim 57, wherein each separator comprises:
a birefringent plate;
a half-wave plate partially optically coupled to the birefringent plate, such that the half-wave plate is capable of intercepting one-half of a signal from the birefringent plate;
a polarization beam-splitter optically coupled to the birefringent plate and the half-wave plate on a side opposite to the birefringent plate;
a prism optically coupled to the birefringent plate and the half-wave plate on a side opposite to the birefringent plate and also optically coupled to the polarization beam-splitter;
a lens optically coupled to the polarization beam splitter on a side opposite to the half-wave plate; and
the non-linear interferometer optically coupled to the lens disposed at a distance equal to the focal length of the lens and on a side opposite to the polarization beam-splitter.

1. A server system for transferring a communication message in a communication session, the server system being connected to a communication network, the server system comprising:
a first server to
store, in a first storage, a logical number and address information of a proxy server connected to the communication network;

in association with each other,
receive a first communication message including first address information of a first proxy server,
generate first session information for controlling a first session corresponding to the received first communication message,
extract the first address information included in the received first communication message,
retrieve a first logical number from the first storage on the basis of the extracted first address information, and
store, in a second storage, the retrieved first logical number and the generated first session information in association with each other.
2. The server system of claim 1, wherein
the first server further
extracts a second logical number from the second storage,
retrieves second address information from the first storage on the basis of the extracted second logical number, and
generates a second communication message including the retrieved second address information.
3. The server system of claim 1, further comprising:
a second server to copy information stored in the first storage to a third storage, and information stored in the second storage to a fourth storage.
4. The server system of claim 1, wherein
the communication session is a SIP session,
the first communication message is an INVITE request, and
the first address information is a header value of a Record-Route header.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method, comprising:
transmitting a first signal representative of a test operation from a test circuit to a memory via a first signal path;
transmitting a second signal, synchronized with the first signal, from the test circuit to the memory via a second signal path; and
initiating the test operation on the memory in response to the second signal arriving at the memory.
2. The method of claim 1 wherein the second signal is synchronized with an end of the first signal.
3. The method of claim 1 wherein transmitting the first signal representative of the test operation from the test circuit to the memory via the first signal path includes storing at least one of a control, address and data bit of the test operation in an input register coupled to the memory input.
4. The method of claim 3 further comprising storing at least one of a control, address and data bit of a subsequent test operation in a shadow register coupled to an input of the input register.
5. The method of claim 4 further comprising:
initiating the subsequent test operation on the memory in response to a signal, synchronized with the subsequent test operation, arriving at the memory;
wherein the test operation and subsequent test operation are performed as back-to-back operations.
6. The method of claim 1 wherein:
the first signal path is defined by a first set of one or more latches included in each of one or more communication path registers; and
the second signal path is defined by a second set of one or more latches included in each of the one or more communication path registers.
7. The method of claim 1 wherein initiating the test operation on the memory in response to the second signal arriving at the memory includes employing the second signal to trigger loading test data into the memory.
8. A method, comprising:
transmitting a first signal representative of stored test data from a memory to a test circuit via a first signal path;
transmitting a second signal, synchronized with the first signal, from the memory to the test circuit via a second signal path; and
employing the second signal to indicate arrival of the first signal at the test circuit.
9. The method of claim 8 further comprising comparing the first signal with expected values.
10. The method of claim 8 wherein transmitting the first signal representative of stored test data from the memory to the test circuit via the first signal path includes, in response to the second signal, storing the stored test data in an output register coupled to the memory output.
11. The method of claim 8 wherein:
the first signal path is defined by a first set of one or more latches included in each of one or more communication path registers; and
the second signal path is defined by a second set of one or more latches included in each of the one or more communication path registers.
12. A method, comprising:
transmitting a first signal representative of a test operation from a test circuit to a memory via a first signal path;
transmitting a second signal, synchronized with the first signal, from the test circuit to the memory via a second signal path;
initiating the test operation on the memory in response to the second signal arriving at the memory;
transmitting a third signal representative of stored test data from the memory to the test circuit via the first signal path;
transmitting the second signal, synchronized with the third signal, from the memory to the test circuit via the second signal path; and
employing the second signal transmitted from the memory to indicate arrival of the third signal at the test circuit.
13. The method of claim 12 wherein the second signal transmitted to the memory is synchronized with an end of the first signal.
14. The method of claim 12 wherein transmitting the first signal representative of the test operation from the test circuit to the memory via the first signal path includes storing at least one of a control, address and data bit of the test operation in an input register coupled to the memory input.
15. The method of claim 14 further comprising storing at least one of a control, address and data bit of a subsequent test operation in a shadow register coupled to an input of the input register.
16. The method of claim 15 further comprising:
initiating the subsequent test operation on the memory in response to a signal, synchronized with the subsequent test operation, arriving at the memory;
wherein the test operation and subsequent test operation are to be performed as back-to-back operations.
17. The method of claim 12 wherein:
the first signal path is defined by a first set of one or more latches included in each of one or more communication path registers; and
the second signal path is defined by a second set of one or more latches included in each of the one or more communication path registers.
18. The method of claim 12 wherein initiating the test operation on the memory in response to the second signal arriving at the memory includes employing the second signal to trigger loading test data into the memory.
19. The method of claim 12 further comprising comparing the third signal with an expected value.
20. The method of claim 12 wherein transmitting the third signal representative of stored test data from the memory to the test circuit via the first signal path includes, in response to the second signal transmitted from the memory, storing the stored test data in an output register coupled to the memory output.
21. A method, comprising:
transmitting a first signal representative of a test operation from a test circuit to a first memory via a first signal path;
transmitting a second signal, synchronized with the first signal, from the test circuit to the first memory via a second signal path;
transmitting the first signal from the test circuit to a second memory via a third signal path;
transmitting a third signal, synchronized with the first signal, from the test circuit to the second memory via a fourth signal path;
initiating the test operation on the first memory in response to the second signal arriving at the first memory; and
initiating the test operation on the second memory in response to the third signal arriving at the second memory.
22. The method of claim 21 wherein:
the first signal path is shorter than the third signal path; and
the second signal path is shorter than the fourth signal path.
23. The method of claim 21 further comprising:
transmitting a fourth signal representative of stored test data from the first memory to the test circuit via the first signal path;
transmitting the second signal, synchronized with the fourth signal, from the memory to the test circuit via the second signal path;
transmitting a fifth signal representative of stored test data from the second memory to the test circuit via the third signal path;
transmitting the third signal, synchronized with the fifth signal, from the second memory to the test circuit via the fourth signal path;
employing the second signal to indicate arrival of the fourth signal at the test circuit; and
employing the third signal to indicate arrival of the fifth signal at the test circuit.
24. An apparatus, comprising:
a test circuit;
a test circuit interface adapted to couple to the test circuit and a memory; and
a plurality of registers, each of which includes a plurality of latches, adapted to define a first signal path and a second signal path and couple to the test circuit interface and the test circuit;
wherein the apparatus is adapted to:
transmit a first signal representative of a test operation from the test circuit to the memory via the first signal path;
transmit a second signal, synchronized with the first signal, from the test circuit to the memory via the second signal path; and
initiate the test operation on the memory in response to the second signal arriving at the memory.
25. The apparatus of claim 24 wherein the second signal is synchronized with an end of the first signal.
26. The apparatus of claim 24 wherein:
the test circuit interface includes an input register coupled to the first signal path and a memory input; and
the apparatus is further adapted to store at least on of a control, address and data bit of the test operation in the input register.
27. The apparatus of claim 26 wherein:
the test circuit interface includes a shadow register coupled to the first signal path and an input of the input register; and
the apparatus is further adapted to store at least one of a control, address and data bit of a subsequent test operation in the shadow register.
28. The apparatus of claim 27 wherein the apparatus is further adapted to:
initiate the subsequent test operation on the memory in response to a signal, synchronized with the subsequent test operation, arriving at the memory;
wherein the test operation and subsequent test operation are back-to-back operations.
29. The apparatus of claim 24 wherein the first signal path is defined by a first set of one or more latches included in each of the plurality of registers; and
the second signal path is defined by a second set of one or more latches included in each of the plurality of registers.
30. The apparatus of claim 24 wherein the apparatus is further adapted to employ the second signal to load test data into the memory.
31. An apparatus, comprising:
a test circuit;
a test circuit interface adapted to couple to the test circuit and a memory; and
a plurality of registers, each of which includes a plurality of latches, adapted to define a first signal path and a second signal path and couple to the test circuit interface and the test circuit;
wherein the apparatus is adapted to:
transmit a first signal representative of stored test data from the memory to the test circuit via the first signal path;
transmit a second signal, synchronized with the first signal, from the memory to the test circuit via the second signal path; and

employ the second signal to indicate arrival of the first signal at the test circuit.
32. The apparatus of claim 31 wherein the apparatus is further adapted to compare the first signal with an expected value.
33. The apparatus of claim 31 wherein:
the test circuit interface includes an output register coupled to a memory output and the first signal path; and
the apparatus is further adapted to, in response to the second signal, store the stored test data in the output register.
34. The apparatus of claim 31 wherein:
the first signal path is defined by a first set of one or more latches included in the plurality of registers; and
the second signal path is defined by a second set of one or more latches included in the plurality of registers.
35. An apparatus, comprising:
a test circuit;
a test circuit interface adapted to couple to the test circuit and a memory; and
a plurality of registers, each of which includes a plurality of latches, adapted to define a first signal path and a second signal path and couple to the test circuit interface and the test circuit;
wherein the apparatus is adapted to:
transmit a first signal representative of a test operation from the test circuit to the memory via the first signal path;
transmit a second signal, synchronized with the first signal, from the test circuit to the memory via the second signal path; and
initiate the test operation on the memory in response to the second signal arriving at the memory;
transmit a third signal representative of stored test data from the memory to the test circuit via the first signal path;
transmit the second signal, synchronized with the third signal, from the memory to the test circuit via the second signal path; and
employ the second signal to indicate arrival of the third signal at the test circuit.
36. The apparatus of claim 35 wherein the second signal is synchronized with an end of the first signal.
37. The apparatus of claim 35 wherein:
the test circuit interface includes an input register coupled to the first signal path and a memory input; and
the apparatus is further adapted to store at least one of a control, address and data bit of the test operation in the input register.
38. The apparatus of claim 37 wherein:
the test circuit interface includes a shadow register coupled to the first signal path and an input of the input register; and
the apparatus is further adapted to store at least one of a control, address and data bit of a subsequent test operation in the shadow register.
39. The apparatus of claim 38 wherein the apparatus is further adapted to:
initiate the subsequent test operation on the memory in response to a signal, synchronized with the subsequent test operation, arriving at the memory;
wherein the test operation and subsequent test operation are to be performed as back-to-back operations.
40. The apparatus of claim 35 wherein:
the first signal path is defined by a first set of one or more latches included in the plurality of registers; and
the second signal path is defined by a second set of one or more latches included in the plurality of registers.
41. The apparatus of claim 35 wherein the apparatus is further adapted to employ the second signal to load test data into the memory.
42. The apparatus of claim 35 wherein the apparatus is further adapted to compare the third signal with an expected value.
43. The apparatus of claim 35 wherein:
the test circuit interface includes an output register coupled to a memory output and the first signal path; and
the apparatus is further adapted to, in response to the second signal, store the stored test data in the output register.
44. An apparatus, comprising:
a test circuit;
a first test circuit interface adapted to couple to the test circuit and a first memory; and
a first plurality of registers, each of which includes a first plurality of latches, adapted to define a first signal path and a second signal path and couple to the first test circuit interface and the test circuit;
a second test circuit interface adapted to couple to the test circuit and a second memory; and
a second plurality of registers, each of which includes a second plurality of latches, adapted to define a third signal path and a fourth signal path and couple to the second test circuit interface and the test circuit;
wherein the apparatus is adapted to:
transmit a first signal representative of a test operation from the test circuit to the first memory via the first signal path;
transmit a second signal, synchronized with the first signal, from the test circuit to the first memory via the second signal path;
transmit the first signal from the test circuit to the second memory via the third signal path;
transmit a third signal, synchronized with the first signal, from the test circuit to the second memory via the fourth signal path;
initiate the test operation on the first memory in response to the second signal arriving at the first memory; and
initiate the test operation on the second memory in response to the third signal arriving at the second memory.
45. The apparatus of claim 44 wherein:
the first signal path is shorter than the third signal path; and
the second signal path is shorter than the fourth signal path.
46. The apparatus of claim 44 wherein the apparatus is further adapted to:
transmit a fourth signal representative of stored test data from the first memory to the test circuit via the first signal path;
transmit the second signal, synchronized with the fourth signal, from the memory to the test circuit via the second signal path;
transmit a fifth signal representative of stored test data from the second memory to the test circuit via the third signal path;
transmit the third signal, synchronized with the fifth signal, from the second memory to the test circuit via the fourth signal path;
employ the second signal to indicate arrival of the fourth signal at the test circuit; and
employ the third signal to indicate arrival of the fifth signal at the test circuit.
47. The method of claim 4 wherein the shadow register includes a single latch for storing a data bit.
48. The method of claim 15 wherein the shadow register includes a single latch for storing a data bit.
49. The apparatus of claim 27 wherein the shadow register includes a single latch for storing a data bit.
50. The apparatus of claim 38 wherein the shadow register includes a single latch for storing a data bit.