Author: claimsbot

1. An apparatus comprising:
a high power excimer or molecular fluorine gas discharge laser DUV light source system comprising:
a pulse stretcher comprising:
an optical delay line mirror,
an optical delay line mirror gas purging assembly comprising:
a purging gas supply system directing purging gas across a face of the optical delay line mirror.
2. The apparatus of claim 1 further comprising:
the optical delay line mirror comprising a plurality of optical delay line mirrors;
the purging gas supply system directing purging gas across a face of each of the plurality of optical delay line mirrors.
3. The apparatus of claim 1 further comprising:
the purging gas supply system comprising:
a purging gas supply line;
a purging gas distributing and directing mechanism directing purging gas across the face of the respective optical delay mirror.
4. The apparatus of claim 2 further comprising:
the purging gas supply system comprising:
a purging gas supply line;
a purging gas distributing and directing mechanism directing purging gas across the face of the respective optical delay mirror.
5. The apparatus of claim 1 further comprising:
the purging gas supply system comprising:
a purging gas supply line;
a purging gas distribution manifold and a baffle arrangement directing purging gas across the face of the respective optical delay path mirror.
6. The apparatus of claim 2 further comprising:
the purging gas supply system comprising:
a purging gas supply line;
a purging gas distribution manifold and a baffle arrangement directing purging gas across the face of the respective optical delay path mirror.
7. The apparatus of claim 3 further comprising:
the purging gas supply system comprising:
a purging gas supply line;
a purging gas distribution manifold and a baffle arrangement directing purging gas across the face of the respective optical delay path mirror.
8. The apparatus of claim 4 further comprising:
the purging gas supply system comprising:
a purging gas supply line;
a purging gas distribution manifold and a baffle arrangement directing purging gas across the face of the respective optical delay path mirror.
9. The apparatus of claim 5 further comprising:
the baffle comprising a light transmitting opening exposing a respective optical delay path mirror to a light beam in the delay path.
10. The apparatus of claim 6 further comprising:
the baffle comprising a light transmitting opening exposing a respective optical delay path mirror to a light beam in the delay path.
11. The apparatus of claim 7 further comprising:
the baffle comprising a light transmitting opening exposing a respective optical delay path mirror to a light beam in the delay path.
12. The apparatus of claim 8 further comprising:
the baffle comprising a light transmitting opening exposing a respective optical delay path mirror to a light beam in the delay path.
13. The apparatus of claim 5 further comprising:
the distribution manifold comprising:
a top plate and a bottom plate forming internal channels when joined together connecting a purging gas inlet plenum to gas manifold gas distribution openings.
14. The apparatus of claim 6 further comprising:
the distribution manifold comprising:
a top plate and a bottom plate forming internal channels when joined together connecting a purging gas inlet plenum to gas manifold gas distribution openings.
15. The apparatus of claim 7 further comprising:
the distribution manifold comprising:
a top plate and a bottom plate forming internal channels when joined together connecting a purging gas inlet plenum to gas manifold gas distribution openings.
16. The apparatus of claim 8 further comprising:
the distribution manifold comprising:
a top plate and a bottom plate forming internal channels when joined together connecting a purging gas inlet plenum to gas manifold gas distribution openings.
17. The apparatus of claim 9 further comprising:
a mirror position adjustment mechanism adjusting the position of an optical delay path mirror to correct for errors in the alignment of the optical delay path.
18. The apparatus of claim 10 further comprising:
a mirror position adjustment mechanism adjusting the position of an optical delay path mirror to correct for errors in the alignment of the optical delay path.
19. The apparatus of claim 11 further comprising:
a mirror position adjustment mechanism adjusting the position of an optical delay path mirror to correct for errors in the alignment of the optical delay path.
20. The apparatus of claim 12 further comprising:
a mirror position adjustment mechanism adjusting the position of an optical delay path mirror to correct for errors in the alignment of the optical delay path.
21. The apparatus of claim 13 further comprising:
a mirror position adjustment mechanism adjusting the position of an optical delay path mirror to correct for errors in the alignment of the optical delay path.
22. The apparatus of claim 14 further comprising:
a mirror position adjustment mechanism adjusting the position of an optical delay path mirror to correct for errors in the alignment of the optical delay path.
23. The apparatus of claim 15 further comprising:
a mirror position adjustment mechanism adjusting the position of an optical delay path mirror to correct for errors in the alignment of the optical delay path.
24. The apparatus of claim 16 further comprising:
a mirror position adjustment mechanism adjusting the position of an optical delay path mirror to correct for errors in the alignment of the optical delay path.
25. The apparatus of claim 17 further comprising:
the mirror position adjustment mechanism comprising:
an optical delay path mirror mount moveably connected to an optical delay path housing wall for movement of the optical delay path mirror relative to the optical delay path.
26. The apparatus of claim 18 further comprising:
the mirror position adjustment mechanism comprising:
an optical delay path mirror mount moveably connected to an optical delay path housing wall for movement of the optical delay path mirror relative to the optical delay path.
27. The apparatus of claim 19 further comprising:
the mirror position adjustment mechanism comprising:
an optical delay path mirror mount moveably connected to an optical delay path housing wall for movement of the optical delay path mirror relative to the optical delay path.
28. The apparatus of claim 20 further comprising:
the mirror position adjustment mechanism comprising:
an optical delay path mirror mount moveably connected to an optical delay path housing wall for movement of the optical delay path mirror relative to the optical delay path.
29. The apparatus of claim 21 further comprising:
the mirror position adjustment mechanism comprising:
an optical delay path mirror mount moveably connected to an optical delay path housing wall for movement of the optical delay path mirror relative to the optical delay path.
30. The apparatus of claim 22 further comprising:
the mirror position adjustment mechanism comprising:
an optical delay path mirror mount moveably connected to an optical delay path housing wall for movement of the optical delay path mirror relative to the optical delay path.
31. The apparatus of claim 23 further comprising:
the mirror position adjustment mechanism comprising:
an optical delay path mirror mount moveably connected to an optical delay path housing wall for movement of the optical delay path mirror relative to the optical delay path.
32. The apparatus of claim 24 further comprising:
the mirror position adjustment mechanism comprising:
an optical delay path mirror mount moveably connected to an optical delay path housing wall for movement of the optical delay path mirror relative to the optical delay path.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A mixture, comprising:
a first compound formed of 2-phenylimidazole; and
a second compound of at least one selected from the group consisting of a compound having a structure expressed in Chemical formula 1, a compound having a structure expressed in Chemical formula 2, and a compound having a structure expressed in Chemical formula 3:
where X1 represents an element of Group 1 in the long-period periodic table;
where X2 represents an element of Group 1 in the long-period periodic table; and
where Y represents hydrogen or halogen, X3 represents an element of Group 1 in the long-period periodic table, and n represents a positive integer,
wherein the mixture is insoluble in water.
2. The mixture according to claim 1, wherein the second compound contains at least one of a polymer having the structure expressed in Chemical formula 1, and a polymer having the structure expressed in Chemical formula 2.
3. The mixture of claim 1, wherein the second compound is pentafluoroethanesulfonimide.
4. A cation conductor, comprising:
a first compound formed of 2-phenylimidazole; and
a second compound of at least one selected from the group consisting of a compound having a structure expressed in Chemical formula 4, a compound having a structure expressed in Chemical formula 5, and a compound having a structure expressed in Chemical formula 6:
where X1 represents an element of Group 1 in the long-period periodic table;
where X2 represents an element of Group 1 in the long-period periodic table; and
where Y represents hydrogen or halogen, X3 represents an element of Group 1 in the long-period periodic table, and n represents a positive integer,
wherein a mixture of the first compound and the second compound is insoluble in water.
5. The cation conductor according to claim 4, wherein the second compound contains at least one of a polymer having the structure expressed in Chemical formula 4, and a polymer having the structure expressed in Chemical formula 5.
6. The cation conductor according to claim 4, further containing a support for supporting the first compound and the second compound.
7. The cation conductor according to claim 6, wherein the support contains a polymer.
8. The cation conductor according to claim 6, further containing a solvent.
9. The cation conductor of claim 4, wherein the second compound is pentafluoroethanesulfonimide.
10. An electrochemical device, comprising a pair of electrodes is arranged with a cation conductor in between,
wherein the cation conductor contains:
a first compound formed of 2-phenylimidazole; and
a second compound of at least one selected from the group consisting of a compound having a structure expressed in Chemical formula 7, a compound having a structure expressed in Chemical formula 8, and a compound having a structure expressed in Chemical formula 9:
where X1 represents an element of Group 1 in the long-period periodic table; and
where X2 represents an element of Group 1 in the long-period periodic table;
where Y represents hydrogen or halogen, X3 represents an element of Group 1 in the long-period periodic table, and n represents a positive integer
wherein a mixture of the first compound and the second compound is insoluble in water.
11. The electrochemical device according to claim 10, wherein the second compound contains at least one of a polymer having the structure expressed in Chemical formula 7, and a polymer having the structure expressed in Chemical formula 8.
12. The electrochemical device according to claim 10, wherein the cation conductor further contains a support for supporting the first compound and the second compound.
13. The electrochemical device according to claim 12, wherein the support contains a polymer.
14. The electrochemical device according to claim 12, wherein the cation conductor further contains a solvent.
15. The electrochemical device according to claim 10, which is a fuel cell.
16. The electrochemical device of claim 10, wherein the second compound is pentafluoroethanesulfonimide.

1. A storage system comprising:
a plurality of flash packages, each of which includes a plurality of flash chips to store data or parity, and a device controller configured to be coupled to the plurality of flash chips, and
a RAID controller configured to be coupled to the plurality of flash packages and to control the plurality of flash packages as a RAID group, the plurality of flash packages including a first flash package storing old data and a second flash package storing old parity;
wherein the storage system is configured to perform steps of:
generating first intermediate parity based on the old data stored in the first flash package and new data sent from a host computer by a first device controller of the first flash package;
transferring the first intermediate parity from the first flash package to a second flash package which is one of the plurality of flash packages and has stored old parity;
generating first new parity based on the first intermediate parity and the old parity stored in the second flash package by a second controller of the second flash package; and
invalidating the old data by the first device controller after storing the first new parity on a flash chip of the second flash package.
2. The storage system according to claim 1,
wherein the storage system is configured to perform steps of:
sending complete information, based on storing the first new parity on the flash chip of the second flash package, from the second flash package to the RAID controller;
sending instruction for invalidating old data from the RAID controller to the first flash package based on the complete information; and
invalidating the old data based on the instruction.
3. The storage system according to claim 2,
wherein each of the plurality of flash chips of the first flash package includes a plurality of physical pages to store data or parity, and the first device controller has a page mapping management table which relates physical pages to logical pages,
wherein the first device controller has related a first logical page to a first physical page, which has stored old data, on the page mapping management table, and
wherein the first device controller is configured to perform steps of:
relating a second physical page, in which the new data are stored and which is different from the first physical page, to the first logical page while keeping on relating the first physical page to the first logical page on the page mapping management table, when the first device controller stores the new data on a flash chip of the first flash package; and
deleting a piece of information of the first physical page from the page mapping management table for invalidating the old data.
4. The storage system according to claim 3,
wherein the first device controller is configured to perform a step of:
deleting the old data after deleting the piece of information of the first physical page from the page mapping management table.
5. The storage system according to claim 1,
wherein when the RAID controller does not receive the complete information in a predetermined time from the second flash package, the storage system is configured to perform steps of:
generating second intermediate parity based on the old data and the new data by the first device controller;
transferring the second intermediate parity from the first device controller to the second device controller; and
generating second new parity based on the second intermediate parity and the old parity by the second device controller.
6. A storage system comprising:
a plurality of flash packages, each of which includes a plurality of flash chips to store data or parity, and a device controller configured to be coupled to the plurality of flash chips, and
a RAID controller configured to be coupled to the plurality of flash packages and to control the plurality of flash packages as a RAID group, the plurality of flash packages including a first flash package storing old data and a second flash package storing old parity;
wherein a first device controller of a first flash package is configured to perform steps of:
storing new data which are received from the RAID controller while keeping old data which have been stored in the first flash package;
generating first intermediate parity based on the new data received from the RAID controller and the old data stored in the first flash package, the first intermediate parity is transferred to the second flash package;
and
invalidating the old data after first new parity, which is generated based on the old parity which has been stored on the second flash package and the first intermediate parity, is stored on a flash chip of the second flash package.
7. The storage system according to claim 6,
wherein the storage system is configured to perform steps of:
sending complete information, based on storing the first new parity on the flash chip of the second flash package, from the second flash package to the RAID controller;
sending instruction for invalidating old data from the RAID controller to the first flash package based on the complete information; and
invalidating the old data based on the instruction.
8. The storage system according to claim 7,
wherein each of the plurality of flash chips of the first flash package includes a plurality of physical pages to store data or parity, and the first device controller has a page mapping management table which relates physical pages to logical pages,
wherein the first device controller has related a first logical page to a first physical page, which has stored old data, on the page mapping management table, and
wherein the first device controller is configured to perform steps of:
relating a second physical page, in which the new data are stored and which is different from the first physical page, to the first logical page while keeping on relating the first physical page to the first logical page on the page mapping management table, when the first device controller stores the new data on a flash chip of the first flash package; and

deleting a piece of information the first physical page from the page mapping management table for invalidating the old data.
9. The storage system according to claim 8,
wherein the first device controller is configured to perform a step of:
deleting the old data after deleting the piece of information of the first physical page from the page mapping management table.
10. The storage system according to claim 7,
wherein when the RAID controller does not receive the complete information in a predetermined time from the second flash package, the storage system is configured to perform steps of:
generating second intermediate parity based on the old data and the new data by the first device controller;
transferring the second intermediate parity from the first device controller to the second device controller; and
generating second new parity based on the second intermediate parity and the old data by the second device controller.
11. A storage system comprising:
a plurality of flash packages, each of which includes a plurality of flash chips to store data or parity, and a device controller configured to be coupled to the plurality of flash chips, and
a RAID controller configured to be coupled to the plurality of flash packages and to control the plurality of flash packages as a RAID group, the plurality of flash packages including a first flash package storing old data and a second flash package storing old parity;
wherein a second device controller of a second flash package is configured to perform steps of:
receiving first intermediate parity, which is generated by a first device controller of a first flash package based on new data, which are received from the RAID controller, and old data, which have been stored in the first flash package, from the first flash package;
generating first new parity based on the first intermediate parity and the old parity, which has been stored in the second flash package; and
storing the first new parity on a flash chip of the second flash package before the old data are invalidated by the first device controller.
12. The storage system according to claim 11,
wherein the storage system is configured to perform steps of:
sending complete information, based on storing the first new parity on the flash chip of the second flash package, from the second flash package to the RAID controller;
sending instruction for invalidating the old data from the RAID controller to the first flash package based on the complete information; and
invalidating the old data based on the instruction.
13. The storage system according to claim 12,
wherein each of the plurality of flash chips of the first flash package includes a plurality of physical pages to store data or parity, and the first device controller has a page mapping management table which relates physical pages to logical pages,
wherein the first device controller has related a first logical page to a first physical page, which has stored old data, on the page mapping management table, and
wherein the first device controller is configured to perform steps of:
relating a second physical page, in which the new data are stored and which is different from the first physical page, to the first logical page while keeping on relating the first physical page to the first logical page on the page mapping management table, when the first device controller stores the new data on the first flash package; and
deleting a piece of information of the first physical page from the page mapping management table for invalidating the old data.
14. The storage system according to claim 13,
wherein the first device controller is configured to perform a step of:
deleting the old data after deleting the piece of information of the first physical page from the page mapping management table.
15. The storage system according to claim 12,
wherein when the RAID controller does not receive the complete information in a predetermined time from the second flash package, the storage system is configured to perform steps of:
generating second intermediate parity based on the old data and the new data by the first device controller;
transferring the second intermediate parity from the first device controller to the second device controller; and
generating second new parity based on the second intermediate parity and the old parity by the second device controller.
16. A storage system comprising:
a plurality of flash packages, each of which includes a plurality of flash chips to store data or parity, and a device controller configured to be coupled to the plurality of flash chips, and
a RAID controller configured to be coupled to the plurality of flash packages and to control the plurality of flash packages as a RAID group, the plurality of flash packages including a first flash package storing old data and a second flash package storing old parity;
wherein the RAID controller or the plurality of flash packages have parity operation parts configured to generate parity;
wherein when a first flash package and a second flash package have parity operation parts, the storage system is configured to perform steps of:
generating first intermediate parity based on the old data stored in the first flash package and new data sent from a host computer by a first device controller of the first flash package;
transferring the first intermediate parity from the first flash package to the second flash package;
generating first new parity based on the intermediate parity and the old parity stored in the second flash package by a second controller of the second flash package; and
invalidating the old data after storing the new parity on a flash chip of the second flash package; and

wherein when the first device controller and the second device controller do not have the parity operation parts and the RAID controller has the parity operation part, the storage system is configured to perform a step of:
generating third new parity by the RAID controller.
17. The storage system according to claim 16,
wherein the storage system is configured to perform steps of:
sending complete information, based on storing the first new parity on the flash chip of the second flash package, from the second flash package to the RAID controller;
sending instruction for invalidating old data from the RAID controller to the first flash package based on the complete information; and
invalidating the old data based on the instruction.
18. The storage system according to claim 17,
wherein each of the plurality of flash chips of the first flash package includes a plurality of physical pages to store data or parity, and the first device controller has a page mapping management table which relates physical pages to logical pages,
wherein the first device controller has related a first logical page to a first physical page, which has stored old data, on the page mapping management table, and
wherein the first device controller is configured to perform steps of:
relating a second physical page, in which the new data are stored and which is different from the first physical page, to the first logical page while keeping on relating the first physical page to the first logical page on the page mapping management table, when the first device controller stores the new data on the first flash package; and

deleting a piece of information of the first physical page from the page mapping management table for invalidating the old data.
19. The storage system according to claim 18,
wherein the first device controller is configured to perform a step of:
deleting the old data after deleting the piece of information of the first physical page from the page mapping management table.
20. The storage system according to claim 17,
wherein the second device controller is configured to perform steps of:
sending complete information of storing first new parity to the RAID controller after storing the first new parity on the flash chip of the second flash package;

wherein when the RAID controller does not receive the complete information in a predetermined time from the second flash package, the storage system is configured to perform steps of:
generating second intermediate parity based on the old data and the new data by the first device controller;
transferring the second intermediate parity from the first device controller to the second device controller; and
generating second new parity based on the second intermediate parity and the old parity by the second device controller.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An organic light emitting diode (OLED) display comprising:
a substrate, a plurality of pixel areas being defined on the substrate;
a heating circuit structure comprising:
a first conductive line and a second conductive line not connected to each other formed on the substrate;
a first isolation layer formed on the substrate, the first isolation layer comprising a plurality of first contact holes exposing the first conductive line and the second conductive line;
a plurality of first heating wires and a plurality of second heating wires disposed on the substrate, each of the first heating wires and each of the second heating wires being electrically connected to the first conductive line and the second conductive line respectively through each of the first contact holes and covering portions of each of the pixel areas; and
a ground electrode being electrically connected to each of the first heating wires and each of the second heating wires; and
a plurality of organic light emitting diodes corresponding to each of the pixel areas.
2. The display of claim 1 wherein both the first heating wire and the second heating wire are transparent heating wires.
3. The display of claim 1 further comprising a second isolation layer covering the heating circuit structure, and each of the organic light emitting diodes is disposed on the second isolation layer.
4. The display of claim 3 wherein each of the first heating wires is used to heat the corresponding organic light emitting diodes to allow the organic light emitting diodes above each of the first heating wires to emit green light, and each of the second heating wires is used to heat the corresponding organic light emitting diodes to allow the organic light emitting diodes above each of the second heating wires to emit red light.
5. The display of claim 4 wherein each of the organic light emitting diodes which are not heated emits blue light.
6. The display of claim 1 wherein the organic light emitting diodes are disposed underneath the first isolation layer.
7. The display of claim 6 wherein each of the first heating wires is used to heat the corresponding organic light emitting diodes to allow the organic light emitting diodes underneath each of the first heating wires to emit green light, and each of the second heating wires is used to heat the corresponding organic light emitting diodes to allow the organic light emitting diodes underneath each of the second heating wires to emit red light.
8. The display of claim 7 wherein each of the organic light emitting diodes which are not heated emits blue light.
9. The display of claim 1 wherein each organic light emitting diode comprises:
a transparent electrode, the transparent electrode is used as an anode;
an organic thin film formed on the transparent electrode; and
a metal layer formed on the organic thin film, the metal layer is used as a cathode.
10. The display of claim 1 wherein the ground electrode is a transparent ground electrode, wherein a width of the ground electrode is greater than widths of the first conductive line and the second conductive line.
11. An organic light emitting diode (OLED) display comprising:
a substrate, a plurality of pixel areas being defined on the substrate, a diode region and a thin film transistor (TFT) region being defined in each of the pixel areas;
a plurality of first heating wires and a plurality of second heating wires disposed on the substrate, each of the first heating wires and each of the second heating wires covering portions of each of the pixel areas;
a thin film transistor disposed on each of the heating wires in each of the thin film transistor regions;
an isolation layer formed on the substrate, and the isolation layer covering each of the thin film transistors and each of the heating wires; and
an organic light emitting diode disposed on the isolation layer in each of the diode regions;
wherein each of the first heating wires is electrically connected to the first conductive wire to heat the corresponding organic light emitting diodes to emit green light, and each of the second heating wires is electrically connected to the second conductive wire to heat the corresponding organic light emitting diodes to emit red light.
12. The display of claim 11 wherein both the first heating wire and the second heating wire are transparent heating wires.
13. The display of claim 11 wherein each of the organic light emitting diodes which are not heated emits blue light.
14. The display of claim 11 wherein a buffer layer is included between each of the thin film transistors and each of the heating wires, and the buffer layer is composed of silicon oxide.
15. The display of claim 11 wherein the isolation layer is composed of silicon oxide, and a thickness of the isolation layer is approximately equal to 1000 angstroms (\u212b).
16. The display of claim 11 wherein each organic light emitting diode comprises:
a transparent electrode formed on the isolation layer, the transparent electrode is used as an anode;
an organic thin film formed on the transparent electrode; and
a metal layer formed on the organic thin film, the metal layer is used as an cathode.
17. The display of claim 16 wherein the transparent electrode is a pixel electrode of the thin film transistor.
18. The display of claim 11 wherein the first conductive line and the second conductive line are not connected to each other.
19. The display of claim 11 further comprising a ground electrode electrically connected to each of the first heating wires and each of the second heating wires.
20. The display of claim 19 wherein the ground electrode is a transparent ground electrode, wherein a width of the ground electrode is greater than widths of the first conductive line and the second conductive line.
21. An organic light emitting diode (OLED) display comprising:
a substrate;
a plurality of pixel areas being defined on the substrate;
a plurality of organic light emitting diodes, each of the organic light emitting diodes corresponding to each of the pixel areas designed to emit a light beam of a predetermined color when unheated; and
a heating circuit for heating selected organic light emitting diodes so as to enable the selected light emitting diodes to emit light beams of a color different from the predetermined color.