Author: claimsbot

1. A method for manufacturing a semiconductor device comprising:
alternately supplying a silicon source and an oxidant to deposit a silicon oxide film on a surface of a semiconductor substrate,
wherein the silicon source is supplied under a supply condition where an adsorption amount of molecules of the silicon source on the semiconductor substrate is increased without causing an adsorption saturation of the molecules of the silicon source on the semiconductor substrate, and
wherein the oxidant is supplied under a supply condition where impurities remain in the molecules of the silicon source adsorbed on the semiconductor substrate.
2. The method for manufacturing a semiconductor device according to claim 1, wherein a silicon oxynitride film containing nitrogen is deposited as the silicon oxide film by using a nitrogen-containing silicon source as the silicon source.
3. The method for manufacturing a semiconductor device according to claim 1, wherein the silicon source is supplied under a supply condition where a temperature of the semiconductor substrate is higher than a temperature of the semiconductor substrate in an ALD method.
4. The method for manufacturing a semiconductor device according to claim 3, wherein the temperature of the semiconductor substrate is 300\xb0 C. to 600\xb0 C.
5. The method for manufacturing a semiconductor device according to claim 1, wherein the silicon source is supplied under a supply condition where a supply amount of the silicon source is greater than a supply amount of the silicon source in an ALD method.
6. The method for manufacturing a semiconductor device according to claim 1, wherein the silicon source is supplied under a supply condition where a supply pressure of the silicon source is higher than a supply pressure of the silicon source in an ALD method.
7. The method for manufacturing a semiconductor device according to claim 1, wherein the silicon source is supplied under a supply condition where a supply time of the silicon source is longer than a supply time of the silicon source in an ALD method.
8. The method for manufacturing a semiconductor device according to claim 1, wherein the oxidant is supplied under a supply condition where a supply of the oxidant is stopped at a condition where the impurities are remaining.
9. The method for manufacturing a semiconductor device according to claim 1, wherein a supply time of the oxidant is set shorter than a supply time of the silicon source in each cycle of the alternate supply of the silicon source and the oxidant.
10. The method for manufacturing a semiconductor device according to claim 1, wherein an oxygensilicon composition ratio of the silicon oxide film is 2.00 to 2.05.
11. The method for manufacturing a semiconductor device according to claim 2, wherein the silicon oxynitride film contains 0.1 to 5.0 at. % of nitrogen.
12. The method for manufacturing a semiconductor device according to claim 2, wherein the nitrogen-containing silicon source is an aminosilane type silicon source.
13. The method for manufacturing a semiconductor device according to claim 1, wherein the supply of the silicon source and the supply of the oxidant are repeated.
14. A method for manufacturing a semiconductor device comprising:
alternately supplying a silicon source and an oxidant to deposit a silicon oxide film on a surface of a semiconductor substrate,
wherein the silicon source is supplied under a supply condition where a supply time of the oxidant is set shorter than a supply time of the silicon source in each cycle of an alternate supply of the silicon source and the oxidant.
15. A semiconductor device comprising;
at least one of a tunnel insulating film, an inter-poly insulating film, a block insulating film, a side wall insulating film, and a gate insulating film as an insulating film,
wherein the at least one of the insulating film is formed with a silicon oxide film deposited by alternately supplying a silicon source and an oxidant, an oxygensilicon composition ratio of the silicon oxide film being 2.00 to 2.05.
16. The semiconductor device according to claim 15, wherein a silicon oxynitride film containing 0.1 to 5.0 at. % of nitrogen is used as the silicon oxide film.
17. The semiconductor device according to claim 15, wherein the tunnel isolation film has a multilayer structure formed of the silicon oxide film, a silicon nitride film, and the silicon oxide film.
18. The semiconductor device according to claim 15, wherein the semiconductor device is a MONOS type nonvolatile semiconductor memory device, and the tunnel insulating film, the block insulating film, and the side wall insulating film are a tunnel insulating film, a block insulating film, and a side wall insulating film of the MONOS type nonvolatile semiconductor memory device, respectively.
19. The semiconductor device according to claim 15, wherein the semiconductor device is an FG type nonvolatile semiconductor memory device, and the tunnel insulating film, the inter-poly insulating film, and the side wall insulating film are a tunnel insulating film, a inter-poly insulating film, and a side wall insulating film of the FG type nonvolatile semiconductor memory device, respectively.
20. The semiconductor device according to claim 15, wherein the semiconductor device is a MOS transistor, and the gate insulating film is a gate insulating film of the MOS transistor.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A method of manufacturing a semiconductor integrated circuit device, comprising:
forming a first mask exposing a first area of a main surface of a semiconductor substrate of a first conductivity type;
introducing a first impurity in said first area by using said first mask to form a first semiconductor region of a second conductivity type opposed to said first conductivity type in said semiconductor substrate;
introducing a second impurity in said first area by using said first mask to form a second semiconductor region of said first conductivity type in said semiconductor substrate such that said first semiconductor region is formed under said second semiconductor region;
selectively introducing a third impurity in a second area within said first area to form a third semiconductor region, serving as a well region, of said second conductivity type in said second semiconductor region;
selectively introducing a fourth impurity in a third area within said first area to form a fourth semiconductor region, serving as a well region, of said first conductivity type in said second semiconductor region;
forming a first MISFET on said third semiconductor region; and
forming a second MISFET on said fourth semiconductor region.
2. A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a width of an element isolation region formed in said first area is less than a width of an element isolation region formed in another area.
3. A method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein said first area is a cache memory forming region.
4. A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said first area is a cache memory forming region.
5. A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said first and second conductivity types are p-type and n-type conductivities, respectively, wherein said first MISFET is a p-channel MISFET, wherein said second MISFET is an n-channel MISFET, and wherein said third semiconductor region and said fourth semiconductor region are an n-well region and a p-well region, respectively.
6. A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein in said selectively introducing said third impurity, said third impurity is introduced in a fourth area located separately from said first area to form a fifth semiconductor region, serving as a well region, of said second conductivity type in said substrate,
wherein in selectively introducing said fourth impurity, said fourth impurity is introduced in a fifth area located separately from said first area and said fourth area to form a sixth semiconductor region, serving as a well region, of said first conductivity type in said substrate,
wherein said first mask covers said fourth area, and
wherein a third MISFET and a fourth MISFET are formed on said fifth semiconductor region and said sixth semiconductor region, respectively.
7. A method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein a width of an element isolation region formed in said first area is less than a width of an element isolation region formed in said fourth area and said fifth area.
8. A method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein said first mask exposes said fifth area, and wherein said first impurity and said second impurity are introduced in said fifth area.
9. A method of manufacturing a semiconductor integrated circuit device, comprising:
forming a first mask exposing a first area of a main surface of a semiconductor substrate of a first conductivity type and exposing a second area located separately from said first area;
introducing a first impurity in said first area by using said first mask to form a first semiconductor region of a second conductivity type opposite to said first conductivity type in said substrate, wherein said first impurity is introduced in said second area by using said first mask to form a second semiconductor region of said second semiconductor region of said second conductivity type in said substrate;
introducing a second impurity in said first area by using said first mask to form a third semiconductor region of said first conductivity type in said semiconductor substrate such that said first semiconductor region is formed under said third semiconductor region, wherein said second impurity is introduced in said second area by using said first mask to form a fourth semiconductor region, serving as a well region, of said first conductivity type in said semiconductor substrate such that said fourth semiconductor region is formed under said second semiconductor region;
selectively introducing a third impurity in a third area within said first area to form a fifth semiconductor region, serving as a well region, of said second conductivity type in said third semiconductor region; and
selectively introducing a fourth impurity in a fourth area within said first area to form a sixth semiconductor region, serving as a well region, of said first conductivity type in said third semiconductor region,
wherein said third impurity and said fourth impurity are not introduced in said second area,
wherein a first MISFET is formed on said fifth semiconductor region,
wherein a second MISFET is formed on said sixth semiconductor region, and
wherein a third MISFET is formed on said fourth semiconductor region.
10. A method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein a width of an element isolation region formed in said first area is less than a width of an element isolation region formed in said second area.
11. A method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein said third MISFET is a MISFET for high breakdown voltage system.
12. A method of manufacturing semiconductor integrated circuit device according to claim 9, wherein said first conductivity type and said second conductivity type are p-type conductivity and n-type conductivity, respectively, wherein said first MISFET is a p-channel MISFET, wherein said second and third MISFETs are n-channel MISFETs, wherein said fourth semiconductor region and said sixth semiconductor region are p-well regions, and wherein said fifth semiconductor region is an n-well region.
13. A method of manufacturing a semiconductor integrated circuit device according to claim 9, further comprising:
forming a second mask exposing a fifth area located separately from said first area; and
introducing a fifth impurity in said fifth area by using said second mask to form a seventh semiconductor region, serving as a well region, of said second impurity conductivity type,
wherein said third impurity and said fourth impurity are not introduced in said fifth area,
wherein said seventh semiconductor region has an impurity concentration lower than that of said fifth semiconductor region,
wherein a fourth MISFET is formed on said seventh semiconductor region, and
wherein each of said third MISFET and said fourth MISFET is a MISFET for high breakdown voltage system.
14. A method of manufacturing a semiconductor integrated circuit device according to claim 13, wherein said seventh semiconductor region is formed to surround the outer periphery of said fourth semiconductor region.
15. A method of manufacturing a semiconductor integrated circuit device, comprising:
forming a first mask exposing a first area of a main surface of a semiconductor substrate of a first conductivity type;
introducing a first impurity in said first area by using said first mask to form a first semiconductor region of a second conductivity type opposed to said first conductivity type in said semiconductor substrate;
introducing a second impurity in said first area by using said first mask to form a second semiconductor region of said first conductivity type in said semiconductor substrate such that said first semiconductor region is formed under said second semiconductor region;
selectively introducing a third impurity in a second area within said first area to form a third semiconductor region, serving as a well region, of said second conductivity type in said second semiconductor region;
forming a first MISFET on said third semiconductor region; and
forming a second MISFET on said first area except said second area of said second semiconductor region.
16. A method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein a width of an element isolation region formed in said first area is less than a width of an element isolation region formed in another area.
17. A method of manufacturing a semiconductor integrated circuit device according to claim 16, wherein said first area is a cache memory forming region.
18. A method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein said first area is a cache memory forming region.
19. A method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein said first conductivity type and said second conductivity type are p-type conductivity and n-type conductivity, respectively, wherein said first MISFET is a p-channel MISFET, and wherein said second MISFET is an n-channel MISFET.
20. A method of manufacturing a semiconductor integrated circuit device, comprising:
forming a first mask exposing a first area of a main surface of a semiconductor substrate of a first conductivity type;
introducing a first impurity in said first area by using said first mask to form a first semiconductor region of a second conductivity type opposed to said first conductivity type in said semiconductor substrate;
introducing a second impurity in said first area by using said first mask to form a second semiconductor region of said first conductivity type in said semiconductor substrate such that said first semiconductor region is formed under said second semiconductor region;
selectively introducing a third impurity in a second area within said first area to form a third semiconductor region, serving as a well region, of said second conductivity type in said second semiconductor region, wherein said third impurity is introduced in a third area located separately from said first area to form a fourth semiconductor region, serving as a well region, of said second conductivity type in said substrate, and wherein said first mask covers said third area;
forming a first MISFET on said third semiconductor region;
forming a second MISFET on said first area except said second area of said second semiconductor region; and
forming a third MISFET on said fourth semiconductor region.
21. A method of manufacturing a semiconductor integrated circuit device according to claim 20, wherein a width of an element isolation region formed in said first area is less than a width of an element isolation region formed in said third area.
22. A method of manufacturing a semiconductor integrated circuit device according to claim 21, wherein said first area is a cache memory forming region.
23. A method of manufacturing a semiconductor integrated circuit device according to claim 20, wherein said first area is a cache memory forming region.
24. A method of manufacturing a semiconductor integrated circuit device according to claim 20, wherein said first conductivity type and said second conductivity type are p-type conductivity and n-type conductivity, respectively, wherein said first MISFET and said third MISFET are p-channel MISFETs, and wherein said second MISFET is an n-channel MISFET.
25. A method of manufacturing a semiconductor integrated circuit device according to claim 20, wherein said fourth semiconductor region is formed to surround the outer periphery of said second semiconductor region.
26. A method of manufacturing a semiconductor integrated circuit device according to claim 20, wherein said first mask exposes a fourth area located separately from said first area,
wherein said first impurity is introduced in said fourth area to form a fifth semiconductor region of said second conductivity type in said substrate,
wherein said second impurity is introduced in said fourth area to form a sixth semiconductor region, serving as a well region, of said first conductivity type such that said fifth semiconductor region is formed below said sixth semiconductor region,
wherein a fourth MISFET is formed on said sixth semiconductor region, and
wherein said fourth semiconductor region is formed to surround the outer periphery of said sixth semiconductor region.
27. A method of manufacturing a semiconductor integrated circuit device according to claim 20, further comprising:
forming a third mask exposing said second area and said third area; and
introducing a sixth impurity in said second area and said third area by using said third mask to form a seventh semiconductor region of said second conductivity type in said second semiconductor region and to form an eighth semiconductor region of said second conductivity type in said fourth semiconductor region,
wherein said seventh semiconductor region and said eighth semiconductor region extend under said second semiconductor region and said fourth semiconductor region, respectively.
28. A method of manufacturing a semiconductor integrated circuit device, comprising:
forming a first mask exposing a first area of a main surface of a semiconductor substrate of a first conductivity type and exposing a second area located separately from said first area;
introducing a first impurity in said first area by using said first mask to form a first semiconductor region of a second conductivity type opposed to said first conductivity type in said substrate, wherein said first impurity is introduced in said second area by using said first mask to form a second semiconductor region of said second conductivity type in said substrate;
introducing a second impurity in said first area by using said first mask to form a third semiconductor region of said first conductivity type in said semiconductor substrate such that said first semiconductor region is formed under said third semiconductor region, wherein said second impurity is introduced in said second area by using said first mask to form a fourth semiconductor region, serving as a well region, of said first conductivity type in said semiconductor substrate such that said fourth semiconductor region is formed under said second semiconductor region; and
selectively introducing a third impurity in a third area within said first area to form a fifth semiconductor region, serving as a well region, of said second conductivity type in said third semiconductor region,
wherein said third impurity is not introduced in said second area,
wherein a first MISFET is formed on said fifth semiconductor region,
wherein a second MISFET is formed on said first area except said second area, and
wherein a third MISFET is formed on said fourth semiconductor region.
29. A method of manufacturing a semiconductor integrated circuit device according to claim 28, wherein a width of an element isolation region formed in said first area is less than a width of an element isolation region formed in said second area.
30. A method of manufacturing a semiconductor integrated circuit device according to claim 28, wherein said third MISFET is a MISFET for high breakdown voltage system.
31. A method of manufacturing a semiconductor integrated circuit device according to claim 28, wherein said first conductivity type and said second conductivity type are p-type conductivity and n-type conductivity, respectively, wherein said first MISFET is a p-channel MISFET, wherein said second and third MISFETs are n-channel MISFETs, wherein said fourth semiconductor region is a p-well region, and wherein said fifth semiconductor region is an n-well region.
32. A method of manufacturing a semiconductor integrated circuit device according to claim 28, further comprising:
forming a second mask exposing a fourth area located separately from said first area; and
introducing a fourth impurity in said fourth area using said second mask, to form a sixth semiconductor region, serving as a well region, of said second conductivity type,
wherein said sixth semiconductor region has an impurity concentration lower than that of said fifth semiconductor region, and
wherein a fourth MISFET for high breakdown voltage system is formed on said sixth semiconductor region.
33. A method of manufacturing a semiconductor integrated circuit device according to claim 32, wherein said sixth semiconductor region is formed to surround the outer periphery of said fourth semiconductor region.

1. A system for producing a copolymer of isoprene comprising: (a) an isoprene starting composition derived from renewable resources; and (b) a polymer produced from at least a portion of the isoprene starting material; wherein at least a portion of the isoprene starting composition undergoes polymerization with another non-isoprene molecule to produce a copolymer.
2. The system of claim 1, wherein the isoprene starting composition derived from renewable resources comprises greater than about 2 mg of isoprene and comprises greater than or about 99.94% isoprene by weight compared to the total weight of all C5 hydrocarbons in the composition.
3. The system of claim 1, wherein the isoprene starting composition derived from renewable resources comprises greater than about 2 mg of isoprene and comprises one or more compounds selected from the group consisting of ethanol, acetone, C5 prenyl alcohols, and isoprenoid compounds with 10 or more carbon atoms.
4. The system of claim 1, wherein the isoprene starting composition derived from renewable resources comprises greater than about 2 mg of isoprene and comprises one or more second compounds selected from the group consisting of ethanol, acetone, methanol, acetaldehyde, methacrolein, methyl vinyl ketone, 2-methyl-2-vinyloxirane, cis- and trans-3-methyl-1,3-pentadiene, a C5 prenyl alcohol, 2-heptanone, 6-methyl-5-hepten-2-one, 2,4,5-trimethylpyridine, 2,3,5-trimethylpyrazine, citronellal, acetaldehyde, methanethiol, methyl acetate, 1-propanol, diacetyl, 2-butanone, 2-methyl-3-buten-2-ol, ethyl acetate, 2-methyl-1-propanol, 3-methyl-1-butanal, 3-methyl-2-butanone, 1-butanol, 2-pentanone, 3-methyl-1-butanol, ethyl isobutyrate, 3-methyl-2-butenal, butyl acetate, 3-methylbutyl acetate, 3-methyl-3-buten-1-yl acetate, 3-methyl-2-buten-1-yl acetate, (E)-3,7-dimethyl-1,3,6-octatriene, (Z)-3,7-dimethyl-1,3,6-octatriene, and 2,3-cycloheptenolpyridine; wherein the amount of the second compound relative to the amount of the isoprene is greater than or about 0.01% (ww).
5. The system of claim 1, wherein the isoprene starting composition derived from renewable resources comprises greater than about 2 mg of isoprene and comprises less than or about 0.5 \u03bcgL per compound for any compound in the composition that inhibits the polymerization of isoprene.
6. The system of claim 1 wherein the polymer produced from the isoprene starting material is a polyisoprene polymer which is comprised of repeat units that are derived from isoprene monomer, wherein the polyisoprene polymer has \u03b413C value of greater than \u221222\u2030 or which is within the range of \u221230\u2030 to \u221228.5\u2030.
7. The system of claim 1 wherein the polymer produced from the isoprene starting material is a polymer which is comprised of repeat units that are derived from isoprene monomer and at least one additional monomer, wherein the polymer includes blocks of repeat units that are derived from isoprene, and wherein the blocks of repeat units that are derived from isoprene have a \u03b413C value of greater than \u221222\u2030 or which is within the range of \u221232\u2030 to \u221224\u2030.
8. The system of claim 1 wherein the polymer produced from the isoprene starting material is a polymer which is comprised of repeat units that are derived from isoprene monomer and at least one additional monomer, wherein the polymer includes blocks of repeat units that are derived from isoprene, and wherein the blocks of repeat units that are derived from isoprene have a \u03b413C value of greater than \u221222\u2030 or which is within the range of \u221234\u2030 to \u221224\u2030.
9. The system of claim 8 wherein the polymer is a copolymer selected from the group consisted of (i) copolymers of isoprene and 1,3-butadiene, (ii) copolymers of isoprene and styrene, (iii) copolymers of isoprene, 1,3-butadiene, and styrene, and (iv) copolymers of isoprene and \u03b1-methyl styrene.
10. The system of claim 1 wherein the polymer produced from the isoprene starting material is a polyisoprene polymer which is comprised of repeat units that are derived from isoprene monomer, wherein the polyisoprene polymer has fM value which is greater than 0.9.
11. The system of claim 1, further comprising one or more of: (i) a catalyst for polymerizing isoprene, (ii) a polymerization initiator, (iii) an ionic surfactant, (iv) a suitable organic solvent, and (v) a polymerization chain terminator.
12. A system for producing a polymer of isoprene comprising: (a) an isoprene starting composition derived from renewable resources; and (b) a polymer produced from at least a portion of the isoprene starting material; wherein at least a portion of the isoprene starting composition undergoes polymerization with other isoprene molecules to produce a polymer of isoprene with a molecular weight of about 5,000 to about 100,000.
13. A method for producing a copolymer of isoprene derived from renewable resources comprising: (a) culturing cells comprising a heterologous nucleic acid encoding an isoprene synthase polypeptide under suitable culture conditions for the production of the isoprene; (b) producing the isoprene; and (c) polymerizing the isoprene derived from renewable resources with another non-isoprene molecules to produce a copolymer.
14. The method of claim 13, further comprising recovering the isoprene from the isoprene-producing cell culture prior to polymerization.
15. The method of claim 13 further comprising step (d) recovering the polymer produced.
16. A method for producing a polymer of isoprene derived from renewable resources comprising: (a) culturing cells comprising a heterologous nucleic acid encoding an isoprene synthase polypeptide under suitable culture conditions for the production of the isoprene; (b) producing the isoprene; and (c) polymerizing the isoprene derived from renewable resources with other isoprene molecules to produce a polymer of isoprene with a molecular weight of about 5,000 to about 100,000.
17. A polymer of isoprene derived from renewable resources produced by the method according to claim 13.
18. A polymer of isoprene derived from renewable resources produced by the method according to claim 16.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of forming a doped portion of a semiconductor, comprising:
providing a semiconductor substrate having a surface;
defining a plurality of protruding portions on the substrate surface, the protruding portions having a minimum height;
providing a sacrificial layer above the substrate surface;
providing a pattern layer above the sacrificial layer and the substrate surface;
removing portions of the pattern layer from predetermined substrate portions;
performing an ion implantation procedure such that an angle of the ions with respect to the substrate surface is less than 90\xb0, wherein the ions are stopped by the pattern layer and by the protruding portions, the predetermined substrate portions thereby being doped with the ions; and
removing the pattern layer.
2. The method of claim 1, wherein the pattern layer is conformally deposited on the substrate surface.
3. The method of claim 1, wherein removing the portions of the pattern layer comprises:
covering predetermined portions of the pattern layer with a resist material, thereby defining uncovered portions of the pattern layer, and
anisotropic etching the pattern layer at the uncovered portions.
4. The method of claim 3, wherein the covering of predetermined portions with the resist material comprises:
providing a photoresist layer, and
photolithographically patterning the photoresist layer.
5. The method of claim 1, wherein a thickness of the pattern layer is less than the minimum height of the protruding portions.
6. The method of claim 1, wherein the pattern layer has a thickness of between 5-10 nm.
7. The method of claim 1, wherein the pattern layer comprises a material selected from the group consisting of: silicon nitride, tungsten, and TiN.
8. The method of claim 1, wherein the sacrificial layer is conformally deposited on the substrate surface.
9. The method of claim 1, wherein the thickness of the sacrificial layer is less than the minimum height of the protruding portions.
10. The method of claim 1, wherein the sacrificial layer has a thickness of between 5-30 nm.
11. The method of claim 1, wherein the sacrificial layer comprises silicon dioxide.
12. The method of claim 1, further comprising removing portions of the sacrificial layer from the predetermined substrate portions prior to performing the ion implantation.
13. The method of claim 12, wherein the thickness of the sacrificial layer is larger than the minimum height of the protruding portions.
14. The method of claim 13, further comprising removing an upper portion of the sacrificial layer.
15. The method of claim 14, wherein, after removing the upper portion of the sacrificial layer, a plane surface of the sacrificial layer is thereby obtained.
16. The method of claim 13, wherein the pattern layer includes a photoactive compound and predetermined portions of the pattern layer are removed by exposing the predetermined portions to electromagnetic radiation and dissolving the exposed portions in a suitable solvent.
17. The method of claim 12, wherein the sacrificial layer has a thickness of between 150-280 nm.
18. The method of claim 12, wherein the pattern layer has a thickness of between 50-250 nm.
19. The method of claim 18, wherein the pattern layer has a thickness of between 50-150 nm.
20. The method of claim 12, wherein the pattern layer comprises an organic compound.
21. The method of claim 20, wherein the pattern layer comprises a hydrocarbon compound comprising an additive selected from the group consisting of silicon and titanium.
22. The method of claim 21, wherein the sacrificial layer comprises a material selected from the group consisting of: an organic compound and an elementary carbon.
23. The method of claim 1, wherein defining a plurality of protruding portions includes forming a gate electrode on the substrate surface, the method further comprising:
forming a first and a second sourcedrain region in the semiconductor substrate such that a transistor is at least partially formed in the semiconductor substrate.
24. The method of claim 23, wherein the first and the second sourcedrain regions are defined via performing an ion implantation procedure that requires the pattern layer and the gate electrode to perform as an implantation mask, thereby stopping the implanted ions.
25. The method of claim 23, wherein the first and the second sourcedrain region are doped with ions having a first conductivity type and the angled ion implantation procedure is performed with ions having a second conductivity type, the second conductivity type being opposite to the first conductivity type.