Author: claimsbot

1: Solar multistage concentrator, wherein
at least one imaging lens is provided upstream of a non-imaging lens, in such a manner that both lenses are integral parts of a specifically formed, light-transparent dielectric medium.
2: Solar multistage concentrator according to claim 1,
wherein
the imaging lens comprises a spherical calotte, which connects to a wedge-shaped non-imaging lens.
3: Solar multistage concentrator according to claim 1,
, wherein
the primary imaging lens guides the direct sunlight incident perpendicular to its entry aperture inside the transparent dielectric medium, without total internal reflection at the edges with the air, directly into the depth of the system, where it concentrates said sunlight.
4: Solar multistage concentrator according to claim 1, wherein
in the area in which the focal zone of the first lens is formed, the subsequent shape of the second stage takes the form of a non-imaging lens, which guides the pre-concentrated light further into the depth of the system by total internal reflection at its edges with the air.
5: Solar multistage concentrator according to claim 1, wherein
the non-imaging lens is designed in such a way that it re-concentrates the sunlight concentrated by the first stage with spherical aberration, and pre-homogenizes said light in respect of the spherical and the chromatic aberration.
6: Solar multistage concentrator according to claim 1, wherein
in a third optical arrangement, integrally connected to the second stage, the concentrated light is re-homogenized by total reflection at the boundary surfaces between dielectric medium and air with respect to the energy density and chromatic distribution thereof, and the shape of the emission area of the third stage is matched to that of the so-called solar receiver.
7: Solar multistage concentrator according to claim 1, wherein
the solar receiver consists of a photovoltaic concentration cell, which is fixed directly and in a lossless manner onto the emission aperture of the last stage of the arrangement by means of an optical immersion medium.
8: Solar multistage concentrator according to claim 6, wherein
the rear side of the solar cell is cooled by a fluid, which runs through a thin transparent polymer tube, which is pressed mechanically against the solar cell.
9: Solar multistage concentrator according to claim 1, wherein
the concentrated sunlight diverges in a directed manner into an optically coupled transparent double plate after leaving through the end aperture.
10: Solar multistage concentrator according to claim 1, wherein
a transparent optical cooling fluid flows through the double plate, and wherein
at an appropriate distance from the diverging bundle of rays, a concentrator solar cell is located in this fluid.
11: Solar multistage concentrator according to claim 1, wherein
the solar cell ends in a metallic support with good thermal conductivity on the reverse side of the plate, which is assembled as an electronic printed circuit, and guides the current flow from the cell into this electronic circuit.
12: Solar multistage concentrator according to claim 1, wherein
the first stage consists of an imaging lens which deviates from spherical form in an arbitrary way, and wherein the downstream stage(s) isare constructed as non-imaging concentrators or homogenizers, respectively, in such a way that the solar receiver used receives the concentrated sunlight in the desired energy density distribution on the entry aperture thereof which is optically directly coupled into the end stage.
13: Solar multistage concentrator according to claim 1, wherein
the sunlight is either concentrated one-dimensionally in focal lines or two-dimensionally in focal points, wherein in the first case a uniaxial and in the second case a biaxial solar tracking system is required.
14: Solar multistage concentrator according to claim 1, wherein
up to a specific range, angular deviations in the solar tracking system are compensated by the non-imaging stages reflecting the resulting inclined solar radiation paths back into the arrangement.
15: Solar multistage concentrator according to claim 1, wherein
the diffuse component of the sunlight radiates through the lateral flanks of the arrangement into the space thereunder.
16: Solar multistage concentrator according to claim 1, wherein multiple concentrators are combined to discs.
17: Solar multistage concentrator according to claim 1, wherein
the one-dimensional or two-dimensional imaging discs, located behind transparent covers such as windows, facade roofs or greenhouse shells, convert the direct solar radiation into useful energy (electricity, chemical energy or heat), whereas the diffuse sunlight is used for illuminating the areas behind or under the arrangement.
18: Solar multistage concentrator according to claim 1, wherein
the lenses are made of highly transparent optical materials, of as high a refractive index as possible, that are non-reflective at the entry and emission apertures, and wherein the total internal reflections occur at the boundary surface between the optical material and air.
19: Solar multistage concentrator according to claim 1, wherein
the lenses consist of transparent hollow bodies, which are likewise filled with highly transparent optical fluids.
20: Solar multistage concentrator according to claim 1, wherein
the transparent walls consist of fluoropolymers with a low refractive index, and the fluid, e.g. silicone oil, has a high refractive index, so that total internal reflection takes place at the boundary between the oil and fluoropolymer.
21: Solar multistage concentrator according to claim 1, wherein
the walls consist of fluoropolymers and the fluid, typically a fluoric liquid or water, also has a low refractive index, so that total internal reflection occurs at the boundary between the cover and air.
22: Greenhouse with a solar multistage concentrator according to claim 1, in particular with a plurality of such solar multistage concentrators.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A buckle having a plug member and a socket member which are detachably coupled to each other,
wherein the plug member having a base part, a pair of lock arms which project from the base part to be elastically coupled to the socket member, a guide rod which projects from the base part between the pair of lock arms, and bridges which extend from the base part inside the pair of lock arms and are connected to distal ends or middle portions of inner surfaces of the lock arms, and
wherein the socket member have a chamber which is defined by an upper plate, a lower plate and sidewalls connecting the upper and lower plates and is open at a distal end thereof to receive the pair of lock arms and the guide rod, and engagement parts which are formed outside the chamber to allow distal end portions of the lock arms to be engaged therewith,
wherein a slot is defined in the guide rod in a lengthwise direction of the guide rod, and a guide rib to be fitted into the slot of the guide rod is formed in the chamber of the socket member in such a way as to connect the upper and lower plates,
wherein the slot is defined to a middle portion of the guide rod, a connecting part is formed to extend from the middle portion of the guide rod to the base part, and a rib groove is defined in the guide rib to receive the connecting part.
2. The buckle according to claim 1, wherein each bridge is formed with one or at least two bending portions on an intermediate portion thereof.
3. The buckle according to claim 1, wherein each bridge is formed in such a way as to define a curved surface.
4. The buckle according to claim 1, wherein each bridge is formed of a flexible material.
5. The buckle according to claim 1, wherein the guide rod of the plug member is formed between the lock arms to be shorter than the lock arms.
6. The buckle according to claim 1, wherein openings are defined on the sidewalls of the socket member which connect the upper and lower plates such that the engagement parts are formed through molding and outer surfaces of the distal end portions of the lock arms are exposed through the openings.
7. The buckle according to claim 1, wherein a space part is defined in a rear part of the socket member to communicate with the chamber defined in the socket member and has indents which are defined in the upper and lower plates so that the space part can be enlarged forward into the socket member.
8. The buckle according to claim 7, wherein the indents are defined to have the sectional shape of a \u2018V\u2019 which gradually decreases in a width thereof toward a center portion of the socket member.
9. The buckle according to claim 7, wherein the indents are defined to have the sectional shape of a \u2018Y\u2019 which gradually decreases in a width thereof toward a center portion of the socket member.
10. The buckle according to claim 1, wherein the guide rod of the plug member extends from the base part to be shorter than the lock arms, a slot is defined from a distal end of the guide rod in the lengthwise direction of the guide rod, a guide rib to be fitted into the slot of the guide rod is formed in the chamber of the socket member in such a way as to connect the upper and lower plates, and a space part is defined in a rear part of the socket member to communicate with the chamber and has indents which are defined in the upper and lower plates so that the space part can be enlarged forward to a portion where the distal end of the guide rod is positioned when the plug member is coupled to the socket member.
11. The buckle according to claim 10, wherein each of the indents forms an inclined section which gradually decreases in width from the space part and a straight section which is formed from a middle portion of the indent.

1. An electrostatic discharge (ESD)-triggered protection apparatus, comprising:
an ESD trigger circuit to sense an ESD pulse and to generate a switching pulse responsive to the ESD pulse;
an ESD discharge device communicatively coupled to the ESD trigger circuit and responsive to the switching pulse to transfer a current generated by the ESD pulse to ground, the ESD discharge device comprising a MOS power transistor; and
a VDD turn-on clamp communicatively coupled to the ESD discharge device to prevent the ESD discharge device from switching to a conduction state during a VDD power-on event the VDD turn-on clamp further comprising:
a VDD turn-on clamp transistor to prevent conduction of the MOS power transistor at times other than the occurrence of an ESD event, a current channel of the VDD turn-on clamp transistor coupled between a gate of the MOS power transistor and ground;
a pull-up resistor coupled between the VDD voltage rail and a gate of the VDD turn-on clamp transistor to bias the VDD turn-on clamp transistor to a conductive state at VDD power-on; and
a clamp release transistor to disable the VDD turn-on clamp transistor upon the occurrence of an ESD event, a current channel of the clamp release transistor coupled between the gate of the VDD turn-on clamp transistor and ground, a gate of the clamp release transistor coupled to the gate of the MOS power transistor to drive the clamp release transistor to conduction at an occurrence of an ESD event.
2. The ESD-triggered protection apparatus of claim 1, further comprising:
an ESD discharge timer communicatively coupled to the ESD discharge device to determine a conduction period associated with the ESD discharge device.
3. The ESD-triggered protection apparatus of claim 2, the ESD discharge timer further comprising:
a gate-to-body capacitance of the MOS power transistor; and
a timer resistor coupled between a gate of the MOS power transistor and ground, a resistance value of the timer resistor selected to obtain a time constant sufficient to substantially discharge energy associated with the ESD pulse as current flow through the MOS power transistor to ground.
4. The ESD-triggered protection apparatus of claim 3, the timer resistor implemented as a long, narrow conduction channel associated with an inverting buffer transistor.
5. The ESD-triggered protection apparatus of claim 1, further comprising:
at least one inverting buffer communicatively coupled between the ESD trigger circuit and the ESD discharge device to propagate the switching pulse from the ESD trigger circuit to the ESD discharge device.
6. The ESD-triggered protection apparatus of claim 5, the at least one inverting buffer further comprising:
first, second, and third inverters, each inverter comprising a PMOS transistor coupled to a VDD voltage rail and an NMOS transistor coupled to ground, the NMOS transistor associated with the third inverter having a long, narrow-width channel to provide resistance characteristics.
7. The ESD-triggered protection apparatus of claim 1, the ESD trigger circuit further comprising:
a trigger circuit resistor coupled to a VDD voltage rail; and
a trigger circuit capacitor in series with the trigger circuit resistor to a ground rail, the switching pulse to originate at a junction of the trigger circuit resistor and the trigger circuit capacitor responsive to the ESD pulse.
8. The ESD-triggered protection apparatus of claim 1, wherein
the metal oxide semiconductor (MOS) power transistor has a current channel with a width sufficient to transfer the current generated by the ESD pulse to ground.
9. An electrostatic discharge (ESD)-triggered protection apparatus, comprising:
an ESD trigger circuit to sense an ESD pulse and to generate a switching pulse responsive to the ESD pulse;
an ESD discharge device communicatively coupled to the ESD trigger circuit and responsive to the switching pulse to transfer a current generated by the ESD pulse to ground; and
a VDD glitch clamp communicatively coupled to the ESD trigger circuit to prevent a VDD transmit-induced switching pulse from propagating to the ESD discharge device and causing the ESD discharge device to conduct, the VDD glitch clamp further comprising:
a first VDD glitch clamp transistor, a current channel of the first VDD glitch clamp transistor communicatively coupled to a path traversed by the switching pulse;
a second VDD glitch clamp transistor, a current channel of the second VDD glitch clamp transistor coupled in series between the current channel of the first VDD glitch clamp transistor and a ground rail, the first and second VDD glitch clamp transistors to clamp the path traversed by the switching pulse to ground absent an ESD pulse occurrence;
a pull-up resistor coupled between a VDD voltage rail and a gate of the first VDD glitch clamp transistor;
a VDD glitch clamp capacitor coupled between the gate of the first VDD glitch clamp transistor and the ground rail to maintain the first VDD glitch clamp transistor in a conductive state during a transient power supply disruption; and
a capacitor associated with the ESD trigger circuit communicatively coupled to a gate of the second VDD glitch clamp transistor to maintain the second VDD glitch clamp transistor in a conductive state during the transient power supply disruption.
10. The ESD-triggered protection apparatus of claim 9, further comprising:
an ESD discharge timer communicatively coupled to the ESD discharge device to determine a conduction period associated with the ESD discharge device.
11. The ESD-triggered protection apparatus of claim 9, further including:
at least one inverting buffer communicatively coupled between the ESD trigger circuit and the ESD discharge device to propagate the switching pulse from the ESD trigger circuit to the ESD discharge device.
12. An electrostatic discharge (ESD)-triggered protection apparatus, comprising:
an ESD trigger circuit to sense an ESD pulse and to generate a switching pulse responsive to the ESD pulse;
an ESD discharge device communicatively coupled to the ESD trigger circuit and responsive to the switching pulse to transfer a current generated by the ESD pulse to ground;
at least one inverting buffer communicatively coupled between the ESD trigger circuit and the ESD discharge device to propagate the switching pulse from the ESD trigger circuit to the ESD discharge device;
an ESD discharge timer communicatively coupled to the ESD discharge device to determine a conduction period associated with the ESD discharge device;
a VDD turn-on clamp communicatively coupled to the ESD discharge device to prevent the ESD discharge device from switching to a conduction state during a VDD power-on event;
a VDD glitch clamp communicatively coupled to the ESD trigger circuit to prevent a VDD transmit-induced switching pulse from propagating to the ESD discharge device and causing the ESD discharge device to conduct, the VDD glitch clamp further comprising:
a first VDD glitch clamp transistor, a current channel of the first VDD glitch clamp transistor communicatively coupled to a path traversed by the switching pulse;
a second VDD glitch clamp transistor, a current channel of the second VDD glitch clamp transistor coupled in series between the current channel of the first VDD glitch clamp transistor and ground, the first and second VDD glitch clamp transistors to clamp the path traversed by the switching pulse to ground absent an ESD pulse occurrence;
a pull-up resistor coupled between a VDD voltage rail and a gate of the first VDD glitch clamp transistor;
a VDD glitch clamp capacitor coupled between the gate of the first VDD glitch clamp transistor and the ground rail to maintain the first VDD glitch clamp transistor in a conductive state during a transient power supply disruption; and
a capacitor associated with the ESD trigger circuit communicatively coupled to a gate of the second VDD glitch clamp transistor to maintain the second VDD glitch clamp transistor in a conductive state during a transient power supply disruption.
13. The ESD-triggered protection apparatus of claim 12, the VDD glitch clamp capacitor comprising a gate-to-source internal capacitance associated with the VDD turn-on clamp transistor.
14. The ESD-triggered protection apparatus of claim 12, the ESD trigger circuit further comprising:
a trigger circuit resistor coupled to a VDD voltage rail; and
a trigger circuit capacitor in series with the trigger circuit resistor to a ground rail, the switching pulse to originate at a junction of the trigger circuit resistor and the trigger circuit capacitor responsive to the ESD pulse.
15. The ESD-triggered protection apparatus of claim 12, the ESD discharge device further comprising:
a metal oxide semiconductor (MOS) power transistor having a current channel of width sufficient to transfer the current generated by the ESD pulse to ground.
16. The ESD-triggered protection apparatus of claim 12, the ESD discharge timer further comprising:
a gate-to-body capacitance of a MOS power transistor; and
a timer resistor coupled between a gate of the MOS power transistor and ground, a resistance value of the timer resistor selected to obtain a time constant sufficient to substantially discharge energy associated with the ESD pulse as current flow through the MOS power transistor to ground.
17. The ESD-triggered protection apparatus of claim 12, the VDD turn-on clamp further comprising:
a VDD turn-on clamp transistor to prevent conduction of a MOS power transistor of the ESD discharge device at times other than the occurrence of an ESD event, a current channel of the VDD turn-on clamp transistor coupled between a gate of the MOS power transistor and ground;
the pull-up resistor coupled between the VDD voltage rail and a gate of the VDD turn-on clamp transistor to bias the VDD turn-on clamp transistor to a conductive state at VDD power-on; and
a clamp release transistor to disable the VDD turn-on clamp transistor upon the occurrence of an ESD event, a current channel of the clamp release transistor coupled between the gate of the VDD turn-on clamp transistor and ground, a gate of the clamp release transistor coupled to the gate of the MOS power transistor to drive the clamp release transistor to conduction at an occurrence of an ESD event.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An antiglare mirror, comprising:
a first electrode layer;
a second electrode layer that is optically transparent;
a dichroic material sandwiched between the first and second electrodes layers and exhibiting a high optical absorption when the first and second electrode layers are biased at a first electrical bias state and a low optical absorption when the first and second electrode layers are biased at a second, different electrical bias state, wherein the dichroic material switches between the high optical absorption and the low optical absorption in less than 0.1 second; and
a control circuit coupled to the first and second electrode layers and operable to control electrical bias between the first and second electrode layers and thus optical absorption of the dichroic material.
2. The mirror as in claim 1, wherein the control circuit further comprises a sensor which causes the first electrical bias state to be applied when light received in the mirror is greater than a threshold intensity and causes the second electrical bias state to be applied when light received in the mirror is less than the threshold intensity.
3. The mirror as in claim 2, wherein the sensor comprises one or more light detectors which are assembled behind the metal coating to measure incident light.
4. The mirror as in claim 1, wherein the second electrode layer is made of ITO.
5. The mirror as in claim 4, further comprising an additional dielectric layer between the ITO layer and the dichroic material.
6. The mirror as in claim 1, wherein the dichroic material includes a dichroic liquid crystal mixture.
7. The mirror as in claim 1, wherein the dichroic material includes a dichroic dye.
8. The mirror as in claim 1, wherein the first electrode layer is at least partially optically reflective.
9. The mirror as in claim 1, wherein the first electrical bias state is a state where a voltage is applied to the dichroic material and the second electrical bias state is a state where no voltage is applied to the dichroic material.
10. The mirror as in claim 1, wherein the second electrical bias state is a state where a voltage is applied to the dichroic material and the first electrical bias state is a state where no voltage is applied to the dichroic material.
11. A pair of eye glasses, comprising:
a first electrode layer that is optically transparent;,
a second electrode layer that is optically transparent;
a dichroic material sandwiched between the first and second electrodes layers and exhibiting a high optical absorption when the first and second electrode layers are biased at a first electrical bias state and a low optical absorption when the first and second electrode layers are biased at a second, different electrical bias state; and
a control circuit coupled to the first and second electrode layers and operable to control electrical bias between the first and second electrode layers and thus optical absorption of the dichroic material.
12. The pair of eye glasses as in claim 11, wherein the control circuit further comprises a sensor which causes the first electrical bias state to be applied when light received in the mirror is greater than a threshold intensity and causes the second electrical bias state to be applied when light received in the mirror is less than the threshold intensity.
13. The pair of eye glasses as in claim 11, wherein the first and second electrode layers are made of ITO.
14. The pair of eye glasses as in claim 11, wherein the dichroic material includes a dichroic liquid crystal mixture.
15. The pair of eye glasses as in claim 11, wherein the dichroic material includes a dichroic dye.
16. The pair of eye glasses as in claim 11, wherein the first electrical bias state is a state where a voltage is applied to the dichroic material and the second electrical bias state is a state where no voltage is applied to the dichroic material.
17. The pair of eye glasses as in claim 11, wherein the dichroic material is operable to switch between the high optical absorption and the low optical absorption in less than 0.1 second.
18. An antiglare mirror, comprising:
a first electrode layer that is at least partially transparent and a second electrode layer that is at least partially transparent;
a dichroic material sandwiched between the first and second electrodes layers and exhibiting a high optical absorption when the first and second electrode layers are biased at a first electrical bias state and a low optical absorption when the first and second electrode layers are biased at a second, different electrical bias state;
a control circuit coupled to the first and second electrode layers and operable to control electrical bias between the first and second electrode layers and thus optical absorption of the dichroic material; and
a reflective layer positioned to receive light transmitted through the first and second electrodes and the dichroic material and reflect the received light back.
19. The mirror as in claim 18, wherein the dichroic material is operable to switch between the high optical absorption and the low optical absorption in less than 0.1 second.
20. The mirror as in claim 18, wherein the dichroic material includes a dichroic dye.