Author: claimsbot

1. A method for a user equipment (UE) operating in a wireless communication system, the method comprising:
receiving, by the UE, control information including first information and second information, wherein the first information indicates one of two resource allocation types and the second information includes a bitmap indicating resource allocation; and
receiving, by the UE, the data using one or more resource blocks (RBs) allocated by the control information,
wherein, if the first information indicates a first resource allocation type of the two resource allocation types, a first bit value of the bitmap indicates whether a corresponding resource block group (RBG) is allocated or not;
if the first information indicates a second resource allocation type of the two resource allocation types, the control information includes third information indicating one of N RB sets, and a second bit value of the bitmap indicates whether a corresponding RB is allocated or not in the indicated RB set comprising a plurality of RBGs,
a size of RBG is N consecutive RBs, and N is an integer equal to or greater than 2.
2. The method according to claim 1, wherein the indicated RB set comprises every Nth RBG starting from a predetermined RBG.
3. The method according to claim 1, wherein the indicated RB set comprising a plurality of RBGs, in which neighboring RBGs are not consecutive in a frequency region.
4. The method according to claim 1, wherein indicated RB set comprises a plurality of RBGs, in which neighboring RBGs are spaced by N\u22121 RBG(s).
5. The method according to claim 1, wherein the first bit value of the bitmap indicates whether a corresponding resource block group (RBG) is allocated or not in consecutive RBGs.
6. The method according to claim 1, wherein a number of RBs in each RBG depends on a total number of RBs in a subframe.
7. The method according to claim 1, wherein a number of the RB sets is the same as a number of RBs in each RBG.
8. A user equipment (UE) operating in a wireless communication system, the UE comprising:
a radio frequency (RF) module; and
a processor configured to control the RF module,
wherein the processor is configured to receive control information including first information and second information, wherein the first information indicates one of two resource allocation types and the second information includes a bitmap indicating resource allocation, and to receive the data using one or more resource blocks (RBs) allocated by the control information,
wherein, if the first information indicates a first resource allocation type of the two resource allocation types, a first bit value of the bitmap indicates whether a corresponding resource block group (RBG) is allocated or not;
if the first information indicates a second resource allocation type of the two resource allocation types, the control information includes third information indicating one of N RB sets, and a second bit value of the bitmap indicates whether a corresponding RB is allocated or not in the indicated RB set comprising a plurality of RBGs,
a size of RBG is N consecutive RBs, and N is an integer equal to or greater than 2.
9. The UE according to claim 8, wherein the indicated RB set comprises every Nth RBG starting from a predetermined RBG.
10. The UE according to claim 8, wherein the indicated RB set comprising a plurality of RBGs, in which neighboring RBGs are not consecutive in a frequency region.
11. The UE according to claim 8, wherein indicated RB set comprises a plurality of RBGs, in which neighboring RBGs are spaced by N\u22121 RBG(s).
12. The UE according to claim 8, wherein the first bit value of the bitmap indicates whether a corresponding resource block group (RBG) is allocated or not in consecutive RBGs.
13. The UE according to claim 8, wherein a number of RBs in each RBG depends on a total number of RBs in a subframe.
14. The UE according to claim 8, wherein a number of the RB sets is the same as a number of RBs in each RBG.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A hybrid maize variety X95C359 seed, wherein representative seed is produced by crossing a first plant of variety PH1KR5 with a second plant of variety PH18T3, and wherein representative seed of said varieties PH1KR5 and PH18T3 have been deposited under ATCC Accession Number PTA-13329 and PTA-12916, respectively.
2. The hybrid maize variety X95C359 seed of claim 1, wherein a seed treatment has been applied to the seed.
3. A method of cleaning the hybrid maize variety X95C359 comprising obtaining the hybrid maize variety X95C359 seed of claim 1 and removing foreign debris from said seed.
4. An F1 plant, plant part, or plant cell produced by growing the hybrid maize variety X95C359 seed of claim 1.
5. A method of producing a commodity plant product comprising obtaining the plant or plant part of claim 4 and producing said commodity plant product therefrom.
6. A method for producing a second maize plant comprising applying plant breeding techniques to a first maize plant, or parts thereof, wherein said first maize plant is the maize plant of claim 4, and wherein application of said techniques results in the production of said second maize plant.
7. The method of claim 6 further comprising:
(a) crossing said first maize plant with itself or another maize plant to produce seed of a subsequent generation;
(b) harvesting and planting the seed of the subsequent generation to produce at least one plant of the subsequent generation; and
(c) repeating steps (a) and (b) for an additional 2-10 generations to produce a second maize plant.
8. The method of claim 6 further comprising:
(a) crossing said first maize plant with an inducer variety to produce haploid seed; and
(b) doubling the haploid seed to produce a second maize plant.
9. A converted seed of hybrid maize variety X95C359, wherein said converted seed is produced by crossing a first plant of variety PH1KR5 with a second plant of variety PH18T3; wherein representative seed of said varieties PH1KR5 and PH18T3 have been deposited under ATCC Accession Number PTA-13329 and PTA-12916, respectively; and wherein at least one of said varieties PH1KR5 and PH18T3 further comprises a locus conversion, and wherein said converted seed produces a plant having said locus conversion and otherwise having essentially the same phenotypic traits listed in Table 1 as X95C359 when grown under the same environmental conditions.
10. The converted seed hybrid maize variety X95C359 of claim 9, wherein a seed treatment has been applied to the converted seed hybrid maize variety X95C359 seed.
11. A method of cleaning the converted seed of hybrid maize variety X95C359 comprising obtaining the converted seed of claim 9 and removing foreign debris from said converted seed of hybrid maize variety X95C359.
12. The converted seed of hybrid maize variety X95C359 of claim 9, wherein the locus conversion confers a trait selected from the group consisting of male sterility, increased site-specific integration, abiotic stress tolerance, altered phosphorus, altered antioxidants, altered fatty acids, altered essential amino acids, altered carbohydrates, herbicide tolerance, insect resistance and disease resistance.
13. An F1 plant, plant part, or plant cell produced by growing the converted seed of hybrid maize variety X95C359 of claim 9.
14. A method of producing a commodity plant product comprising obtaining the plant or plant part of claim 13 and producing said commodity plant product therefrom.
15. A method for producing a second maize plant comprising applying plant breeding techniques to a first maize plant, or parts thereof, wherein said first maize plant is the maize plant of claim 13, and wherein application of said techniques results in the production of said second maize plant.
16. The method for producing a second maize plant of claim 15, further comprising:
(a) crossing said first maize plant with itself or another maize plant to produce seed of a subsequent generation;
(b) harvesting and planting the seed of the subsequent generation to produce at least one plant of the subsequent generation; and
(c) repeating steps (a) and (b) for an additional 2-10 generations to produce a second maize plant.
17. The method for producing a second maize plant of claim 15, further comprising:
(a) crossing said first maize plant with an inducer variety to produce haploid seed; and
(b) doubling the haploid seed to produce a second maize plant.

We claim:

1. An integrated circuit, comprising:
a terminal for supplying a digital signal;
a controllable driver circuit having a driver input connected to said terminal for receiving the digital signal and a driver output for outputting the digital signal;
an actuating circuit for actuating the driver circuit as a function of a clock signal, said actuating circuit having an actuating input for receiving the clock signal; and
a comparator device having:
a first comparator input for receiving the clock signal;
a second comparator input connected to said driver output for receiving the digital signal; and
a comparator output,

said comparator device outputting, from said comparator output, an output signal having:
a first state if a signal transition of the clock signal at said first comparator input takes place before a signal transition of the digital signal at said second comparator input; and
a second state if the signal transition of the clock signal at said first comparator input takes place after the signal transition of said digital signal at said second comparator input.
2. The integrated circuit according to claim 1, wherein said comparator device stores the first and second states of said output signal.
3. The integrated circuit according to claim 1, including a flipflop circuit having a first setting input, a second setting input, and a flipflop output;
said first comparator input connected to said first setting input;
said second comparator input connected to said second setting input;
said comparator output connected to said flipflop output; and
said comparator device programmed to produce the output signal indicating which of said first comparator input and said second comparator input receives a signal transition first.
4. The integrated circuit according to claim 1, including a function unit connected to said comparator output and to said actuation circuit, said function unit programmed to set a control function of said actuation circuit based upon a state of said output signal.
5. The integrated circuit according to claim 4, wherein said function unit has a self-test unit for analyzing respectively successive states of said output signal, said self-test unit programmed to incrementally set said actuation circuit based upon a result of the analysis.
6. The integrated circuit according to claim 1, wherein said actuation circuit has a control function to be set based on a reference value, and a memory unit for storing said reference value.
7. The integrated circuit according to claim 6, wherein said memory unit has programmable elements.
8. The integrated circuit according to claim 7, wherein said programmable elements are programmable fuses.
9. The integrated circuit according to claim 1, including an oscillator circuit connected to said terminal for producing the digital signal.
10. In a DRAM memory circuit, an integrated circuit comprising:
a terminal for supplying a digital signal;
a controllable driver circuit having a driver input connected to said terminal for receiving the digital signal and a driver output for outputting the digital signal;
an actuating circuit for actuating the driver circuit as a function of a clock signal, said actuating circuit having an actuating input for receiving the clock signal; and
a comparator device having:
a first comparator input for receiving the clock signal;
a second comparator input connected to said driver output for receiving the digital signal; and
a comparator output,

said comparator device outputting, from said comparator output, an output signal having:
a first state if a signal transition of the clock signal at said first comparator input takes place before a signal transition of the digital signal at said second comparator input; and
a second state if the signal transition of the clock signal at said first comparator input takes place after the signal transition of said digital signal at said second comparator input.
11. The integrated circuit according to claim 10, wherein the digital signal includes a data validity signal and a data clock signal for reading out data from the DRAM memory circuit.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A frequency multiplier comprising:
a multiphase signal generator configured to generate multiphase signals in response to a source signal;
a pulse generator configured to generate a plurality of pulse signals in response to the multiphase signals; and
a synthesizer configured to change a logic level of a frequency multiplication signal to a first logic level in response to edges of even numbered signals among the pulse signals, and change the logic level of the frequency multiplication signal to a second logic level in response to edges of odd numbered signals among the pulse signals,
wherein each of the plurality of pulse signals is generated in response to a corresponding multiphase signal.
2. The frequency multiplier according to claim 1, wherein the source signal comprises a clock signal.
3. The frequency multiplier according to claim 1, wherein the multiphase signal generator comprises:
a delay line configured to delay the source signal by a delay time adjusted in response to a delay control voltage and generate pre-multiphase signals;
a buffer configured to buffer the pre-multiphase signals and generate the multiphase signals;
a phase detector configured to detect a phase difference between two signals among the multiphase signals and generate a phase difference detection signal; and
a charge pump configured to generate the delay control voltage in response to the phase difference detection signal.
4. The frequency multiplier according to claim 3, wherein the phase detector detects a phase difference of the first signal and the last signal among the multiphase signals, and generates the phase difference detection signal.
5. The frequency multiplier according to claim 1, wherein the pulse generator is configured to sequentially respond to the multiphase signals and generate the plurality of pulse signals in which falling pulses and rising pulses are repeated.
6. The frequency multiplier according to claim 1, wherein the pulse generator comprises:
a plurality of falling pulse generation units configured to generate falling pulse signals among the plurality of pulse signals in response to even multiphase signals; and
a plurality of rising pulse generation units configured to generate rising pulse signals among the plurality of pulse signals in response to odd multiphase signals.
7. The frequency multiplier according to claim 6, wherein each of the falling pulse generation units comprises:
an inverter chain configured to receive one of the even multiphase signals and generate an inverted and delayed signal; and
a logic gate configured to receive one of the even multiphase signals and the inverted and delayed signal and generate a falling pulse signal.
8. The frequency multiplier according to claim 7, wherein the falling pulse signal has a pulse width which is set according to a signal delay time of the inverter chain.
9. The frequency multiplier according to claim 6, wherein each of the rising pulse generation units comprises:
an inverter chain configured to receive one of the odd multiphase signals and generate an inverted and delayed signal; and
a logic gate configured to receive one of the odd multiphase signals and the inverted and delayed signal and generate a rising pulse signal.
10. The frequency multiplier according to claim 9, wherein the rising pulse signal has a pulse width which is set according to a signal delay time of the inverter chain.
11. The frequency multiplier according to claim 1, wherein the synthesizer comprises:
a plurality of first switches configured to change the logic level of the frequency multiplication signal to a logic high level in response to first edges of the even numbered signals among the pulse signals; and
a plurality of second switches configured to change the logic level of the frequency multiplication signal to a logic low level in response to second edges of the odd numbered signals among the pulse signals.
12. The frequency multiplier according to claim 11, further comprising a latch configured to latch and output the level-changed frequency multiplication signal.
13. A frequency multiplier comprising:
a multiphase signal generator configured to generate even and odd multiphase signals in response to a source signal;
a falling pulse generation unit configured to generate falling pulse signals in response to the even multiphase signals;
a rising pulse generation unit configured to generate rising pulse signals in response to the odd multiphase signals; and
a synthesizer configured to change a logic level of a frequency multiplication signal to a first logic level in response to edges of the falling pulse signals, and change the logic level of the frequency multiplication signal to a second logic level in response to edges of the rising pulse signals.
14. The frequency multiplier according to claim 13, wherein the multiphase signal generator comprises a delay locked loop.
15. The frequency multiplier according to claim 13, further comprising a latch configured to latch and output the level-changed frequency multiplication signal.
16. A frequency multiplier comprising:
a multiphase generator configured to generate multiphase signals with a predetermined phase difference through a delay time compensation process in response to source signals;
a pulse generator configured to generate a plurality of pulse signals in response to the multiphase signals; and
a synthesizer configured to change a logic level of a frequency multiplication signal to a first logic level in response to falling edges of even numbered signals among the pulse signals, and change the logic level of the frequency multiplication signal to a second logic level in response to rising edges of odd numbered signals among the pulse signals.
17. The frequency multiplier of claim 16, further comprising:
a plurality of delay units configured to delay the source signals by a delay time in response to a delay control voltage.
18. The frequency multiplier of claim 17, further comprising:
a charge pump configured to perform a pumping operation to generate the delay control voltage in response to phase difference detection signals.
19. The frequency multiplier of claim 18, wherein the charge pump may be configured to compensate for a phase difference between a first signal and a last signal to allow the multiphase signals to have a constant delay time.
20. The frequency multiplier of claim 16, wherein the synthesizer is configured to generate the frequency multiplication signal by a multiplication of a frequency to a preset ratio.