1. A chopper-stabilized signal generating apparatus applied to a thin-film transistor (TFT) liquid crystal display (LCD) having a plurality of OP amplifiers, the apparatus comprising:
a sampling unit for sampling a voltage polarity control signal to obtain a sampling signal, and judging a manner of voltage transformation of a voltage polarity inversion of the voltage polarity control signal according to the sampling signal;
a control unit coupled to the sampling unit; and
a signal generating unit for generating a first chopper-stabilized signal or a second chopper-stabilized signal, selecting the first chopper-stabilized signal or the second chopper-stabilized signal as a chopper-stabilized signal, and outputting the selected chopper-stabilized signal to the OP amplifiers,
wherein when the sampling unit judges the manner of voltage transformation of the voltage polarity inversion of the voltage polarity control signal as a one-line inversion or a two-line inversion, the control unit outputs a first trigger signal, and obtains a frame transformation signal template according to the sampling signal, the signal generating unit compares the frame transformation signal template with the sampling signal to generate a frame transformation signal, and the signal generating unit generates the first chopper-stabilized signal according to the first trigger signal in conjunction with the frame transformation signal and the voltage polarity control signal;
wherein the voltage polarity control signal is generated by a timing controller of the TFT LCD;
wherein the sampling unit comprises
a register for receiving the voltage polarity control signal having a plurality of pulses, wherein the register continuously samples continuous n pulses of the voltage polarity control signal to obtain the sampling signal, and n is a positive integer, and
an inversion checking device for judging whether the manner of voltage transformation of the voltage polarity control signal is the one-line inversion or the two-line inversion according to the sampling signal; and
wherein the sampling unit further comprises a rule checking device; and when the control unit cannot obtain the frame transformation signal template according to the manner of voltage transformation of the voltage polarity inversion of the voltage polarity control signal and the sampling signal, the rule checking device enables the control unit to output a second trigger signal, and the signal generating unit generates the second chopper-stabilized signal according to the second trigger signal in conjunction with the voltage polarity control signal.
2. The apparatus according to claim 1, wherein n is 8.
3. The apparatus according to claim 1, wherein the control unit comprises:
a control circuit for outputting the first trigger signal or the second trigger signal to the signal generating unit; and
a count circuit for obtaining the frame transformation signal template according to the manner of voltage transformation of the voltage polarity inversion of the voltage polarity control signal and the sampling signal.
4. The apparatus according to claim 3, wherein the control circuit comprises:
a central controller for outputting the first trigger signal or the second trigger signal to make the signal generating unit correspondingly generate the first chopper-stabilized signal or the second chopper-stabilized signal.
5. The apparatus according to claim 4, wherein:
the control circuit further comprises a watchdog; and
after m frame time periods have elapsed and if the count circuit cannot obtain the frame transformation signal template, the watchdog enables the control unit to output the second trigger signal, and the signal generating unit generates the second chopper-stabilized signal according to the second trigger signal and the voltage polarity control signal, wherein m is a positive integer greater than or equal to 20.
6. The apparatus according to claim 5, wherein the count circuit comprises:
a first register;
a second register;
a logic circuit, wherein:
when the manner of voltage transformation of the voltage polarity inversion of the voltage polarity control signal is the one-line inversion, the logic circuit judges whether the sampling signal is a first sequence signal or a second sequence signal, stores the sampling signal to the first register if the sampling signal is the first sequence signal, and stores the sampling signal to the second register if the sampling signal is the second sequence signal; and
when the manner of voltage transformation of the voltage polarity inversion of the voltage polarity control signal is the two-line inversion, the logic circuit judges whether the sampling signal is a third sequence signal or a fourth sequence signal, stores the sampling signal to the first register if the sampling signal is the third sequence signal, and stores the sampling signal to the second register when the sampling signal is the fourth sequence signal;
a counter for counting the numbers of the first sequence signals and the second sequence signals, or counting the numbers of the third sequence signals and the fourth sequence signals; and
a sequence register for temporarily storing the first sequence signals or the second sequence signals or the third sequence signals or the fourth sequence signals as the frame transformation signal template, and outputting the frame transformation signal template to the signal generating unit when the number of the first sequence signals or the second sequence signals is first counted to 3, or the number of the third sequence signals or the fourth sequence signals is first counted to 3.
7. The apparatus according to claim 6, wherein the signal generating unit comprises:
a first logic circuit for receiving the first trigger signal from the central controller, comparing the frame transformation signal template with the sampling signal to generate a frame transformation signal, and generating the first chopper-stabilized signal according to the frame transformation signal and the voltage polarity control signal;
a second logic circuit for receiving the second trigger signal from the central controller and generating the second chopper-stabilized signal in a specific order configured such that an exchanged order, which is obtained after a front half portion of the specific order and a rear half portion of the specific order are exchanged, is reverse to this specific order; and
a multiplexer, which is coupled to the first logic circuit and the second logic circuit and controlled by the central controller to select the first chopper-stabilized signal or the second chopper-stabilized signal as the chopper-stabilized signal, and to output the chopper-stabilized signal to the OP amplifiers.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. In a packet-switched communication system including a plurality of data sources and a plurality of destinations, interconnected by a plurality of communication switches,
an integrated shaping-scheduling mechanism responsive to shaped packet flows from a first set of data sources and to unshaped packet flows from a second set of data sources, for providing a single, multiplexed output flow of data packets from both the first and the second set of sources, the mechanism comprising:
a receiver for organizing incoming packets from said plurality of data sources into a plurality of predetermined flow queues, a first partition of flow queues corresponding to shaped packet flows and a second partition of flow queues corresponding to unshaped packet flows, each shaped packet flow being associated with a separate traffic profile, said traffic profile being defined as means for expressing upper limits on the amount of data packets that the packet communication system is allowed to transmit for an associated shaped packet flow;
a plurality of traffic regulators, each traffic regulator being used for determining whether a corresponding flow is classified as either \u201cvirtually compliant\u201d or \u201cvirtually incompliant\u201d, where all unshaped flows are always virtually compliant, and shaped flows are virtually compliant as long as their traffic profiles are not close to be violated, and virtually incompliant when their traffic profiles are close to be violated;
a selector for determining the order of transmission of data packets associated with packet flows, the activity of the selector being driven by the values of a plurality of state variables associated with the packet flows;
a flow-dequeue element for removing a just-transmitted packet from its queue and modifying one or more of said plurality of state variables associated with that queue; and
a flow-enqueue element for updating one or more of said plurality of state variables when a new packet reaches the head of one of a plurality of packet queues, each of said packet queues being associated with a respective packet flow.
2. A packet-switched communication system as defined in claim 1, wherein the traffic profile of a shaped flow fl is expressed by a set of dual-leaky-bucket traffic-regulator parameters, said dual-leaky-bucket traffic-regulator parameters being called a sustainable-bit-rate (SBR) bucket size Bl,s, a sustainable-bit-rate token rate \u03c1l,s, a peak-bit-rate (PBR) bucket size Bl,p, and a peak-bit-rate token rate \u03c1l,p.
3. A packet-switched communication system as defined in claim 2, wherein the status of virtual compliance of a packet flow fl is determined by comparison of said dual-leaky-bucket traffic-regulator parameters with a plurality of associated state variables, said state variables being called token levels Xl,s and Xl,p, and time of latest update \u03c4l.
4. A packet-switched communication system as defined in claim 3, wherein the selector determines the virtually-compliant versus virtually-incompliant status of a packet flow fl using the following test:
X
l
,
p
\u2264
B
l
,
p
–
(
l
l
k
\u03c1
l
,
p
–
l
l
k
r
)
X
l
,
s
\u2264
B
l
,
s
–
(
l
l
k
\u03c1
l
,
s
–
l
l
k
r
)
wherein llk is the length of the data packet currently located at the head of the packet queue associated with the packet flow being tested, said data packet being referred to as the head-of-the-queue packet of said packet queue, and r is the total transmission capacity of the server, the packet flow being classified as \u201cvirtually compliant\u201d as long as both inequalities are satisfied, and as \u201cvirtually incompliant\u201d otherwise.
5. A packet-switched communication system as defined in claim 1, wherein the selector determines the next packet to be transmitted by first searching for eligible packet flows and transmitting a packet from a queue associated with one of such eligible packet flows if any is found, and if no eligible packet flow is found, the selector determines the next packet to be transmitted by searching for a virtually-compliant packet flow and transmitting a packet from a queue associated with one of such virtually-compliant packet flows if any is found, and if no virtually-compliant packet flow is found the selector determines no packet transmission.
6. A packet-switched communication system as defined in claim 5, wherein a timestamp is associated with each of a plurality of packet flows, each timestamp being used in the determination of the eligibility and virtual-compliance status of the associated packet flow and in the determination of the order of transmission of packets.
7. A packet-switched communication system as defined in claim 6, wherein the eligibility of a packet flow is determined by checking the associated timestamp in accordance with a Smallest Eligible Finishing time First (SEFF) packet-selection policy.
8. A packet-switched communication system as defined in claim 7, wherein the flow-dequeue element modifies the state variables associated with the packet queue of the packet flow of a just-transmitted packet with the assessment of a new eligibility status of the packet flow and the consequent setting of an \u201celigibility flag\u201d associated with the packet flow.
9. A packet-switched communication system as defined in claim 8, wherein a timestamp is recalibrated by the flow-dequeue element if a data packet has just been transmitted from the packet queue of the associated packet flow and the current value of said timestamp is greater than the current \u201creal\u201d time plus the service interval of the just transmitted packet, the recalibrated timestamp being equal to the sum of the \u201creal\u201d time plus the service interval of the just transmitted packet, said service interval being equal to the ratio between the length of the just transmitted packet and the guaranteed service rate of the packet flow of the just transmitted packet.
10. A packet-switched communication system as defined in claim 8, wherein the flow-enqueue element uses the result of the virtual-compliance test applied to the packet flow being processed and the current value of the eligibility flag of said packet flow to compute a value for the timestamp associated with said packet flow.
11. A packet-switched communication system as defined in claim 10, wherein if the value in the eligibility flag is \u201cFALSE\u201d and the associated packet flow is virtually incompliant, the generated timestamp is the maximum of either the previous timestamp or the current \u201creal\u201d time plus the service interval of the head-of-the-queue packet of said packet flow, with said service interval being added to said maximum.
12. A packet-switched communication system as defined in claim 10, wherein if the head-of-queue packet of a packet flow is a newly-arrived packet, the generated timestamp is the maximum of either the previous timestamp of the packet flow or the current \u201creal\u201d time, with the value of the service interval of the head-of-the-queue packet being added to said maximum.
13. A packet-switched communication system as defined in claim 10, wherein if the packet flow is virtually-compliant and its head-of-the-queue packet did not just arrive to the queue, the generated timestamp is equal to the previous timestamp of the packet flow plus the service interval of the head-of-the-queue packet.
14. A method of scheduling service over a plurality of queues holding flows of packet data traffic, the method integrating shaping of packet flows and scheduling of both shaped and unshaped packet flows and defined by the steps of:
responsive to receiving a plurality of data packets from a plurality of data sources, identifying for each receiving data packet a respective queue for storage of said data packet;
storing each received data packet in its identified queue;
determining, for each shaped packet flow, a set of traffic-regulator parameters associated with a traffic profile of said packet flow;
for each packet flow, performing a \u201cvirtual-compliance\u201d test every time a new packet reaches the head of the corresponding flow queue, wherein each unshaped flow is predetermined as being always classified as virtually compliant, and each shaped flow is determined to be classified as virtually compliant as long as the size of its head-of-queue packet does not create the possibility of violating the predetermined traffic-regulator parameters;
selecting a packet for transmission from among eligible packet flows and virtually-compliant packet flows, therefore always excluding from the selection data packets of packet flows that are both non-eligible and virtually-incompliant;
performing a flow-dequeue process subsequent to data packet transmission for recalibrating a plurality of state variables associated with the packet queue of the packet flow of the just transmitted data packet; and
performing a flow-enqueue process upon every arrival of a new packet to the head of a corresponding flow queue.
15. The method as defined in claim 14, wherein the traffic regulators are defined by dual-leaky-bucket parameters for a sustainable-bit-rate (SBR) leaky bucket and a peak-bit-rate (PBR) leaky bucket, and include for each leaky bucket a first state variable X that defines the number of tokens in the bucket, and a second state variable \u03c4 that expresses the time when the number of tokens was last updated.
16. The method according to claim 15, wherein the test for virtual compliance is based on the verification of the following inequalities:
X
l
,
p
\u2264
B
l
,
p
–
(
l
l
k
\u03c1
l
,
p
–
l
l
k
r
)
X
l
,
s
\u2264
B
l
,
s
–
(
l
l
k
\u03c1
l
,
s
–
l
l
k
r
)
wherein Bl,s and Bl,p are the \u201cbucket sizes\u201d for the two leaky buckets of the packet flow being tested, llk is the length of the head-of-the-queue packet of said packet flow, \u03c1l,s and \u03c1l,p are the token rates of the two leaky buckets, and r is the total transmission capacity of the server, the packet flow being defined as \u201cvirtually compliant\u201d as long as both inequalities are satisfied.
17. The method according to claim 14, wherein in determining the order of packets to be transmitted, the following steps are used:
searching for an eligible packet flow, and selecting an eligible packet flow with the shortest time before expiration of the transmission deadline for its head-of-the-queue packet, said transmission deadline being expressed by a timestamp associated with said packet flow; if no such eligible packet flow exists, then
searching for a virtually-compliant packet flow, and selecting a virtually-compliant packet flow with the shortest time before expiration of the transmission deadline for its head-of-the-queue packet; if no such virtually-compliant packet flow exists, then
not selecting any packet for transmission at that time.
18. The method according to claim 14, wherein the eligibility of a packet flow is determined in accordance with a Smallest Eligible Finishing time First (SEFF) packet-selection policy.
19. The method according to claim 18, wherein in performing the flow-dequeue process for a packet flow fl, the following steps are executed to determine the value of an eligibility flag EFl and possibly recalibrate the timestamp Flk of the packet flow:
1
if (Flk > tl,dk + llkr1)
* Timestamp is not eligible *
2
EFl \u2190 FALSE
3
Flk \u2190 tl,dk + llkrl
* Recalibration of timestamp *
4
else
5
EFl \u2190 TRUE
* Timestamp is eligible *
where tl,dk is the current \u201creal\u201d time.
20. The method according to claim 19, wherein in performing the flow-enqueue process for a packet flow fI, the following steps are executed:
1
if (EF1 = FALSE) and (i \u03b5 I)
2
Flk \u2190 max(Flk\u22121,tl,hk + llkrl) + 1tkr1
3
else if (flow 22-i is newly backlogged)
4
Flk \u2190 max(Flk\u22121,tl,hk) + llkrl
5
else
6
Flk \u2190 Flk\u22121 + llkrl
where I is defined as the set of virtually-incompliant packet flows.