Author: claimsbot

1. An apparatus for on-die termination of a semiconductor memory, comprising:
a first ODT (On-Die Termination) voltage generating unit configured to output a first line voltage by calibrating an input voltage with a resistance ratio according to a first code having at least two bits;
a first code calibrating unit that counts the first code according to the result of a comparison between the first line voltage and a reference voltage, stops the code count when the first code is one of two target values that are a maximum value and a minimum value, and stores the first code corresponding to the maximum value or the minimum value;
a second ODT voltage generating unit that outputs a second line voltage by calibrating an input voltage with a resistance ratio according to the first code and a second code having at least two bits; and
a second code calibrating unit that counts the second code according to the result of a comparison between the second line voltage and the reference voltage, stops the code count when the second code is one of two target values that are a maximum value and a minimum value, and stores the second code corresponding to the maximum value or the minimum value, wherein the first code calibrating unit includes a first XNOR gate that is configured to stop the code counting of the first code in response to the first code and the result of the comparison between the first line voltage and the reference voltage, and the second code calibrating unit includes a second XNOR gate that is configured to stop the code counting of the second code in response to the second code and the result of the comparison between the second line voltage and the reference voltage.
2. The apparatus of claim 1,
wherein the first ODT voltage generating unit includes:
a plurality of switching elements that are connected to power terminals and are turned on according to the first code, and
a plurality of resistors that are connected between the plurality of switching elements and ground terminals VSSQ, respectively.
3. The apparatus of claim 1,
wherein the first code calibrating unit includes:
a comparison unit that compares the first line voltage with the reference voltage to output a first comparison result signal;
a register that counts the first code according to the first comparison result signal and a first control signal; and
a control unit that generates the first control signal according to the first comparison result signal and the first code.
4. The apparatus of claim 3,
wherein the register stops the counting when the first control signal is disabled.
5. The apparatus of claim 3,
wherein the control unit disables the first control signal when the first comparison result signal is at a level that indicates an up-counting operation of the register, and the first code reaches the maximum value.
6. The apparatus of claim 3,
wherein the control unit disables the first control signal when the first comparison result signal is at a level that indicates a down-counting operation of the register, and the first code reaches the minimum value.
7. The apparatus of claim 3,
wherein the control unit includes the first XNOR gate that receives the first comparison result signal and the first code.
8. The apparatus of claim 1,
wherein the second ODT voltage generating unit includes:
a first transistor group having a plurality of transistors that are connected to power terminals and are turned on according to the second code;
a first resistor group having a plurality of resistors that are connected between the transistors of the first transistor group and ground terminals, respectively;
a second resistor group having a plurality of resistors that are connected to the resistors of the first resistor group; and
a second transistor group having a plurality of transistors that are connected between the resistors of the second resistor group and the ground terminals, respectively, and are turned on according to the second code.
9. The apparatus of claim 1,
wherein the second code calibrating unit includes:
a comparison unit that compares the second line voltage with the reference voltage so as to output a second comparison result signal;
a register that counts the second code according to the second comparison result signal and a second control signal; and
a control unit that generates the second control signal according to the second comparison result signal and the second code.
10. The apparatus of claim 9,
wherein the register stops the counting when the second control signal is disabled.
11. The apparatus of claim 9,
wherein the control unit disables the second control signal when the second comparison result signal is at a level that indicates an up-counting operation of the register, and the second code reaches the maximum value.
12. The apparatus of claim 9,
wherein the control unit disables the second control signal when the second comparison result signal is at a level that indicates a down-counting operation of the register, and the second code reaches the minimum value.
13. The apparatus of claim 9,
wherein the control unit includes the second XNOR gate that receives the second comparison result signal and the second code.
14. A method of on-die termination of a semiconductor memory that includes a first voltage generating unit in which a resistance ratio is determined according to a first code and a second voltage generating unit in which a resistance ratio is determined according to a second code, the method comprising:
primarily comparing a first line voltage output from the first voltage generating unit with a reference voltage;
counting the first code according to a result of the primary comparison;
stopping the counting of the first code when the first code is one of two target values that are a maximum value and a minimum value defining that every bit of the first code is the same value by using a first code calibrating unit including a first XNOR gate that is configured to stop the first code counting in response to the first code and the result of the primary comparison between the first line voltage and the reference voltage, and storing the first code corresponding to the maximum value or the minimum value;
secondarily comparing a second line voltage output from the second voltage generating unit and the reference voltage;
counting the second code according to a result of the secondarily comparison; and
stopping the counting of the second code when the second code is one of two target values that are a maximum value and a minimum value defining that every bit of the second code is the same value by using a second code calibrating unit including a second XNOR gate that is configured to stop the second code counting in response to the second code and the result of the secondarily comparison between the second line voltage and the reference voltage, and storing the second code corresponding to the maximum value or the minimum value.
15. The method of claim 14,
wherein the stopping of the counting of the first code and the storing of the code value based on the final count is stopping the counting of the first code and storing the code value based on the final count when the signal level according to the result of the primary comparison is the same as the level of every bit in the first code.
16. The method of claim 14,
wherein the stopping of the counting of the first code and the storing of the code value based on the final count is stopping the counting of the first code and storing the code value based on the final count when the result of the primary comparison is at a level that indicates an up-counting operation, and the first code reaches the maximum value.
17. The method of claim 14,
wherein the stopping of the counting of the first code and the storing of the code value based on the final count is stopping the counting of the first code and storing the code value based on the final count when the result of the primary comparison is at a level that indicates a down-counting operation, and the first code reaches the minimum value.
18. The method of claim 14,
wherein the stopping of the counting of the second code and the storing of the code value based on the final count is stopping the counting of the second code and storing the code value based on the final count when the signal level according to the result of the secondary comparison is the same as the level of every bit in the second code.
19. The method of claim 14,
wherein the stopping of the counting of the second code and the storing of the code value based on the final count is stopping the counting of the second code and storing the code value based on the final count when the result of the secondary comparison is at a level that indicates an up-counting operation, and the second code reaches the maximum value.
20. The method of claim 14,
wherein the stopping of the counting of the second code and the storing of the code value based on the final count is stopping the counting of the second code and storing the code value based on the final count when the result of the secondary comparison is at a level that indicates a down-counting operation, and the second code reaches the minimum value.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for the detection of pathogens in a sample, the sample contained in a housing, comprising:
placing paramagnetic microspheres with immobilizing primary antibodies that bind with the pathogens in the housing;
placing optical markers bound to secondary antibodies that bind with the pathogens in the housing;
forming in the sample molecular complexes, each molecular complex comprising one of the pathogens bound to at least one of the primary antibodies and at least one of the secondary antibodies;
focusing the molecular complexes in a field of view of a proximal end of a waveguide probe, the proximal end comprised of a first tube and a second tube and shaped to form a receiving aperture, the aperture having a magnet received therein;
transmitting light through the proximal end and into the housing to generate a fluorescent signal from the molecular complexes;
collecting the fluorescent signal; and
detecting the fluorescent signal which corresponds to the presence of the pathogens in the sample.
2. The method claim 1 wherein the antibodies are anti-Salmonella.
3. The method of claim 1 wherein the pathogen is S.typhimurium.
4. The method of claim 1 wherein the sample is selected from the group consisting of mammals, fish and fowl.
5. The method of claim 1 wherein transmitting light through the proximal end comprises:
injecting a laser beam into and through the first tube and through the proximal end.
6. The method of claim 1 wherein the housing is a cuvette.
7. The method of claim 1 wherein the first tube has a wall and the length of the diameter of the proximal end is about twice the magnitude of the wall thickness of the first tube.
8. A method for the detection of pathogens in a sample, the sample contained in a housing, comprising:
placing paramagnetic microspheres with immobilizing primary antibodies that are capable of binding with the pathogens in the housing;
placing optical markers bound to secondary antibodies that are capable of binding with the pathogens in the housing;
forming in the sample molecular complexes, each molecular complex comprising one of the pathogens bound to at least one of the primary antibodies and at least one of the secondary antibodies;
focusing the molecular complexes in a field of view of a proximal end of a waveguide probe, the proximal end comprised of a first tube and a second tube and shaped to form a receiving aperture, the aperture having a magnet received therein;
communicating an excitation fiber with the first tube;
transmitting light through the excitation fiber, first tube and into the housing to generate a fluorescent signal from the molecular complexes;
collecting the fluorescent signal; and
detecting the fluorescent signal.

1. A liquid crystal display, comprising:
a first gate line for transmitting a first gate signal;
a second gate line for transmitting a second gate signal;
a data line for transmitting a data signal;
a pixel unit, electrically connected to the first gate line and the data line, for outputting an image signal according to the first gate signal and the data signal;
a photo-sensing input unit, electrically connected to the first gate line, for generating a sensing voltage according to a driving voltage and an incident light signal, and for outputting a readout signal according to the sensing voltage and the first gate signal;
a driving adjustment unit, electrically connected to the second gate line and the photo-sensing input unit, for providing the driving voltage according to the second gate signal and the incident light signal; and
a readout line, electrically connected to the photo-sensing input unit, for transmitting the readout signal;
wherein the photo-sensing input unit comprises:
a first transistor having a first end for receiving a first common voltage, a gate end for receiving the driving voltage, and a second end;
a first capacitor, electrically connected between the first and second ends of the first transistor; and
a second transistor having a first end electrically connected to the second end of the first transistor, a gate end electrically connected to the first gate line, and a second end electrically connected to the readout line;
wherein the driving adjustment unit comprises:
a third transistor having a first end for receiving a second common voltage, a gate end electrically connected to the second gate line, and a second end electrically connected to the gate end of the first transistor;
a fourth transistor having a first end for receiving a third common voltage, a gate end electrically connected to the second gate line, and a second end electrically connected to the second end of the first transistor; and
a second capacitor electrically connected between the second end of the third transistor and the second end of the fourth transistor.
2. The liquid crystal display of claim 1, wherein the first transistor is a photo-sensing thin film transistor or a photo-sensing field effect transistor, the second transistor is a thin film transistor or a field effect transistor, the third transistor is a thin film transistor or a field effect transistor, and the fourth transistor is a thin film transistor or a field effect transistor.
3. A photo-sensing input device, comprising:
a photo-sensing input unit, for generating a sensing voltage according to a driving voltage and an incident light signal, and for outputting a readout signal according to the sensing voltage and a first gate signal; and
a driving adjustment unit, electrically connected to the photo-sensing input unit, for providing the driving voltage according to a second gate signal and the incident light signal;
wherein the photo-sensing input unit comprises:
a first transistor having a first end for receiving a first common voltage, a gate end for receiving the driving voltage, and a second end;
a first capacitor, electrically connected between the first and second ends of the first transistor; and
a second transistor having a first end electrically connected to the second end of the first transistor, a gate end for receiving the first gate signal, and a second end for outputting the readout signal;
wherein the driving adjustment unit comprises:
a third transistor having a first end for receiving a second common voltage, a gate end for receiving the second gate signal, and a second end electrically connected to the gate end of the first transistor;
a fourth transistor having a first end for receiving a third common voltage, a gate end for receiving the second gate signal, and a second end electrically connected to the second end of the first transistor; and
a second capacitor electrically connected between the second end of the third transistor and the second end of the fourth transistor.
4. The photo-sensing input device of claim 3, wherein the first transistor is a photo-sensing thin film transistor or a photo-sensing field effect transistor, the second transistor is a thin film transistor or a field effect transistor, the third transistor is a thin film transistor or a field effect transistor, and the fourth transistor is a thin film transistor or a field effect transistor.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of treating lymphoma in a subject in need thereof, comprising:
administering to a subject afflicted with lymphoma an antibody that binds to tenascin in a treatment effective amount.
2. A method according to claim 1, wherein said antibody is a monoclonal antibody.
3. A method according to claim 1, wherein said subject is a human subject.
4. A method according to claim 1, wherein said antibody is selected from the group consisting of monoclonal antibody 81C6 and antibodies that bind to the epitope bound by monoclonal antibody 81C6.
5. A method according to claim 1, wherein said lymphoma is Hodgkin’s lymphoma.
6. A method according to claim 1, wherein said lymphoma is Non-Hodgkin’s lymphoma.
7. A method according to claim 1, wherein said antibody is coupled to a radioisotope.
8. A method according to claim 7 wherein said radioisotope is selected from the group consisting of 131I, 90Y, 211At, 212Bi, 67Cu, 186Re, 188Re, and 212Pb.
9. A method according to claim 7, wherein said radioisotope is 131I.
10. A method according to claim 7, wherein said antibody coupled to a radioisotope is administered in an amount of from 5,000 rads to 100,000 rads.
11. A method according to claim 1, wherein said administering step is a parenteral injection step.
12. A method of treating Non-Hodgkin’s lymphoma in a human subject in need thereof, comprising:
parenterally administering to a human subject afflicted with lymphoma a monoclonal antibody that binds to tenascin in a treatment effective amount;
wherein said antibody is selected from the group consisting of monoclonal antibody 81C6 and antibodies that bind to the epitope bound by monoclonal antibody 81C6; and
wherein said antibody is coupled to a radioisotope.
13. A method according to claim 12, wherein said Non-Hodgkin’s Lymphoma is unresponsive to chemotherapy treatment selected from the group consisting of rituximab, cyclophosphamide, doxorubicin, vincristine and prednisone treatment.
14. A method according to claim 12, wherein said Non-Hodgkin’s Lymphoma is unresponsive to rituximab treatment.
15. A method according to claim 12, wherein said radioisotope is selected from the group consisting of 131I, 90Y, 211At, 212Bi, 67Cu, 186Re, 188Re, and 212Pb.
16. A method according to claim 12, wherein said radioisotope is 131I.
17. A method according to claim 12, wherein said antibody coupled to a radioisotope is administered in an amount of from 5,000 rads to 100,000 rads.
18. A method according to claim 12, wherein said Non-Hodgkin’s lymphoma is a low grade lymphoma.
19. A method according to claim 12, wherein said Non-Hodgkin’s lymphoma is an intermediate grade lymphoma.
20. A method according to claim 12, wherein said Non-Hodgkin’s lymphoma is a high grade lymphoma.
21. A method according to claim 12, wherein said parenteral administration step is carried out by intravenous injection.