Author: claimsbot

What is claimed is:

1. A signal processing circuit generating a digital signal based on an input pulse signal, the signal processing circuit comprising:
a clock pulse output circuit which outputs clock pulses having one of positive and negative polarities for a period which includes a pulse of the input pulse signal;
a counter circuit which counts the clock pulses; and
an output circuit which outputs the digital signal based on a counted value of said counter circuit.
2. The signal processing circuit as claimed in claim 1, wherein:
said clock pulse output circuit comprises:
a first clock pulse output circuit which outputs clock pulses when the input pulse signal has a positive polarity; and
a second clock pulse output circuit which outputs clock pulses when the input pulse signal has a negative polarity; and

said counter circuit comprises:
a first counter circuit which counts the clock pulses supplied from said first clock pulse output circuit; and
a second counter circuit which counts the clock pulses supplied from said second clock pulse output circuit.
3. The signal processing circuit as claimed in claim 2, wherein:
said first counter circuit outputs a first timing signal at a first predetermined counted value;
said second counter circuit outputs a second timing signal at a second predetermined counted value; and
said output circuit comprises:
a first latch circuit which latches a counted value of said first counter circuit based on the second timing signal; and
a second latch circuit which latches a counted value of said second counter circuit based on the first timing signal.
4. The signal processing circuit as claimed in claim 3, wherein:
said output circuit comprises:
a first delay circuit which delays the first timing signal; and
a second delay circuit which delays the second timing signal;

said first counter circuit is reset by an output signal of said second delay circuit; and
said second counter circuit is reset by an output signal of said first delay circuit.
5. The signal processing circuit as claimed in claim 4, wherein said output circuit further comprises:
a flip flop which is set by the output signal of said first delay circuit and is reset by the output signal of said second delay circuit; and
a switching circuit which switches, based on an output of said flip flop, between outputs of the counted values latched by said first and second latch circuits, respectively.
6. The signal processing circuit as claimed in claim 2, wherein said counter circuit further comprises:
a third counter circuit which counts the clock pulses supplied from said first clock pulse output circuit;
a fourth counter circuit which counts the clock pulses supplied from said second clock pulse output circuit; and
a setting circuit which sets the predetermined period based on respective predetermined counted values of said third and fourth counter circuits.
7. The signal processing circuit as claimed in claim 6, wherein:
said third counter circuit outputs a first timing signal at the predetermined counted value of said third counter circuit;
said fourth counter circuit outputs a second timing signal at the predetermined counted value of said fourth counter circuit; and
said setting circuit outputs, based on the first and second timing signals, a signal which determines the predetermined period.
8. The signal processing circuit as claimed in claim 7, wherein said setting circuit comprises a flip flop which is set by the first timing signal and is reset by the second timing signal.
9. The signal processing circuit as claimed in claim 8, wherein one of the counted values of said third and fourth counter circuits is reset when said flip flop is reset.
10. The signal processing circuit as claimed in claim 8, wherein said output circuit comprises:
a rising edge output circuit which outputs a third timing signal at a rising edge of an output of said flip flop;
a falling edge output circuit which outputs a fourth timing signal at a falling edge of the output of said flip flop;
a first latch circuit which latches a counted value of said first counter circuit based on the fourth timing signal; and
a second latch circuit which latches a counted value of said second counter circuit based on the third timing signal.
11. The signal processing circuit as claimed in claim 10, wherein:
said output circuit further comprises:
a first delay circuit which delays the third timing signal and outputs a fifth timing signal; and
a second delay circuit which delays the fourth timing signal and outputs a sixth timing signal;

said first counter circuit is reset by the sixth timing signal; and
said second counter circuit is reset by the fifth timing signal.
12. The signal processing circuit as claimed in claim 10, wherein said output circuit further comprises a switching circuit which switches, based on an output of said flip flop, between outputs of the counted values latched by said first and second latch circuits, respectively.
13. The signal processing circuit as claimed in claim 2, wherein said output circuit comprises:
a generation circuit which generates a phase difference pulse signal having a predetermined phase difference with respect to the input pulse signal;
a rising edge output circuit which outputs a third timing signal at a rising edge of the phase difference pulse signal;
a falling edge output circuit which outputs a fourth timing signal at a falling edge of the phase difference pulse signal;
a first latch circuit which latches a counted value of said first counter circuit based on the third timing signal; and
a second latch circuit which latches a counted value of said second counter circuit based on the fourth timing signal.
14. The signal processing circuit as claimed in claim 13, wherein:
said output circuit further comprises:
a first delay circuit which delays the third timing signal to output a fifth timing signal; and
a second delay circuit which delays the fourth timing signal to output a sixth timing signal;

said first counter circuit is reset by the fifth timing signal; and
said second counter circuit is reset by the sixth timing signal.
15. The signal processing circuit as claimed in claim 13, wherein said output circuit further comprises:
a third delay circuit which delays the phase difference pulse signal to output a delayed phase difference pulse signal; and
a switching circuit which switches, based on the delayed phase difference pulse signal, between outputs of the counted values latched by said first and second latch circuits, respectively.
16. The signal processing circuit as claimed in claim 1, wherein said output circuit includes a digital low-pass filter.
17. A method of generating a digital signal based on an input pulse signal, the method comprising the steps of:
(a) outputting clock pulses having one of positive and negative polarities for a period including a pulse of the input pulse signal;
(b) counting the clock pulses; and
(c) outputting the digital signal based on the counted value obtained in said step (b).

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

We claim:

1. In an environment comprising at least one source of a desired signal and at least one source of undesired electromagnetic energy, an antenna system comprising:
a plurality of antenna elements, each antenna element responsive to generate an electrical signal when in the presence of an electromagnetic field; and
a partitioning structure comprising walls defining sectors:
the partitioning structure positioned between the plurality of antenna elements and the set of each desired signal and each source of undesired electromagnetic energy; and
the partitioning structure disposed so as to create at least two non-identical radio frequency fields of view, such that not all antenna elements share the same radio frequency field of view.
2. The antenna system according to claim 1, further comprising:
a processing unit:
in electrical communication with at least two antenna elements and
operative to receive the electrical signal of each communicated antenna element,
operative to characterize the electrical signal of each communicated antenna element, and
operative to modify those electrical signals for which the characterization meets a condition.
3. The antenna system according to claim 2, wherein the characterization of the electrical signal of each communicated antenna element comprises a function of the power such electrical signal.
4. The antenna system according to claim 3, wherein the condition for modification is that the function of the power of the characterized electrical signal exceeds a threshold.
5. The antenna system according to claim 4, wherein the modification of those electrical signals for which power is greater than a threshold is attenuation.
6. The antenna system according to claim 4, wherein the modification of those electrical signals for which power is greater than a threshold is blocking.
7. The antenna system according to claim 2, further comprising,
a combiner,
in electrical communication with at the processing unit, and
operative to receive at least two electrical signals from the processing unit and combine the signals.
8. The antenna system according to claim 1 further comprising at least one absorber substantially lining at least one interior wall of at least one sector.
9. The antenna system according to claim 2 further comprising at least one absorber substantially lining at least one interior wall of at least one sector.
10. The antenna system according to claim 3 further comprising at least one absorber substantially lining at least one interior wall of at least one sector.
11. The antenna system according to claim 4 further comprising at least one absorber substantially lining at least one interior wall of at least one sector.
12. The antenna system according to claim 5 further comprising at least one absorber substantially lining at least one interior wall of at least one sector.
13. The antenna system according to claim 6 further comprising at least one absorber substantially lining at least one interior wall of at least one sector.
14. The antenna system according to claim 7 further comprising at least one absorber substantially lining at least one interior wall of at least one sector.
15. The antenna system according to claim 1 further comprising an outer skin substantially covering at least one sector.
16. The antenna system according to claim 7 further comprising an outer skin substantially covering at least one sector.
17. The antenna system according to claim 15, wherein the outer skin is a bandpass filter.
18. The antenna system according to claim 1 wherein the partitioning structure comprises a plurality of hex-shaped walls.
19. In an antenna array comprising a plurality of antenna elements, a method for improving the resistance of the antenna system to interference, the method comprising:
physically partitioning the space adjacent the antenna array into at least two sectors with respect to an angle of arrival of incident electromagnetic energy such that not all antenna elements share the same radio frequency field of view.
20. The method according to claim 19, further comprising:
in response to electromagnetic energy incident on the antenna array, determining which array elements contain energy characteristic of interference; and
modifying the signal from at least one array element that contains energy characteristic of interference.
21. The method according to claim 20, wherein the step of modification comprises broadband attenuation of the signal from at least one antenna element that contains energy characteristic of interference.
22. The method according to claim 20, wherein the step of modification comprises blocking the electromagnetic energy from at least one antenna element that contains energy characteristic of interference.
23. The method according to claim 19, further comprising substantially coating at least one surface of a sector boundary with an absorber.

1. A sheet processing apparatus comprising:
a pair of planar members configured to have a plane surface respectively to hold a booklet made of a folded sheet therebetween, the plane surfaces being substantially parallel to each other; and
a pressing member configured to enter between the plane surfaces to press a folded spine of the booklet, and to be moved along a direction of a length of the folded spine while pressing the folded spine.
2. The sheet processing apparatus according to claim 1, wherein the plane surfaces regulate the deformation, in a thickness direction of the booklet, of the folded spine by contacting the folded spine for preventing the thickness of the folded spine from exceeding the thickness of the booklet.
3. The sheet processing apparatus according to claim 1, wherein the pressing member presses the folded spine to deform the folded spine into a square shape, and a pressing position where the square shape is formed along the direction of the length of the folded spine is within a region defined by the plane surfaces.
4. The sheet processing apparatus according to claim 1, wherein the pressing member is a roller that rotates and moves along the direction of the length of the folded spine.
5. The sheet processing apparatus according to claim 1, wherein the folded spine is positioned in the region defined by the plane surfaces, and the pressing member enters the region to press the folded spine.
6. The sheet processing apparatus according to claim 1, further comprising:
a positioning member against which the folded spine of the booklet is abutted to position the booklet,
wherein the pair of planar members holds the booklet positioned by the positioning member, and the pressing member presses the folded spine of the booklet held by the holding unit.
7. The sheet processing apparatus according to claim 1, further comprising:
a folding unit configured to fold the sheet,
wherein the pressing member presses the folded spine of the booklet made of the sheet folded by the folding unit.
8. An image forming apparatus comprising:
an image forming portion that forms an image on a sheet; and
a sheet processing apparatus that processes the sheet having the image formed thereon,
wherein the sheet processing apparatus includes:
a pair of planar members configured to have a plane surface respectively to hold a booklet made of a folded sheet therebetween, the plane surfaces being substantially parallel to each other; and
a pressing member configured to enter between the plane surfaces to press a folded spine of the booklet, and to be moved along a direction of a length of the folded spine while pressing the folded spine.
9. The image forming apparatus according to claim 8, wherein the plane surfaces regulate the deformation, in a thickness direction of the booklet, of the folded spine by contacting the folded spine for preventing the thickness of the folded spine from exceeding the thickness of the booklet.
10. The image forming apparatus according to claim 8, wherein the pressing member presses the folded spine to deform the folded spine into a square shape, and a pressing position where the square shape is formed along the direction of the length of the folded spine is within a region defined by the plane surfaces.
11. The image forming apparatus according to claim 8, wherein the pressing member is a roller that rotates and moves along the direction of the length of the folded spine.
12. The image forming apparatus according to claim 8, further comprising:
a positioning member against which the folded spine of the booklet is abutted to position the booklet,
wherein the pair of planar members holds the booklet positioned by the positioning member, and the pressing member presses the folded spine of the booklet held by the holding unit.
13. The image forming apparatus according to claim 8, further comprising:
a folding unit configured to fold the sheet,
wherein the pressing member presses the folded spine of the booklet made of the sheet folded by the folding unit.
14. A image forming apparatus according to claim 8, wherein the folded spine is positioned in the region defined by the plane surfaces, and the pressing member enters the region to press the folded spine.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor device comprising:
a power source terminal to which a first power source voltage and a second power source voltage higher than the first power source voltage are supplied;
a grounding terminal to which a grounding voltage is supplied;
a first power source line coupled to the power source terminal;
a logic semiconductor chip which is coupled to the first power source line and the grounding terminal, operates on any of the first power source voltage and the second power source voltage, and performs a logic process on input data;
a power supply interrupting semiconductor chip which is coupled to the first power source line and the grounding terminal, when the first power source voltage is supplied, outputs the voltage to a second power source line and, when the second power source voltage is supplied, stops supplying the voltage to the second power source line;
a nonvolatile semiconductor storage chip which is coupled to the second power source line and the grounding terminal and operates on supply of the voltage; and
a controller chip which is coupled to the second power source line and the grounding terminal, has a first terminal to which a signal is input and, on reception of the input signal, inputsoutputs data tofrom the nonvolatile semiconductor storage chip.
2. A semiconductor device comprising:
a power source terminal to which a first power source voltage and a second power source voltage higher than the first power source voltage are supplied;
a grounding terminal to which a grounding voltage is supplied;
a first power source line coupled to the power source terminal;
a logic semiconductor chip which is coupled to the first power source line and the grounding terminal, operates on any of the first power source voltage and the second power source voltage, and performs a logic process on input data;
a power supply interrupting semiconductor chip which is coupled to the first power source line and the grounding terminal, when the first power source voltage is supplied, outputs the voltage to a second power source line and, when the second power source voltage is supplied, stops supplying the voltage to the second power source line;
a nonvolatile semiconductor storage chip which is coupled to the second power source line and the first power source line and operates on supply of the voltage; and
a controller chip which is coupled to the second power source line and the first power source line, has a first terminal to which a signal is input and, on reception of the input signal, inputsoutputs data fromto the nonvolatile semiconductor storage chip.
3. The semiconductor device according to claim 1,
wherein area of the nonvolatile semiconductor storage chip is larger than that of the logic semiconductor chip, the power supply interrupting semiconductor chip, and the controller chip, and
wherein the logic semiconductor chip, the power supply interrupting semiconductor chip, and the controller chip are mounted over the nonvolatile semiconductor storage chip.
4. The semiconductor device according to claim 3,
wherein the nonvolatile semiconductor storage chip has a rectangular shape,
wherein pads are arranged along one of four sides of the rectangular shape,
wherein a plurality of nonvolatile semiconductor storage chips are stacked so that the pads of the nonvolatile semiconductor chips are aligned in the nonvolatile semiconductor storage chips, and
wherein the controller chip is mounted over the uppermost nonvolatile semiconductor storage chip in the stacked chips along a side different from the side along which the pads of the nonvolatile semiconductor storage chip are arranged in a position closer to the different side.
5. A semiconductor device comprising:
a power source terminal to which a first power source voltage and a second power source voltage higher than the first power source voltage are supplied;
a grounding terminal to which a grounding voltage is supplied;
a first power source line coupled to the power source terminal;
a logic semiconductor chip which has a power supply interrupting circuit, when the first power source voltage is supplied, for outputting the voltage to a second power source line and, when the second power source voltage is supplied, stops supplying the voltage to the second power source line, wherein the logic semiconductor chip is coupled to the first power source line and the grounding terminal, operates on any of the first power source voltage and the second power source voltage, and performs a logic process on input data;
a nonvolatile semiconductor storage chip which is coupled to the second power source line and the grounding terminal and operates on supply of the voltage; and
a controller chip which is coupled to the second power source line and the grounding terminal, has a first terminal to which a signal is input and, on reception of the input signal, inputsoutputs data fromto the nonvolatile semiconductor storage chip.
6. A semiconductor device comprising:
a power source terminal to which a power source voltage is supplied;
a grounding terminal to which a grounding voltage is supplied;
a first power source line coupled to the power source terminal;
a first semiconductor chip which is coupled to the first power source line and the grounding terminal;
a power source voltage supply control circuit which is coupled to the first power source line and the grounding terminal and controls whether or not voltage is output from the first power source line to a second power source line in accordance with a signal input from the outside; and
a second semiconductor chip which is coupled to the second power source line and the grounding terminal and operates on reception of the voltage supplied.
7. The semiconductor device according to claim 6, further comprising a third semiconductor chip different from the first and second semiconductor chips and having the power source voltage supply control circuit,
wherein the signal input from the outside is supplied to the first semiconductor chip, and
wherein a signal responding to the signal input from the outside supplied from the first semiconductor chip is supplied to the third semiconductor chip, and the power source voltage supply control circuit controls a voltage output.
8. The semiconductor device according to claim 6, wherein the second semiconductor chip has a nonvolatile semiconductor storage chip capable of retaining data even when supply of the power source voltage stops.
9. The semiconductor device according to claim 6, wherein the second semiconductor chip has an internal step-down circuit for stepping down the power source voltage supplied from the outside and supplying the resultant voltage to the inside.
10. A semiconductor device comprising:
a first semiconductor chip which is coupled to a power source terminal to which a first power source voltage is supplied and a grounding terminal to which a grounding voltage is supplied, and outputs a control signal in accordance with an input signal;
a power supply interrupting semiconductor chip coupled to the power source terminal and the grounding terminal and supplying or stopping a second power source voltage to a power source line in accordance with output of the control signal;
a nonvolatile semiconductor storage chip coupled to the power source line and the grounding terminal, operates on receipt of the second power source voltage, and inputsoutputs data in response to a signal input from a first terminal;
a controller chip for controlling the nonvolatile semiconductor storage chip; and
a wiring board having a first surface over which the first semiconductor chip, the power supply interrupting semiconductor chip, the nonvolatile semiconductor storage chip, or the controller chip is arranged, and a second surface having an external terminal for inputtingoutputting a signal fromto a second terminal provided for the first semiconductor chip and the first terminal of the controller chip,
wherein the wiring board, the first semiconductor chip, the power supply interrupting semiconductor chip, and the controller chip have pads to be coupled to each other via wires,
wherein the nonvolatile semiconductor storage chip has a rectangular shape and is provided over the wiring board,
wherein area of the first semiconductor chip is smaller than that of the nonvolatile semiconductor storage chip,
wherein the first semiconductor chip is arranged over the nonvolatile semiconductor storage chip,
wherein pads of the first semiconductor chip are provided along a first long side of the rectangular shape of the nonvolatile semiconductor storage chip and coupled to pads of the wiring board provided along the first long side via wires,
wherein area of the controller chip is smaller than that of the nonvolatile semiconductor storage chip,
wherein the controller chip is arranged over the nonvolatile semiconductor storage chip,
wherein pads of the controller chip are provided along a first short side or a second long side of the rectangular shape of the nonvolatile semiconductor storage chip and coupled to pads of the wiring board provided along the first short side or the second long side via wires,
wherein area of the power supply interrupting semiconductor chip is smaller than that of the nonvolatile semiconductor storage chip,
wherein the power supply interrupting semiconductor chip is arranged over the nonvolatile semiconductor storage chip, and
wherein pads of the power supply interrupting semiconductor chip are provided along the first long side of the rectangular shape of the nonvolatile semiconductor storage chip and coupled to pads over the wiring board provided along the first long side via wires.
11. The semiconductor device according to claim 10,
wherein the power supply interrupting semiconductor chip is provided between the pads of the wiring board provided along the first long side of the rectangular shape of the nonvolatile semiconductor storage chip and the first semiconductor chip,
wherein each of the first semiconductor chip and the power supply interrupting semiconductor chip has a rectangular shape, and
wherein one side of the rectangular shape of the first semiconductor chip facing the first long side of the rectangular shape of the nonvolatile semiconductor storage chip is longer than one side of the power supply interrupting semiconductor chip facing the first long side of the nonvolatile semiconductor storage chip.