Author: claimsbot

1. A system for detecting neutron radiation, comprising:
a neutron detector array comprising:
a two-dimensional array of microbolometer detectors comprising sensing elements responsive to heat;
a plurality of particle capture layers, each particle capture layer coupled to a different microbolometer detector of the two-dimensional array of microbolometer detectors, each particle capture layer configured to capture energetic particles and convert kinetic energy from the energetic particles to heat;
a plurality of neutron sensitive layers, each neutron sensitive layer coupled to a different particle capture layer and configured to react with incident neutrons to form energetic particles; and
a plurality of heat barriers, each heat barrier coupled to a different neutron sensitive layer and configured to reflect at least a portion of incident radiant heat;

a readout circuit coupled to the neutron detector array, the readout circuit configured to generate a plurality of response values from the two-dimensional array of microbolometer detectors; and
a processor coupled to the readout circuit, the processor configured to:
generate a comparison value based on the plurality of response values and a baseline response value; and
determine whether more than a first threshold amount of neutron radiation has been detected by the neutron detector array.
2. A method for detecting neutron radiation, comprising:
exposing a neutron detector array comprising at least one two-dimensional array of neutron detectors to a first scene of interest, the neutron detector array based on at least one two-dimensional array of microbolometer detectors;
receiving a plurality of response values from a corresponding plurality of neutron detectors of the neutron detector array;
generating a comparison value based on the plurality of response values and a baseline response value; and
determining whether more than a first threshold amount of neutron radiation is being generated by the first scene based on the comparison value.
3. The method of claim 2, wherein generating a comparison value based on the plurality of response values and a baseline response value comprises:
averaging the plurality of response values from the plurality of neutron detectors; and
comparing the average response to the baseline response value.
4. The method of claim 2, wherein generating a comparison value based on the plurality of response values and a baseline response value comprises:
adjusting each response value by a baseline response value;
generating a plurality of adjusted response values based on the adjustment to each response value;
averaging the adjusted response values; and
comparing the average response to a threshold response value.
5. The method of claim 2, further comprising determining the baseline response value from one or more previously received response values from a corresponding plurality of neutron detectors of the neutron detector array.
6. The method of claim 2, further comprising determining the baseline response value from one or more response values from one or more reference microbolometer detectors, the one or more reference microbolometers party of the at least one two-dimensional array of microbolometer detectors.
7. The method of claim 2, wherein exposing a neutron detector array comprising a two-dimensional array of neutron detectors to a first scene of interest comprises exposing the neutron detector array comprising a two-dimensional array of neutron detectors to a first scene of interest, each neutron detector comprising:
a heat barrier configured to reflect at least a portion of incident radiant heat;
a neutron sensitive layer configured to react with incident neutrons to form energetic particles;
a particle capture layer configured to capture energetic particles and convert kinetic energy from the energetic particles to heat; and
a microbolometer sensing element responsive to the heat.
8. The method of claim 2, further comprising, upon determining that more than the first threshold amount of neutron radiation is being generated by the first scene, generating a warning signal indicating that more than the first threshold amount of neutron radiation has been detected.
9. The method of claim 2:
wherein exposing a neutron detector array to a first scene of interest comprises exposing a neutron detector array comprising two or more two-dimensional arrays of neutron detectors to a first scene of interest; and
further comprising, upon determining that more than the first threshold amount of neutron radiation is being generated by the first scene:
determining which two-dimensional array of neutron detectors provided the comparison value indicating that more than the first threshold amount of neutron radiation is being generated by the first scene; and
generating a warning signal indicating that more than the first threshold amount of neutron radiation has been detected and indicating which two-dimensional array of neutron detectors detected the more than the first threshold amount of neutron radiation.
10. A system for detecting neutron radiation, comprising:
a neutron detector array comprising at least one two-dimensional array of neutron detectors based on at least one two-dimensional array of microbolometer detectors, the neutron detector array configured to be exposed to a first scene;
a readout circuit coupled to the neutron detector array, the readout circuit configured to generate a plurality of response values from a corresponding plurality of neutron detectors of the neutron detector array; and
a processor coupled to the readout circuit, the processor configured to:
generate a comparison value based on the plurality of response values and a baseline response value; and
determine whether more than a first threshold amount of neutron radiation is being generated by the first scene based on the comparison value.
11. The system of claim 10, wherein each neutron detector of the two-dimensional array of neutron detectors comprises:
a heat barrier configured to reflect at least a portion of incident radiant heat;
a neutron sensitive layer configured to react with incident neutrons to form energetic particles;
a particle capture layer configured to capture energetic particles and convert kinetic energy from the energetic particles to heat; and
a microbolometer sensing element responsive to the heat.
12. The system of claim 10, wherein the neutron detector array comprises two or more two-dimensional arrays of neutron detectors, each of the two or more two-dimensional arrays aligned in a different direction.
13. The system of claim 12, wherein the processor is further configured to:
determine a direction the more than a first threshold amount of neutron radiation is being generated; and
generate a warning signal indicating the direction from which the more than a first threshold amount neutron radiation is being generated.
14. The system of claim 10, wherein the neutron detector array comprises two or more two-dimensional arrays of neutron detectors, each of the two or more two-dimensional arrays arranged in a stack aligned in a same direction.
15. The system of claim 10, wherein the processor is further configured to:
average the plurality of response values from the readout circuit; and
compare the average response to the baseline response value.
16. The system of claim 10, wherein the processor is further configured to:
adjust each response value by a baseline response value;
generate a plurality of adjusted response values based on the adjustment to each response value;
average the adjusted response values; and
compare the average response to a threshold response value.
17. One or more computer-readable non-transitory storage media embodying software that when executed by a processor is configured to:
expose a neutron detector array comprising at least one two-dimensional array of neutron detectors to a first scene of interest, the neutron detector array based on at least one two-dimensional array of microbolometer detectors;
receive a plurality of response values from a corresponding plurality of neutron detectors of the neutron detector array;
generate a comparison value based on the plurality of response values and a baseline response value; and
determine whether more than a first threshold amount of neutron radiation is being generated by the first scene based on the comparison value.
18. The media of claim 17, wherein the software configured to generate a comparison value based on the plurality of response values and a baseline response value is further configured to:
average the plurality of response values from the plurality of neutron detectors; and
compare the average response to the baseline response value.
19. The media of claim 17, wherein the software configured to generate a comparison value based on the plurality of response values and a baseline response value is further configured to:
adjust each response value by a baseline response value;
generate a plurality of adjusted response values based on the adjustment to each response value;
average the adjusted response values; and
compare the average response to a threshold response value.
20. The media of claim 17, wherein the software is further configured to determine the baseline response value from one or more previously received response values from a corresponding plurality of neutron detectors of the neutron detector array.
21. The media of claim 17, wherein the software configured to expose a neutron detector array comprising a two-dimensional array of neutron detectors to a first scene of interest is further configured to expose the neutron detector array comprising a two-dimensional array of neutron detectors to a first scene of interest, each neutron detector comprising:
a heat barrier configured to reflect at least a portion of incident radiant heat;
a neutron sensitive layer configured to react with incident neutrons to form energetic particles;
a particle capture layer configured to capture energetic particles and convert kinetic energy from the energetic particles to heat; and
a microbolometer sensing element responsive to the heat.
22. The media of claim 17, wherein the software is further configured to, upon determining that more than the first threshold amount of neutron radiation is being generated by the first scene, generate a warning signal indicating that more than the first threshold amount of neutron radiation has been detected.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed:

1. A method for making a series of cuts at different angles in one or more panels using a panel sawing machine comprising the following steps:
placing a stack of one or more panels on a worktable having a cutting line for a panel sawing machine;
turning the panel stack a first time in a first rotation direction;
making a first series of cuts in the panel stack;
turning the panel stack a second time; and
making a second series of cuts in the panel stack;
wherein the second rotation occurs in a direction opposite the first direction and wherein, during the second rotation, the panel stack is moved closer to the cutting line.
2. The method according to claim 1, wherein the step of turning the panel stack the second time in turn comprises the following steps:
rotatably securing a pickup element to the panel stack at a corner portion located close to the cutting line, the panel stack being substantially rectangular in shape; and
moving the pickup element away from the cutting line.
3. The method according to claim 2, wherein the step of moving the pickup element away from the cutting line is carried out by moving the pickup element along a first guide following a first, straight path that is transversal to the cutting line.
4. The method according to claim 3, wherein said straight path is substantially perpendicular to the cutting line.
5. The method according to claim 3 or 4, wherein the step of turning the panel stack the second time in turn comprises the following steps:
abutting a push element against a portion of the side of the panel stack close to the first guide, the portion being located further away from the cutting line than the corner portion; and
moving the push element away from the first guide.
6. The method according to claim 5, wherein the step of moving the push element away from the first guide is carried out by moving the push element along a second guide following a second path that is substantially perpendicular to the first path.
7. The method according to claim 5 or 6, wherein the steps of moving the push element away from the first guide and moving the pickup element away from the cutting line are simultaneous andor sequential.
8. The method according to claim 1, wherein the step of turning the panel stack for the second time causes it to turn by approximately 90 degrees.
9. A device for making a series of cuts at different angles in one or more panels using a panel sawing machine that comprises:
a worktable for a stack of one of more panels, said worktable having at least one cutting line for a panel sawing machine;
first handling means working in conjunction with the worktable to turn the panel stack about the cutting line in a first rotation direction and in a second rotation direction;
a push carriage operating on the worktable to move the panel stack to the cutting line when the panel stack has to be cut;
wherein the first handling means comprise:
a first guide extending crossways on the worktable, preferably perpendicularly to the cutting line;
a second guide extending on the worktable in a direction substantially perpendicular to the first guide;
a pickup element that moves along the first guide;
a push element that moves along the second guide.
10. The device according to claim 9, wherein the pickup element comprises a gripper with two jaws, each jaw having a supporting portion and an active portion designed to engage the panel stack on the support portion.
11. The device according to the previous claim, wherein the active portions of the jaws are mounted on the supporting portions in such a way that they can turn freely.
12. The device according to claim 10 or 11, wherein the pickup element comprises a pneumatic system that operates between the first and second jaws so as to tighten the gripper on the panel stack.
13. The device according to claim 12, wherein the pneumatic system comprises a piston attached to the second jaw and a cylinder attached to the first jaw.
14. The device according to any of the foregoing claims from 9 to 13, wherein the guide comprises a mounting beam extending crossways, in a direction preferably perpendicular to the cutting line, and a rack connected to the mounting beam.
15. The device according to claim 14, wherein the pickup element comprises a motor and a toothed wheel, the toothed wheel being meshed with the rack and being driven by the motor.
16. The device according to any of the foregoing claims from 9 to 15, comprising a bed over which the worktable is positioned, and a fence connected to the bed.
17. The device according to claim 16, wherein the fence moves between an idle position under the worktable, and a working position 10 above the worktable.
18. The device according to claim 17, wherein the fence comprises a first arm and a second arm perpendicular to the first arm, the first arm being hinged, at a first end, to the bed 45, and the second arm being rigidly connected to the second end of the first arm.
19. The device according to claim 17, wherein the fence comprises a lever having a first end hinged to the bed, a central portion and a second end that abuts against the first arm.
20. The device according to claim 19, comprising a control piston that operates between the bed and the central portion of the lever.

1. A method of determining access node capacity, comprising:
determining a first throughput of information received from a first access node at an application running on a wireless device;
determining a second throughput of information received from a second access node at the application running on the wireless device, wherein the first access node does not receive capacity information from the second access node;
identifying unique modulation and coding schemes (MCS’) assigned to the wireless device for communication with the respective first and second access nodes;
estimating a number of free physical resource blocks per frame of the first access node and of the second access node based on the respective first and second throughputs of information and based on the identified MCS’ assigned to the wireless device for communication with each of the first and second access nodes; and,
based on the estimated number of free physical resource blocks per frame of the first access node and of the second access node, instructing the wireless device to change from communicating with the first access node to communicating with the second access node.
2. The method of claim 1, wherein the first throughput of information received at the application running on the wireless device is associated with a lowest traffic class indicator from among a plurality of traffic class indicators.
3. The method of claim 1, further comprising:
changing the MCS assigned to the wireless device for communication with the first access node to a second MCS;
determining a third throughput of the information received from the first access node at the application running on the wireless device; and
estimating, based on the third determined throughput of information, a second number of free physical resource blocks per frame of the first access node based on the second MCS and the third throughput.
4. The method of claim 3, further comprising determining a total number of free physical resource blocks per frame of the first access node based on the estimated number of free physical resource blocks per frame of the first access node.
5. The method of claim 1, further comprising:
instructing the wireless device to change from communicating with the first access node to the second access node when the estimated number of free physical resource blocks per frame of the first access node and of the second access node indicate that the second access node has a greater capacity than the first access node.
6. The method of claim 1, wherein the second throughput of information received from the second access node at the application running on the wireless device comprises test data sent from the first access node to the wireless device.
7. A method of determining access node capacity, comprising:
determining a first throughput of information received from a first access node at an application running on a first wireless device;
determining a second throughput of information received from a second access node at an application running on a second wireless device, wherein the first access node does not receive capacity information from the second access node;
identifying a modulation and coding scheme (MCS) assigned to the first wireless device for communication with the first access node;
identifying a MCS assigned to the second wireless device for communication with second access node;
estimating a number of free physical resource blocks per frame of the first access node based on the first throughput of information and the MCS assigned to the first wireless device, and a number of free physical resource blocks per frame of the second access node based on the second throughput of information and the MCS assigned to the second wireless device; and
based on the estimated number of free physical resource blocks per frame of the respective first and second access nodes, instructing the first wireless device to change from communicating with the first access node to communicating with the second access node.
8. The method of claim 7, further comprising:
instructing the first wireless device to change from communicating with the first access node to communicating with the second access node when the estimated number of free physical resource blocks per frame of the first access node and of the second access node indicate that the second access node has a greater capacity than the first access node.
9. The method of claim 7, wherein the first throughput of information received from the first access node at the first wireless device and the second throughput of information received from the second access node at the second wireless device are each associated with a lowest traffic class indicator from among a plurality of traffic class indicators.
10. The method of claim 7, further comprising:
determining a third throughput of information received from the first access node at an application running on a third wireless device;
identifying a MCS assigned to the third wireless device for communication with the first access node, wherein the MCS assigned to the third wireless device is different than the MCS assigned to the first wireless device;
determining a fourth throughput of information received from the second access node at an application running on a fourth wireless device;
identifying a MCS assigned to the fourth wireless device for communication with the second access node, wherein the MCS assigned to the fourth wireless device is different than the MCS assigned to the second wireless device;
estimating the number of free physical resource blocks per frame of the first access node based on the first throughput of information received at the first wireless device, the MCS assigned to the first wireless device, the third throughput of information received at the third wireless device, and the MCS assigned to the third wireless device; and
estimating the number of free physical resource blocks per frame of the second access node based on the second throughput of information received at the second wireless device, the MCS assigned to the second wireless device, the fourth throughput of information received at the fourth wireless device, and the MCS assigned to the fourth wireless device.
11. The method of claim 7, further comprising:
determining a third throughput of information received from a third access node at an application running on a third wireless device;
identifying a MCS assigned to the third wireless device for communication with third access node; and
estimating a number of free physical resource blocks per frame of the third access node based on the third throughput of information and the MCS assigned to the third wireless device, and
wherein the first and second access nodes do not receive capacity information from the third access node.
12. The method of claim 11, further comprising:
instructing the first wireless device to change from communicating with the first access node to communicating with the third access node based on the estimated number of free physical resource blocks per frame of the first access node, the second access node, and the third access node.
13. The method of claim 11 further comprising:
instructing the first wireless device to change from communicating with the first access node access to communicating with the third access node when the estimated number of free physical resource blocks per frame of the first access node, the second access node, and the third access node indicate that the third access node has a greater capacity than the first and second access nodes.
14. The method of claim 12, wherein the first throughput of information received from the first access node, the second throughput of information received from the second access node, and the third throughput of information received from the third access node are each associated with a lowest traffic class indicator from among a plurality of traffic class indicators.
15. The method of claim 11, further comprising:
estimating the number of free physical resource blocks per frame of the first access node, the second access node, and the third access node at a predetermined time based on historical capacity information of the first access node.
16. The method of claim 11, further comprising:
estimating the number of free physical resource blocks per frame of the first access node, the second access node, and third access node at a predetermined time based on historical capacity information of the first access node, the second access node, and third access node.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An integrated circuit device comprising:
a memory cell consisting essentially of an electrically floating body transistor, wherein the electrically floating body transistor comprises:
a source region;
a drain region;
a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and
a gate disposed over the body region;

circuitry, coupled to the memory cell, to write a data state into the memory cell and to read the data state of the memory cell;
wherein, in response to write control signals applied to the electrically floating body transistor, the electrically floating body transistor stores a charge which is representative of a data state of the memory cell in the body region of the electrically floating body transistor; and
wherein, in response to read control signals applied to the electrically floating body transistor, the electrically floating body transistor generates a bipolar transistor current which is representative of the data state of the memory cell and wherein the circuitry determines the data state of the memory cell based on a signal which is representative of the bipolar transistor current of the electrically floating body transistor.
2. The integrated circuit device of claim 1 wherein electrically floating body transistor is an N-channel type transistor or a P-channel type transistor.
3. The integrated circuit device of claim 1 wherein electrically floating body transistor is non-symmetrical.
4. The integrated circuit device of claim 1 wherein the read control signals include signals applied to the gate, source region, and drain region to cause, force andor induce the bipolar transistor current which is representative of the data state of the memory cell.
5. The integrated circuit device of claim 4 wherein the read control signals include a positive voltage pulse which is applied to the drain region of the electrically floating body transistor and wherein the circuitry is connected to the drain region via a bit line.
6. The integrated circuit device of claim 4 wherein the read control signals include a negative voltage pulse which is applied to the drain region of the electrically floating body transistor and wherein the circuitry is connected to the drain region via a bit line.
7. The integrated circuit of claim 1 wherein, if the memory cell stores a logic low, the electrically floating body transistor, in response to the read control signals applied thereto, generates a bipolar transistor current equal to or substantially equal to zero.
8. The integrated circuit of claim 1 wherein the signal which is representative of the bipolar transistor current of the electrically floating body transistor is a voltage amplitude.
9. An integrated circuit device comprising:
a memory cell consisting essentially of an electrically floating body transistor, wherein the electrically floating body transistor comprises of:
a first region having impurities to provide a first conductivity type;
a second region having impurities to provide the first conductivity type;
a body region disposed between the first region and the second region wherein the body region is electrically floating and includes impurities to provide a second conductivity type wherein the second conductivity type is different from the first conductivity type; and
a gate disposed over the body region;

circuitry, coupled to the memory cell, to write a data state into the memory cell and to read the data state of the memory cell;
wherein, in response to the write control signals applied to the electrically floating body transistor, the electrically floating body transistor stores a charge which is representative of the data state in the body region of the electrically floating body transistor; and
wherein, in response to the read control signals, the electrically floating body transistor generates a bipolar transistor current which is representative of the data state of the memory cell and wherein the circuitry determines the data state of the memory cell based on a signal which is representative of the bipolar transistor current of the electrically floating body transistor.
10. The integrated circuit device of claim 9 wherein electrically floating body transistor is an N-channel type transistor or a P-channel type transistor.
11. The integrated circuit device of claim 9 wherein electrically floating body transistor is non-symmetrical.
12. The integrated circuit device of claim 9 wherein the read control signals include signals applied to the gate, first region, and second region to cause, force andor induce the bipolar transistor current which is representative of the data state of the memory cell.
13. The integrated circuit device of claim 12 wherein the read control signals include a positive voltage pulse which is applied to the second region of the electrically floating body transistor and wherein circuitry is connected to the second region via a bit line.
14. The integrated circuit device of claim 12 wherein the read control signals include a negative voltage pulse which is applied to the second region of the electrically floating body transistor and wherein the circuitry is connected to the second region via a bit line.
15. The integrated circuit of claim 9 wherein, if the memory cell stores a logic low, the electrically floating body transistor, in response to the read control signals applied thereto, generates a bipolar transistor current equal to or substantially equal to zero.
16. The integrated circuit of claim 9 wherein the signal which is representative of the bipolar transistor current of the electrically floating body transistor is a voltage amplitude.
17. An integrated circuit device comprising:
a memory cell consisting essentially of an electrically floating body transistor, wherein the electrically floating body transistor is disposed in or on a semiconductor region or layer which resides on or above an insulating region or layer of a substrate, the electrically floating body transistor comprises:
a source region having impurities to provide a first conductivity type;
a drain region having impurities to provide the first conductivity type,
a body region disposed between the source region, the drain region and the insulating region or layer of the substrate, wherein the body region is electrically floating and includes impurities to provide a second conductivity type wherein the second conductivity type is different from the first conductivity type; and
a gate spaced apart from the body region;

circuitry, coupled to the memory cell, to (i) read a data state of the memory cell and (ii) generate and apply read control signals to the electrically floating body transistor; and
wherein, in response to the read control signals, the electrically floating body transistor generates a bipolar transistor current which Is representative of the data state of the memory cell and wherein the circuitry determines the data state of the memory cell based on a signal which is representative of the bipolar transistor current of the electrically floating body transistor.
18. The integrated circuit device of claim 17 wherein electrically floating body transistor is an N-channel type transistor or a P-channel type transistor.
19. The integrated circuit device of claim 17 wherein electrically floating body transistor is non-symmetrical.
20. The integrated circuit device of claim 17 wherein the read control signals include signals applied to the gate, source region, and drain region to cause, force andor induce the bipolar transistor current which is representative of the data state of the memory cell.
21. The integrated circuit device of claim 20 wherein the read control signals include a positive voltage pulse which is applied to the drain region of the electrically floating body transistor and wherein the circuitry is connected to the drain region via a bit line.
22. The integrated circuit device of claim 20 wherein the read control signals include a negative voltage pulse which is applied to the drain region of the electrically floating body transistor and wherein the circuitry is connected to the drain region via a bit line.
23. The integrated circuit of claim 17 wherein, if the memory cell stores a logic low, the electrically floating body transistor, in response to the read control signals applied thereto, generates a bipolar transistor current equal to or substantially equal to zero.
24. The integrated circuit of claim 17 wherein the signal which is representative of the bipolar transistor current of the electrically floating body transistor is a voltage amplitude.
25. A method of operating an integrated circuit device having a memory cell comprising an electrically floating body transistor, wherein the electrically floating body transistor comprises: (i) a source region, (ii) a drain region, (iii) a body region disposed between the source region and the drain region, wherein the body region is electrically floating, and (iv) a gate disposed over the body region, the method comprises:
applying read control signals to the electrically floating body transistor of the memory cell, wherein, in response to the read control signals, the electrically floating body transistor generates a bipolar transistor current which is representative of a data state of stored in the memory cell;
generating a voltage, having an amplitude, using the bipolar transistor current;
determining the data state of the memory cell based on the amplitude of the voltage which is representative of an amount of the bipolar transistor current generated by the electrically floating body transistor; and
outputting the data state of the memory cell.
26. The method of claim 25 further including applying write control signals to the electrically floating body transistor of the memory cell, wherein in response to the write control signals the electrically floating body transistor stores a charge which is representative of a data state in the body region of the electrically floating body transistor.
27. The method of claim 25 wherein the read control signals include a positive voltage pulse which is applied to the drain region of the electrically floating body transistor.
28. The method of claim 25 wherein the read control signals include a negative voltage pulse which is applied to the drain region of the electrically floating body transistor.
29. The method of claim 25 wherein, if the memory cell stores a logic low, the electrically floating body transistor, in response to the read control signals, generates a bipolar transistor current equal to or substantially equal to zero.
30. A method of operating an integrated circuit device having a memory cell comprising an electrically floating body transistor, wherein the electrically floating body transistor comprises: (i) a source region, (ii) a drain region, (iii) a body region disposed between the source region and the drain region, wherein the body region is electrically floating, and (iv) a gate disposed over the body region, the method comprises:
applying write control signals to the electrically floating body transistor of the memory cell, wherein, in response to the write control signals, the electrically floating body transistor stores a charge which is representative of a data state in the body region of the electrically floating body transistor; and
applying read control signals to the electrically floating body transistor of the memory cell, wherein, in response to the read control signals, the electrically floating body transistor generates a bipolar transistor current which is representative of a data state of stored in the memory cell.
31. The method of claim 30 wherein the read control signals include a positive or negative voltage pulse which is applied to the drain region of the electrically floating body transistor.
32. The method of claim 30 further including:
generating a voltage, having an amplitude, using the bipolar transistor current generated by the electrically floating body transistor in response to the read control signals;
determining the data state of the memory cell based on the amplitude of the voltage; and
outputting the data state of the memory cell.
33. The method of claim 32 wherein, if the memory cell stores a logic low, the electrically floating body transistor, in response to the read control signals, generates a bipolar transistor current equal to or substantially equal to zero.