Author: claimsbot

1. A current feedback amplifier circuit, comprising:
a first input buffer (406a) that provides a first non-inverting input (IN+A) of the amplifier circuit, provides a first inverting input (IN\u2212A) of the amplifier circuit, and produces a first plurality of currents;
a second input buffer (406b) that provides a second non-inverting input (IN+B) of the amplifier circuit, provides a second inverting input (IN\u2212B) of the amplifier circuit, and produces a second plurality of currents;
first and second high impedance nodes (414a and 414b);
a plurality of current mirrors to provide currents, proportional to sums of specific currents of the first and second plurality of currents, to the high impedance nodes;
a first output buffer (408a) having an input connected to the first high impedance node (414a), and having an output that provides a first output (OUTA) of the amplifier circuit; and
a second output buffer (408b) having an input connected to the second high impedance node (414b), and having an output that provides a second output (OUTB) of the amplifier circuit;
wherein the first plurality of currents are proportional to a difference between an input voltage provided to the first non-inverting input (IN+A) of the amplifier circuit and a fraction of its associated output voltage at the first output (OUTA); and
wherein the second plurality of currents are proportional to a difference between an input voltage provided to the second non-inverting input (IN+B) of the amplifier circuit and a fraction of its associated output voltage at the second output (OUTB).
2. The amplifier circuit of claim 1, wherein a feedback resistor connects the first output (OUTA) of the amplifier circuit to the first inverting input (IN\u2212A) of the amplifier circuit.
3. The amplifier circuit of claim 2, wherein a second feedback resistor connects the second output (OUTB) of the amplifier circuit to the second inverting input (IN\u2212B) of the amplifier circuit.
4. The amplifier circuit of claim 3, wherein the first non-inverting input (IN+A) is connected to the second non-inverting input (IN+B).
5. The amplifier circuit of claim 1, wherein the first non-inverting input (IN+A) is connected to the second non-inverting input (IN+B).
6. A current feedback amplifier circuit, comprising:
an input buffer (406a) that provides a non-inverting input (IN+A) of the amplifier circuit, provides an inverting input (IN\u2212A) of the amplifier circuit, and produces a plurality of currents;
first and second high impedance nodes (414a and 414b);
a first plurality of current mirrors that provides mirrored versions of specific ones of the plurality of currents to the first high impedance node (414a);
a second plurality of current mirrors that provides mirrored versions of specific ones of the plurality of currents to the second high impedance node (414b);
a first output buffer (408a) having an input connected to the first high impedance node (414a), and having an output that provides a first output (OUTA) of the amplifier circuit; and
a second output buffer (408b) having an input connected to the second high impedance node (414b), and having an output that provides a second output (OUTB) of the amplifier circuit;
wherein the plurality of currents are proportional to a difference between an input voltage provided to the non-inverting input (IN+A) of the amplifier circuit and a fraction of its associated output voltage at the first output (OUTA).
7. The amplifier circuit of claim 6, wherein a feedback resistor connects the first output (OUTA) of the amplifier circuit to the inverting input (IN\u2212A) of the amplifier circuit.
8. The amplifier circuit of claim 7, wherein a second feedback resistor connects the second output (OUTB) of the amplifier circuit to the inverting input (IN\u2212A) of the amplifier circuit.
9. A current feedback amplifier circuit, comprising:
a first input buffer (906a) that provides a non-inverting input (IN+A) of the amplifier circuit, provides an inverting input (IN\u2212A) of the amplifier circuit, and produces a first plurality of currents;
a second input buffer (906b) that provides a second non-inverting input (IN+B) of the amplifier circuit, provides a second inverting input (IN\u2212B) of the amplifier circuit, and produces a second plurality of currents;
first and second high impedance nodes 914a and 914b;
a first output buffer (908a) having an input connected to the first high impedance node (914a), and having an output that provides a first output (OUTA) of the amplifier circuit; and
a second output buffer (908b) having an input connected to the second high impedance node (914b), and having an output the provides a second output (OUTB) of the amplifier circuit;
a first plurality of current mirrors each of which includes at least one corresponding input and at least two corresponding outputs; and
a second plurality of current mirrors each of which includes at least one corresponding input and at least two corresponding outputs;
wherein two of the outputs of the first plurality of current mirrors are connected to the first high impedance node (914a);
wherein two of the outputs of the second plurality of current mirrors are connected to the second high impedance node (914b);
wherein each of the first plurality of current mirrors receives at one or more input of the current mirror one of the first plurality of currents and a current output by one of the outputs of one of the second plurality of current mirrors; and
wherein each of the second plurality of current mirrors receives at one or more input of the current mirror one of the second plurality of currents and a current output by the one of the outputs of one of the first plurality of current mirrors.
10. The amplifier circuit of claim 9, wherein:
the first plurality of currents are proportional to a difference between an input voltage provided to the first non-inverting input (IN+A) of the amplifier circuit and a fraction of its associated output voltage at the first output (OUTA); and
the second plurality of current are proportional to a difference between an input voltage provided to the second non-inverting input (IN+B) of the amplifier circuit and a fraction of its associated output voltage at the second output (OUTB).
11. The amplifier circuit of claim 10, wherein for each of the first and second plurality of current mirrors, one of the outputs of the current mirror has a lower current gain than another one of the outputs.
12. The amplifier circuit of claim 9, wherein for each of the first and second plurality of current mirrors, one of the outputs of the current mirror has a lower current gain than another one of the outputs.
13. A current feedback amplifier circuit, comprising:
a first input buffer (1106a) that provides a first DM input (IN+DM) of the amplifier circuit, provides a first feedback node (FB+) of the amplifier circuit, and produces a first plurality of currents;
a second input buffer (1106b) that provides a second DM input (IN\u2212DM) of the amplifier circuit, provides a second feedback node (FB\u2212) of the amplifier circuit, and produces a second plurality of currents;
a third input buffer (1106c) that provides a CM input (IN_CM) of the amplifier circuit, has an output (1104c), and produces a third plurality of currents;
first and second high impedance nodes (1114a and 1114b);
a first output buffer (1108a) having an input connected to the first high impedance node (1114a), and having an output that provides a first output (OUTA) of the amplifier circuit;
a second output buffer (1108b) having an input connected to the second high impedance node (1114b), and having an output that provides a second output (OUTB) of the amplifier circuit;
a first plurality of current mirrors each of which includes at least one corresponding input and at least two corresponding outputs; and
a second plurality of current mirrors each of which includes at least one corresponding input and at least two corresponding outputs;
wherein each of the first plurality of current mirrors receives one of the first plurality of currents and one of the third plurality of currents at one or more input of the current mirror, has one of the second plurality of currents drawn from one of its outputs, and has a further one of its outputs connected to the first high impedance node (1114a); and
wherein each of the second plurality of current mirrors receives one of the second plurality of currents and one of the third plurality of currents at one or more input of the current mirror, has one of the first plurality of currents drawn from one of its outputs, and has a further one of its outputs connected to the second high impedance node (1114b).
14. The amplifier circuit of claim 13, wherein:
the first plurality of currents are proportional to a difference between an input voltage provided to the first DM input (IN+DM) of the amplifier circuit and a fraction of its associated output voltage at the first output (OUTA);
the second plurality of currents are proportional to a difference between an input voltage provided to the second DM input (IN\u2212DM) of the amplifier circuit and a fraction of its associated output voltage at the second output (OUTB); and
the third plurality of currents are proportional to a difference between an input voltage provided to the CM input (IN_CM) of the amplifier circuit and a fraction of its associated output voltage at the output (1104c) of the third input buffer (1106c).
15. The amplifier circuit of claim 14, wherein:
a first feedback resistor connects the first output (OUTA) of the amplifier circuit to the first feedback node (FB+) of the amplifier circuit;
a second feedback resistor connects the second output (OUTB) of the amplifier circuit to the second feedback node (FB\u2212) of the amplifier circuit;
a third feedback resistor connects the first output (OUTA) of the amplifier circuit to the output (1104c) of the third input buffer (1106c); and
a fourth feedback resistor connects the second output (OUTB) of the amplifier circuit to the output (1104c) of the third input buffer (1106c).
16. The amplifier circuit of claim 13, wherein:
a first feedback resistor connects the first output (OUTA) of the amplifier circuit to the first feedback node (FB+) of the amplifier circuit;
a second feedback resistor connects the second output (OUTB) of the amplifier circuit to the second feedback node (FB\u2212) of the amplifier circuit;
a third feedback resistor connects the first output (OUTA) of the amplifier circuit to the output (1104c) of the third input buffer (1106c); and
a fourth feedback resistor connects the second output (OUTB) of the amplifier circuit to the output (1104c) of the third input buffer (1106c).
17. A current feedback amplifier circuit, comprising:
a first input buffer (806a or 1106a) that provides a first DM input (IN+DM) of the amplifier circuit, provides a first feedback node (FB+) of the amplifier circuit, and produces a first plurality of currents;
a second input buffer (806a or 1106b) that provides a second DM input (IN\u2212DM) of the amplifier circuit, provides a second feedback node (FB\u2212) of the amplifier circuit, and produces a second plurality of currents;
a third input buffer (806c or 1106c) that provides a CM input (IN_CM) of the amplifier circuit, has an output (804c or 1104c), and produces a third plurality of currents;
first and second high impedance nodes (814a or 1114a, and 814b or 1114b);
a first output buffer (808a or 1108a) having an input connected to the first high impedance node (814b or 1114a), and having an output that provides a first output (OUTA) of the amplifier circuit;
a second output buffer (808b or 1108b) having an input connected to the second high impedance node (814b or 1114b), and having an output that provides a second output (OUTB) of the amplifier circuit;
a first plurality of current mirrors each of which includes at least one corresponding input and at least one corresponding output;
a second plurality of current mirrors each of which includes at least one corresponding input and at least one corresponding output;
wherein two outputs, of the first plurality of current mirrors, are connected to the first high impedance node (814a or 1114a);
wherein two outputs, of the second plurality of current mirrors, are connected to the second high impedance node (814b or 1114b);
wherein each of the first plurality of current mirrors, or each of a pair of the first plurality of current mirrors, receives one of the first plurality of currents and one of the third plurality of currents at one or more input, and has one of the second plurality of currents drawn from one of its outputs; and
wherein each of the second plurality of current mirrors, or each of a pair of the second plurality of current mirrors, receives one of the second plurality of currents and one of the third plurality of currents at one or more input, and has one of the first plurality of currents drawn from one of its outputs.
18. The amplifier circuit of claim 17, wherein:
the first plurality of currents are proportional to a difference between an input voltage provided to the first DM input (IN+DM) of the amplifier circuit and a fraction of its associated output voltage at the first output (OUTA);
the second plurality of currents are proportional to a difference between an input voltage provided to the second DM input (IN\u2212DM) of the amplifier circuit and a fraction of its associated output voltage at the second output (OUTB); and
the third plurality of currents are proportional to a difference between an input voltage provided to the CM input (IN_CM) of the amplifier circuit and a fraction of its associated output voltage at the output (804c or 1104c) of the third input buffer (1106c).
19. The amplifier circuit of claim 18, wherein:
a first feedback resistor connects the first output (OUTA) of the amplifier circuit to the first feedback node (FB+) of the amplifier circuit;
a second feedback resistor connects the second output (OUTB) of the amplifier circuit to the second feedback node (FB\u2212) of the amplifier circuit;
a third feedback resistor connects the first output (OUTA) of the amplifier circuit to the output (804c or 1104c) of the third input buffer (806c or 1106c); and
a fourth feedback resistor connects the second output (OUTB) of the amplifier circuit to the output (804c or 1104c) of the third input buffer (806c or 1106c).
20. The amplifier circuit of claim 17, wherein:
a first feedback resistor connects the first output (OUTA) of the amplifier circuit to the first feedback node (FB+) of the amplifier circuit;
a second feedback resistor connects the second output (OUTB) of the amplifier circuit to the second feedback node (FB\u2212) of the amplifier circuit;
a third feedback resistor connects the first output (OUTA) of the amplifier circuit to the output (804c or 1104c) of the third input buffer (806c or 1106c); and
a fourth feedback resistor connects the second output (OUTB) of the amplifier circuit to the output (804c or 1104c) of the third input buffer (806c or 1106c).

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1-259. (canceled)
260. Apparatus for spraying a liquid onto at least one vehicle surface comprising:
a liquid reservoir;
a vehicle surface liquid heating assembly receiving a liquid from said liquid reservoir, said vehicle surface liquid heating assembly comprising:
a heat-conductive element; and
a liquid heating enclosure defining a liquid heating volume including a primary liquid heating volume portion and a secondary liquid heating volume portion, separated by said heat-conductive element, said primary liquid heating volume portion including a heat exchanger for directly heating liquid in said primary liquid heating volume portion and for indirectly heating liquid in said secondary liquid heating volume portion via said heat-conductive element;

a vehicle surface liquid spraying assembly receiving heated liquid from said vehicle surface liquid heating assembly; and
a heated liquid spray control subassembly employing said vehicle surface liquid heating assembly and said vehicle surface liquid spraying assembly for providing a spray of said heated liquid onto said at least one vehicle surface.
261. Apparatus according to claim 260 and wherein said heat-conductive element comprises a displaceable, resilient, flexible element.
262. Apparatus according to claim 260 and wherein said heat-conductive element forms at least a wall both of said primary liquid heating volume portion and of said secondary liquid heating volume portion.
263. Apparatus according to claim 260 and wherein at least said liquid heating enclosure defines a primary liquid flow pathway in said primary liquid heating volume portion and a secondary liquid flow pathway in said secondary liquid heating volume portion, said secondary liquid flow pathway supplying liquid to said primary liquid flow pathway.
264. Apparatus according to claim 260 and wherein said primary liquid heating volume portion is formed of a relatively rigid, highly heat conductive material.
265. Apparatus according to claim 264 and wherein said secondary liquid heating volume portion is formed of a material which is less rigid and less heat conductive than said material forming said primary liquid heating volume portion.
266. Apparatus according to claim 263 and wherein at least said primary liquid flow pathway is defined by said liquid heating enclosure and by said heat-conductive element.
267. Apparatus according to claim 260 and wherein at least said liquid heating enclosure defines an at least partially turbulent flow primary liquid flow pathway in said primary liquid heating volume portion and an at least partially turbulent flow secondary liquid flow pathway in said secondary liquid heating volume portion, said at least partially turbulent flow secondary liquid flow pathway supplying liquid to said at least partially turbulent flow primary liquid flow pathway.
268. Apparatus according to claim 260 and wherein said primary liquid heating volume portion is formed at least partially of a metal material, which is relatively highly heat conductive and said secondary liquid heating volume portion is formed at least partially of a plastic material, which is relatively heat insulative, separated by said heat-conductive element, said heat-conductive element being formed of a material which is less heat conductive than said metal material and more heat conductive than said plastic material.
269. Apparatus according to claim 260 and wherein said heat-conductive element is apertured to permit liquid communication from said secondary liquid heating volume portion to said primary liquid heating volume portion.
270. Apparatus according to claim 260 and wherein said secondary liquid heating volume portion includes at least one displaceable outer wall portion providing freeze protection by virtue of its displaceability.
271. Apparatus according to claim 270 and wherein said heat-conductive element comprises a displaceable element operative to be displaced into said secondary liquid heating volume portion upon freezing of liquid inside said primary liquid heating volume portion.
272. Apparatus according to claim 260 and wherein said heat-conductive element is an intervening liquid impermeable displaceable diaphragm.
273. Apparatus according to claim 260 and wherein said primary liquid heating volume portion is a first conduit element and said secondary liquid heating volume portion is a second conduit element.
274. Apparatus according to claim 273 and wherein said heat exchanger is defined by said first conduit element and said second conduit element.
275. Apparatus according to claim 260 and wherein said at least one vehicle surface includes at least one of the following surfaces:
a front vehicle windshield surface, a back vehicle windshield surface, side vehicle windows, a vehicle headlight surface, a vehicle rear light surface, a vehicle radar antenna surface and a vehicle exterior mirror surface.
276. Apparatus according to claim 260 and wherein said heated liquid spray control subassembly is operative to employ said vehicle surface liquid heating assembly and said vehicle surface liquid spraying assembly for providing a spray of liquid onto a vehicle windshield surface and a vehicle radar antenna surface.
277. Apparatus according to claim 276 and also comprising a normally-open valve interconnecting vehicle windshield sprayers of said vehicle windshield surface to said vehicle surface liquid spraying assembly and being operative, when open, to bypass vehicle radar antenna sprayers of said vehicle radar antenna surface.
278. Apparatus according to claim 277 and also comprising a flow restrictor, restricting liquid flow to said vehicle radar antenna sprayers to ensure liquid is supplied to said vehicle windshield sprayers when said normally-open valve is open.
279. Apparatus for spraying a liquid onto at least one vehicle surface comprising:
a liquid reservoir;
a vehicle surface liquid heating assembly receiving a liquid from said liquid reservoir;
a vehicle surface liquid spraying assembly receiving heated liquid from said vehicle surface liquid heating assembly; and
a heated liquid spray control subassembly employing said vehicle surface liquid heating assembly and said vehicle surface liquid spraying assembly for providing a spray of said heated liquid onto said at least one vehicle surface; and
a normally closed automatically operative valve interconnecting said liquid reservoir to said vehicle surface liquid spraying assembly and being operative, when open, to bypass said liquid heating assembly.
280. Apparatus according to claim 279 and also comprising a vehicle pump connected upstream of said at least one liquid reservoir and downstream of said normally closed automatically operative valve.
281. Apparatus according to claim 279 and wherein said at least one vehicle surface includes at least one of the following surfaces:
a front vehicle windshield surface, a back vehicle windshield surface, a side vehicle window, a vehicle headlight surface, a vehicle rear light surface, a vehicle radar antenna surface and a vehicle exterior mirror surface.
282. Apparatus according to claim 279 and wherein said normally closed automatically operative valve is a differential pressure responsive one-way valve.
283. Apparatus according to claim 279 and wherein said at least one vehicle surface includes a first surface and a second surface and said apparatus also comprises a normally-open valve interconnecting vehicle sprayers of said first surface to said vehicle surface liquid spraying assembly and being operative, when open, to bypass vehicle sprayers of said second surface.
284. Apparatus according to claim 283 and also comprising a flow restrictor, restricting liquid flow to said vehicle sprayers of said second surface to ensure liquid is supplied to said vehicle sprayers of said first surface when said normally-open valve is open.
285. Apparatus according to claim 284 and wherein said first surface is a vehicle windshield surface.
286. A method for spraying a liquid onto at least one vehicle surface comprising:
providing a vehicle including said at least one vehicle surface and a liquid reservoir;
supplying said liquid from said liquid reservoir to a vehicle surface liquid heating assembly including a primary liquid heating volume portion and a secondary liquid heating volume portion, separated by a heat-conductive element;
directly heating said liquid in said primary liquid heating volume portion, thereby indirectly heating said liquid in said secondary liquid heating volume portion via said heat-conductive element; and
thereafter spraying said liquid onto said at least one vehicle surface.
287. A method according to claim 286 and wherein said spraying includes spraying said liquid for an initial spray cycle.
288. A method according to claim 287 and wherein said indirectly heating liquid in said secondary liquid heating volume portion during a relatively long time duration after initial operation of a motor of said vehicle causes said initial spray cycle to be relatively longer than when said indirectly heating liquid in said secondary liquid heating volume portion is during a relatively short time duration after said initial operation of said motor of said vehicle.
289. A method according to claim 287 and wherein said spraying said liquid onto said at least one vehicle surface is nearly instantaneous when said indirectly heating liquid in said secondary liquid heating volume portion is for a relatively short time duration after said initial operation of said motor of said vehicle.
290. A method according to claim 287 and wherein said indirectly heating liquid in said secondary liquid heating volume portion during a relatively long time duration after a previous spray cycle causes said initial spray cycle to be relatively longer than when said indirectly heating liquid in said secondary liquid heating volume portion is during a relatively short time duration after said previous spray cycle.
291. A method according to claim 287 and wherein said spraying said liquid onto said at least one vehicle surface is nearly instantaneous when said indirectly heating liquid in said secondary liquid heating volume portion is for a relatively short time duration after a previous spray cycle.
292. A heated liquid discharge system comprising:
a main assembly which provides liquid heating and includes electrical and liquid flow control functionalities;
a liquid inflow conduit supplying liquid from a liquid reservoir to said main assembly; and
a liquid outflow conduit supplying liquid to at least one sprayer located at at least one location on a motor vehicle,
said liquid inflow conduit having connected in series therewith a leaky one-way valve which permits limited backflow of liquid from said main assembly to said reservoir.
293. A heated liquid discharge system according to claim 292 and wherein said main assembly comprises a liquid heating chamber communicating with said liquid inflow conduit and said liquid outflow conduit and being formed with a liquid drain aperture located on a side thereof which permits draining of liquid from said liquid heating chamber generally down to a level of said liquid drain aperture via said leaky one-way valve.
294. A heated liquid discharge system according to claim 293 and wherein said draining takes place when a vehicle pump supplying liquid to said liquid inflow conduit is not in operation.
295. A heated liquid discharge system according to claim 292 and wherein said at least one location includes at least one of the following locations:
front vehicle windshield, back vehicle windshield, side vehicle windows, vehicle headlights, vehicle rear lights and vehicle exterior mirrors.
296. A heated liquid discharge system according to claim 292 and also comprising an overheating cut-off fuse for shutting off electrical power to at least part of said main assembly in the event of overheating of a liquid heating chamber located within said main assembly.
297. A heated liquid discharge system according to claim 296 and wherein said fuse is formed with an undersurface of a resilient material and is retained in tight thermal engagement with the underside of a base of a liquid heating element located within said liquid heating chamber.
298. A heated liquid discharge system according to claim 293 and wherein said liquid drain aperture together with said leaky one-way valve provides both overheating and anti-freezing protection for said main assembly.
299. Apparatus for spraying a liquid onto at least one vehicle surface comprising:
a liquid reservoir;
a vehicle surface liquid heating assembly receiving a liquid from said liquid reservoir;
a vehicle surface liquid spraying assembly receiving heated liquid from said vehicle surface liquid heating assembly; and
a heated liquid spray control subassembly employing said vehicle surface liquid heating assembly and said vehicle surface liquid spraying assembly for providing a spray of said heated liquid onto said at least one vehicle surface,
said spray of said heated liquid being automatically activated by an automatic gain control circuit (AGC) actuation signal.

What is claimed is:

1. A method for managing a CAM (content addressable memory) look-up table using LPM (Longest Prefix Matching), the method comprising:
providing a pair of pointers per every band of data having the same prefix in length, wherein one of the pair of pointers stores the address of data having the lowest address in each band of data, and the other pointer of the pair of pointers stores the next higher address of data having the highest address in each band of data; and
making a space in which data is to be added in the CAM look-up table by moving data having the addresses stored in the pair of pointers provided per each band of data that has a shorter prefix length than the prefix length of the data to be added, when data is added to the CAM look-up table.
2. A method for managing a CAM look-up table using LPM wherein data having the longest prefix length is stored at the lowest address, the method comprising:
providing a pair of pointers per every band of data having the same prefix length, wherein one of the pair of pointers is a lower pointer which stores the address of data having the lowest address in each band of data, and the other pointer of the pair of pointers is an upper pointer which stores the next higher address of data having the highest address in each band of data; and
writing data having an address stored in the lower pointer provided per each band of data, which has a shorter prefix length than the prefix length of the data to be added, to the address stored in the upper pointer provided per each band of data, and writing the data to be added at the address stored in the upper pointer provided in the band of data having the same prefix length as the data to be added, in the case that data is added to the look-up table.
3. The method of claim 2 further comprising:
updating the addresses stored in the lower pointer and the upper pointer provided per each band of data which has a shorter prefix length than the prefix length of the data to be added so that the lower pointer and the upper pointer provided per each band of data may store the next higher addresses, and updating the addresses stored in the upper pointer provided per each band of data which has the same prefix length as the prefix length of the data to be added so that the upper pointer provided per said each band of data may store the next higher address.
4. A method for adding data to a CAM look-up table using LPM wherein data having the longest prefix length is stored at the lowest address, the method comprising:
providing a pair of pointers per every band of data having the same prefix in length, wherein one of the pair of pointers is a lower pointer which stores the address of data having the lowest address in each band of data, and the other pointer of the pair of pointers is an upper pointer which stores the next higher address of data having the highest address in each band of data;
receiving a command of adding data to the look-up table;
writing data having an address stored in the lower pointer provided per each band of data, which has a shorter prefix length than the prefix length of the data to be added, to the address stored in the upper pointer provided per said each band of data in order to make a space in which data is to be added in the CAM look-up table; and
writing the data, which is to be added, at the address stored in the upper pointer provided in the band of data having the same prefix length as the data to be added.
5. An apparatus for managing a CAM look-up table using the LPM, the apparatus comprising:
a CAM including a look-up table in which data having the longest prefix is stored at the lowest address;
a pointer storage unit including a pair of pointers per every band of data having the same prefix in length, wherein one of the pair of pointers is a lower pointer which stores the address of data having the lowest address in each band of data, and the other pointer of the pair of pointers is an upper pointer which stores the next higher address of data having the highest address in each band of data; and
a table managing unit for writing data having an address stored in the lower pointer provided per each band of data, which has a shorter prefix length than the prefix length of the data to be added, to the address stored in the upper pointer provided per each band of data, writing the data to be added, at the address stored in the upper pointer provided at the band of data having the same prefix length as the data to be added, and updating the addresses stored in the lower pointers and the upper pointers included in the pointer storage unit, in the case that data is added to the look-up table.
6. The apparatus of claim 5, wherein when updating the addresses stored in the lower pointer and the upper pointer included in the pointer storage unit, the table managing unit updates the addresses stored in the lower pointer and the upper pointer provided per each band of data, which has a shorter prefix length than the length of the prefix of the data to be added, so that the lower pointer and the upper pointer provided per said each band of data may store the next higher addresses, and updating the address stored in the upper pointer provided to the band of data which has the same prefix length as the prefix length of the data to be added, so that the upper pointer provided per said band of data may store the next higher address.
7. The apparatus of claim 5, wherein the upper and lower pointers are implemented as registers.
8. A computer-readable recording medium for recording a program that can implement a method of any one of claims 1 through 4 in a computer.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A device comprising:
a substrate comprising at least one microelectronic andor nanoelectronic structure comprising at least one suspended portion,
a cover,
a fluid channel defined between said substrate and the cover, said fluid channel comprising two lateral walls and an upper wall connecting the two lateral walls formed by said cover and a lower wall formed by said substrate and at least two openings in order to provide a circulation in said channel, said microelectronic andor nanoelectronic structure being located inside the fluid channel,
an intermediate layer comprising a face in contact with base faces of said lateral walls, said face of the intermediate layer having an aptitude for sealing with the base faces,
at least one electrical connection line extending between said microelectronic andor nanoelectronic structure and the outside of the fluid channel, said connection line being carried out on the substrate and passing under one of the lateral walls, said at least one electrical connection line being at least partially covered by said intermediate layer at least immediately above the base face of said lateral wall, said lateral walls being sealingly fixed on said substrate by a sealing mechanism on said intermediate layer.
2. The device according to claim 1, comprising a functionalization layer encapsulating at least one portion of the suspended portion of the microelectronic andor nanoelectronic structure.
3. The device according to claim 2, wherein the functionalization layer comprises one or several materials chosen from among organic or inorganic materials, polymers, oxides, semiconductors.
4. The device according to claim 1, wherein the at least one electrical connection line comprises at least one pair of connection lines extending laterally on either side of the microelectronic andor nanoelectronic structure and each passing under a lateral wall.
5. The device according to claim 1, wherein the intermediate layer covers, in the fluid channel, the entire microelectronic andor nanoelectronic structure except for its suspended portion.
6. The device according to claim 1, wherein the intermediate layer comprises an electrical insulating material, such as silicon oxide, or a silicon nitride.
7. The device according to claim 1, comprising electrical connection lines and contact pads, said contact pads being located outside of the fluid channel, said connection lines extending between the microelectronic andor nanoelectronic structure and the contact pads.
8. The device according to claim 1, wherein the electrical connection lines comprise several levels of metallisation at least inside the fluid channel.
9. The device according to claim 1, comprising a dry film for sealing inserted between the intermediate layer and the base faces of the lateral walls of the cover.
10. The device according to claim 9, wherein the dry film for sealing is structured into several beads on interfaces between the intermediate layer and the base faces of the lateral walls.
11. The device according to claim 1, comprising at least one layer of material inserted between the intermediate layer and the base faces of the lateral walls creating a eutectic sealing or by thermo-compression, or by screen printing or wherein the sealing is a molecular sealing or wherein the sealing is made by glass frit.
12. The device according to claim 1, wherein the intermediate layer comprises a first layer of electrical insulating material in contact with the electrical connection line and a second layer deposited onto the first layer, said second layer being of a material such that it is little or not sensitive to a step of releasing the microelectronic andor nanoelectronic structure.
13. The device according to claim 12, wherein the second layer is made of Si, silicon nitride, metal or hafnium oxide.
14. The device according to claim 1, wherein the channel forms a gas chromatography microcolumn.
15. A method of carrying out at least one device according to claim 1, comprising the steps of:
a) carrying out the microelectronic andor nanoelectronic structure on a substrate and of at least one connection line,
b) forming of the intermediate layer is such a way that it has a substantially planar free face having an opening above said at least suspended portion
c) carrying out of a cover substrate comprising a fluid channel,
d) sealing of the cover substrate on the intermediate layer in such a way that the fluid channel is arranged facing the microelectronic andor nanoelectronic structure.
16. The method according to claim 15, comprising a step of carrying out a functionalization layer inside the fluid channel on the microelectronic andor nanoelectronic structure andor on the walls of the cover andor on the intermediate layer, said step being carried out before the sealing.
17. The method of carrying out according to claim 15, comprising after the step b), a step of releasing said microelectronic andor nanoelectronic structure.
18. The method of carrying out according to claim 15, wherein the step of sealing using a dry film, the method for carrying out comprises the sub-steps of:
rolling of dry film on the base faces of the walls of the cover,
structuring of the dry film,
coming closer together of the cover and of the substrate comprising the microelectronic andor nanoelectronic structure,
application of a pressure in such a way as to crush the dry film.
19. The method of carrying out according to claim 15, wherein the sealing is a eutectic sealing or by thermo-compression, or by molecular sealing or by screen printing.
20. The method of carrying out according to claim 15, wherein the carrying out of the intermediate layer takes place by deposit of a first layer of electrical insulating material and of deposit of a second layer on the first layer.
21. The method of carrying out according to claim 15, wherein several devices are carried out simultaneously, said substrate comprising several microelectronic andor nanoelectronic structures and the cover substrate comprising several covers, with the covers being sealed simultaneously on the substrate comprising the microelectronic andor nanoelectronic structures, in such a way that a fluid channel of a device can communicate or not with the fluid channel of other devices.
22. The method of carrying out according to claim 21, comprising the steps of:
carrying out pre-cuts in a direction perpendicular to the fluid channels in the cover substrate and in the substrate bearing the microelectronic structures andor
carrying out cuts or pre-cuts in a direction parallel to the fluid channels in the substrate bearing the microelectronic andor nanoelectronic structures,
separating devices.
23. The method of carrying out according to claim 22, wherein the separation of the devices is carried by cleavage.
24. The method of carrying out according to claim 22, wherein the cover substrate comprising cavities formed beforehand between the channels wherein are located contact pads after sealing, the method further comprises a step of cutting the cover substrate in order to open said cavities.
25. The method of carrying out according to claim 23, wherein the cover substrate comprising cavities formed beforehand between the channels wherein are located contact pads after sealing, the method further comprises a step of cutting the cover substrate in order to open said cavities.
26. The method of carrying out according to claim 24, wherein a functionalization layer has been formed on said microelectronic andor nanoelectronic structure and on the contact pads before the sealing, said method comprising the step of removing by etching of the functionalisation layer on the contact pads after sealing and opening of the cavities in the cover, said covers forming masks to said etching for the microelectronic andor nanoelectronic structures.
27. The method of carrying out according to claim 25, wherein a functionalization layer has been formed on said microelectronic andor nanoelectronic structure and on the contact pads before the sealing, said method comprising the step of removing by etching of the functionalization layer on the contact pads after sealing and opening of the cavities in the cover, said covers forming masks to said etching for the microelectronic andor nanoelectronic structures.
28. A method of carrying out at least one device according to claim 1, comprising the steps of:
a) carrying out the microelectronic andor nanoelectronic structure on a substrate and of at least one connection line,
b) forming of the intermediate layer in such a way that it has a substantially planar free face having an opening above said at least suspended portion
c) carrying out of a cover substrate comprising a fluid channel,
d) sealing of the cover substrate on the intermediate layer in such a way that the fluid channel is arranged facing the microelectronic andor nanoelectronic structure, the method also comprising a step of carrying out a functionalization layer inside the fluid channel on the microelectronic andor nanoelectronic structure andor on the walls of the cover andor on the intermediate layer, said step being carried out before the sealing.