1. A wireless receiver, comprising:
a plurality of reception section that receives a plurality of radio signals that pass through different propagation paths;
a propagation path compensation section that compensates for variations in amplitude and phase that are provided to said radio signals in said propagation paths, for each of radio signals received by said plurality of reception sections;
an interference compensation section that respectively compensates for interference components in the radio signals received by said plurality of reception sections based on environments in said propagation paths; and
a selection section that selects one of said propagation path compensation section and a said interference compensation section.
2. The wireless receiver according to claim 1, wherein said selection section conducts the selection based on environments in said different propagation paths.
3. The wireless receiver according to claim 1, wherein said selection section selects said propagation path compensation section, when the radio signal received by said reception section is not multiple signal or is a multiplexed signal of an identical signal.
4. The wireless receiver according to claim 1, further comprising:
a propagation path estimation section that estimates the variations in amplitude and phase that are provided to desired signals and interference signals contained in said radio signals in said propagation paths in relation to said desired signal and said interference signal,
wherein said selection section conducts said selection based on differences or ratios of variables estimated about said desired signals and said interference signals.
5. The wireless receiver according to claim 4, wherein said selection section comprises:
a comparing section that compares said differences or ratios with a predetermined threshold; and
a setting section that sets said threshold based on a modulation level, a coding rate, a spreading factor or a code multiplex number of said radio signal,
wherein said selection is conducted based on a comparing result of said comparing section.
6. The wireless receiver according to claim 1, wherein said radio signal is converted into a multi-carrier.
7. A communication terminal apparatus comprising said wireless receiver according to claim 1.
8. Abase station apparatus comprising said wireless receiver according to claim 1.
9. A wireless receiver, comprising:
a plurality of reception section that receives a plurality of radio signals that pass through different propagation paths;
a first compensation section that compensates for signals except for a desired signal in radio signals received by said plurality of reception sections as an interference component;
a second compensation section that compensates for signals except a desired signal in radio signals received by said plurality of reception sections as a noise component; and
a selection section that selects one of said first compensation section and said second compensation section.
10. A wireless reception method, comprising the steps of:
receiving a radio signal that contains multiplexed different signals through a plurality of antennas;
compensating for a propagation path by compensating for variations in amplitude and phase that are provided to said radio signals in said propagation paths for each of received radio signals;
compensating for an interference for compensating interference components in the respective received radio signals based on environments in said propagation paths through which the radio signals pass; and
selecting one of said propagation path compensation step and said interference compensation step based on said propagation path environment.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. Byte alignment circuitry comprising:
a data input;
a control input;
a special character selection input indicating which one of a plurality of different special characters is to be used for byte alignment, the plurality of different special characters including special characters having a plurality of different sizes in terms of how many bytes they include;
a special character status output indicating which one of the plurality of special characters was used to align the byte boundaries; and
a data output.
2. The circuitry defined in claim 1 wherein said data input is one of a plurality of parallel data inputs.
3. The circuitry defined in claim 2 wherein said plurality of parallel data inputs is the number of bits in a byte.
4. The circuitry defined in claim 1 wherein said data output is one of a plurality of parallel data outputs.
5. The circuitry defined in claim 4 wherein said plurality of parallel data outputs is the number of bits in a byte.
6. The circuitry defined in claim 5 wherein successive aligned bytes are output one after another via the data outputs.
7. The circuitry defined in claim 1 further comprising a clock input.
8. A digital processing system comprising:
processing circuitry;
a memory coupled to the processing circuitry; and
byte alignment circuitry as defined in claim 1 coupled to said processing circuitry and said memory.
9. A printed circuit board on which is mounted byte alignment circuitry as defined in claim 1.
10. The printed circuit board defined in claim 9 further comprising:
a memory mounted on said printed circuit board and coupled to said byte alignment circuitry.
11. The printed circuit board defined in claim 9 further comprising:
processing circuitry mounted on said printed circuit board and coupled to said byte alignment circuitry.
12. Circuitry for receiving and byte-aligning data comprising:
byte alignment circuitry that uses a first special character selected by a special character selection signal from a plurality of different special characters having a plurality of different sizes in terms of how many bytes they include to detect byte boundaries in received data, and aligns the byte boundaries when enabled by a control signal to subsequently output byte-aligned data and a special character status signal indicative of which one of the special characters was used to align the byte boundaries; and
utilization circuitry responsive to outputs of the byte alignment circuitry and selectively providing said control signal and said special character selection signal.
13. The circuitry defined in claim 12 wherein the byte-aligned data is output in parallel form.
14. The circuitry defined in claim 12 wherein said utilization circuitry comprises programmable logic circuitry.
15. The circuitry defined in claim 12, wherein said byte alignment circuitry outputs a pattern detect signal indicative of the presence of byte aligned data; and
said pattern detect signal causes said utilization circuitry to disable said control signal.
16. The circuitry defined in claim 12, wherein said byte alignment circuitry automatically prevents alignment to subsequently received data containing byte boundary data after the byte boundaries have already been aligned.
17. The circuitry defined in claim 12, wherein said byte alignment circuitry provides data representing said first special character to said utilization circuitry.
18. The circuitry defined in claim 12, wherein said special character select signal can instruct said byte alignment circuitry to use a second special character selected from the plurality of different special characters to detect the byte boundaries in received data.
19. The circuitry defined claim 18, wherein said byte alignment circuitry re-aligns the byte boundaries using said second special character when enabled by said control signal.
20. Circuitry for receiving and byte-aligning data comprising:
byte alignment circuitry that processes received data and outputs byte-aligned data after byte boundaries are aligned, said byte alignment circuitry further comprising:
special character detection circuitry that detects a selected special character in the received data, said selected special character being selected, based on a selection signal, from a plurality of different special characters that have a plurality of different sizes in terms of how many bytes they include; and
boundary adjustor circuitry that sets the byte boundaries when said selected special character is detected and criteria are met; and
utilization circuitry that receives the outputs of said byte alignment circuitry.
21. The circuitry defined in claim 20, wherein said selection signal is hardwired to permanently select a particular one of the special characters from the plurality of different special characters.
22. The circuitry defined in claim 20, wherein said utilization circuitry provides said selection signal to select a particular special character from the plurality of different special characters.
23. The circuitry defined in claim 20, wherein said byte alignment circuitry disables said boundary adjustor circuitry independent of a control signal.
24. The circuitry defined in claim 20, wherein said utilization circuitry enables said boundary adjustor circuitry by providing a control signal to said byte alignment circuitry.
25. The circuitry defined in claim 20, wherein said byte alignment circuitry further comprises special character constructor circuitry.