All The Claims

1. A fuel vapor supply system configured to supply fuel vapor to an internal combustion engine having an intake passage, the fuel vapor supply system comprising:
a canister configured to store the fuel vapor;
a purge passage extending from the canister to connect to the intake passage of the internal combustion engine wherein the purge passage allows the fuel vapor stored in the canister to flow to the internal combustion engine through the purge passage;
a purge valve disposed in the purge passage wherein the purge valve is configured to regulate a flow rate of the fuel vapor flowing from the canister to the intake passage is controlled;
a check valve disposed in the purge passage between the purge valve and the intake passage wherein the check valve is configured to permit the flow of the fuel vapor from the canister to the intake passage and further wherein the check valve is configured to prevent the flow of air from the intake passage to the canister;
wherein the purge passage has an intermediate purge passage that extends from the purge valve to the check valve; and
wherein the check valve is configured to open when an intermediate purge passage pressure within the intermediate purge passage exceeds an intake passage pressure within the intake passage and the check valve is configured to close when the intermediate purge passage pressure does not exceed the intake passage pressure;
a pressure detection device configured to detect the intake passage pressure;
a controller coupled with the purge valve, wherein the controller is configured to:
control a degree of opening of the purge valve or a duty ratio wherein the duty ratio is defined as a ratio of a valve opening time to a predetermined frequency period and further wherein control of the degree of opening of the purge valve or control of the duty ratio regulates the flow rate of the fuel vapor flowing across the purge valve;
perform a purge control to control the purge valve to open with a predetermined opening degree or a predetermined duty ratio such that the fuel vapor stored in the canister flows from the canister to the internal combustion engine via the purge passage and the intake passage because of a negative pressure in the intake passage wherein the negative pressure is defined as a pressure less than an atmospheric pressure, while the fuel vapor flows across the purge valve, through the intermediate purge passage, and across the check valve in the purge passage; and
estimate the intermediate purge passage pressure within the intermediate purge passage at least partially based on the intake passage pressure detected by the pressure detection device.
2. The fuel vapor supply system according to claim 1, wherein the controller is configured to estimate the intermediate purge passage pressure to be equal to a smallest value of detected values of the intake passage pressure should the purge valve be fully closed.
3. The fuel vapor supply system according to claim 1, wherein the controller is configured to estimate the intermediate purge passage pressure to be equal to the intake passage pressure detected at a time when a predetermined pressure variation transition time has elapsed after initiating the purge control should the purge valve not be fully closed.
4. The fuel vapor supply system according to claim 3, wherein the controller is further configured to adjust a duration of the predetermined pressure variation transition time based on a difference between the intake passage pressure detected by the pressure detection device and the intermediate purge passage pressure estimated when the purge valve is fully closed.
5. The fuel vapor supply system according to claim 3, wherein the controller is configured to estimate the intermediate purge passage pressure to be equal to the atmospheric pressure provided that the intake passage pressure exceeds the atmospheric pressure at a time when the predetermined pressure variation transition time has elapsed after starting the purge control should the purge valve not be fully closed.
6. The fuel vapor supply system according to claim 1,
wherein the controller is further coupled with a fuel injector associated with the internal combustion engine and is further configured to perform a reduction control to reduce a quantity of fuel injected from the injector;
wherein the reduction control regulates the fuel injector to reduce a quantity of fuel injected from the injector to compensate for the fuel vapor supplied to the internal combustion engine during the purge control; and
wherein the reduction control begins at a time determined at least partially based on the intake passage pressure detected by the pressure detection device, the estimated pressure within the intermediate purge passage, and a predetermined arrival delay time that is a time of delay for arrival of the fuel vapor from the canister to the internal combustion engine.
7. The fuel vapor supply system according to claim 6, wherein the predetermined arrival delay time is determined based on at least one of a rotational speed of a crankshaft of the engine, a flow rate of intake air flowing through the intake passage, a degree of opening of the purge valve, and the intake passage pressure detected by the pressure detection device.
8. A system comprising:
an internal combustion engine;
an intake passage in fluid communication with the internal combustion engine wherein the intake passage is configured to supply intake air to the internal combustions engine;
a fuel tank configured to store the fuel;
a canister in fluid communication with the fuel tank wherein the canister is configured to store fuel from the fuel tank;
a purge passage extending from the canister to connect with the intake passage;
a purge valve disposed in the purge passage such that the fuel stored in the canister flows to the intake passage through the purge passage when the purge valve is open;
a check valve disposed in the purge passage at a downstream position relative to a flow of fuel from the canister to the intake passage wherein the check valve is configured to prevent flow of intake air from the intake passage to the canister through the purge passage;
a controller coupled with the purge valve wherein the controller is configured to regulate the purge valve at least partially based on an intake passage pressure within the intake passage and an intermediate purge passage pressure within an intermediate purge passage of the purge passage located between the purge valve and the check valve; and
wherein the controller is further configured to estimate the intermediate purge passage pressure to be equal to the intake passage pressure or an atmospheric pressure dependent on a controlled opening and closing state of the purge valve.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of forming a hardmask pattern over a semiconductor device semiconductor device, the method comprising:
forming a first hardmask layer and a second hardmask layer over a semiconductor substrate;
forming first and second patterns of a first type over the second hardmask layer;
forming first and second overcoats over the first and second patterns of the first type, respectively, the first and second overcoats being conformal to the corresponding patterns of the first type, the first and second overcoats defining a space therebetween and configured to expose an underlying layer;
forming a filling layer to fill the space defined between the first and second overcoats;
removing the first and second overcoats to provide the first pattern of the first type, the second pattern of the first type, and an additional pattern provided between the first and second patterns of the first type; and
etching the second hardmask layer and the first hardmask layer using the first pattern of the first type, the second pattern of the first type, and the additional pattern to obtain hardmask patterns.
2. The method of claim 1, wherein the substrate defines a dense region and an isolated region, the dense region having more transistors per area than the isolated region, the method further comprising:
providing a pattern of a second type over the filling region, wherein the pattern of the second type covers in the dense region and exposes the isolated region, so that a portion the filling layer that is provided in the isolated region is exposed; and
removing the exposed filling layer in the isolated region while leaving the filling layer in the dense region intact.
3. The method of claim 2, further comprising:
removing the pattern of the second type, wherein the first and second overcoats are removed using the same process to remove the pattern of the second type.
4. The method of claim 1, wherein the first and second overcoats are formed using amorphous carbon.
5. The method of claim 1, wherein the first and second overcoats are configured to have substantially the same thickness.
6. The method of claim 1, wherein the first hardmask layer is formed from amorphous carbon.
7. The method of claim 1, wherein the second hardmask layer is formed from SiON.
8. The method of claim 1, wherein the second hardmask layer is formed from nitride.
9. The method of claim 1, wherein the first and second patterns of the first type are formed from polysilicon, wherein the underlying layer is the second hardmask layer.
10. The method of claim 1, wherein the filling layer is formed from spin on glass (SOG).
11. A method of forming a hardmask pattern over a semiconductor device semiconductor device, the method comprising:
forming a first hardmask layer over a semiconductor substrate;
forming first and second structures over the first hardmask layer, the first and second structures formed of the same material, the first and second structures defining a first pitch;
forming first and second overcoats over the first and second structures, respectively, the first and second overcoats being conformal to the first and second structures, respectively, the first and second overcoats defining a space therebetween and configured to expose an underlying layer;
forming a filling layer to fill the space defined between the first and second overcoats;
removing the first and second overcoats to provide the first structure, the second structure, and a third structure provided between the first and second structures, the first and third structures defining a second pitch, the second and third structures defining a third pitch; and
etching the first hardmask layer using the first, second, and third structures to obtain first, second, and third hardmask patterns, respectively.
12. The method of claim 11 , further comprising:
providing a second hardmask layer below the first hardmask layer, wherein the etching step involves etching the first and second hardmask layers to obtain the first, second, and third hardmask layers, each hardmask layer including the first and second hardmask layers.
13. The method of claim 11, wherein the substrate defines a dense region and an isolated region, the dense region having more transistors per area than the isolated region, the method further comprising:
providing a pattern over the filling region, wherein the pattern covers in the dense region and exposes the isolated region, so that a portion the filling layer that is provided in the isolated region is exposed; and
removing the exposed filling layer in the isolated region while leaving the filling layer in the dense region intact.
14. The method of claim 13, wherein the filling layer includes spin on glass.
15. The method of claim 14, wherein the pattern is a photoresist pattern.
16. The method of claim 15, wherein the pattern and the first and second overcoats are removed using the same process.
17. The method of claim 11, wherein the first pitch is greater than the second pitch or the third pitch, the second and third pitch being substantially the same.
18. The method of claim 17, wherein the second or third pitch has a dimension that is less than the maximum resolution of an exposure apparatus used to form the first and second structures.

1. A circuit analysis device for acquiring a signal delay time at a Register Transfer level of a circuit including multiple components, comprising:
a storage unit for storing:
connection information including information about kinds and numbers of said multiple components and connection relations among components;
delay information including information about a delay time of a discrete component and a chain delay time which is a delay time in a case in which a chain delay effect is generated by a connection with another component about each kind of said multiple components; and
chain effect propagating component information including information about kinds of chain effect propagating components which are components for transmitting the chain delay effect, and
a data processing unit for:
when inputting said connection information, said delay information about each kind of said multiple components and said chain effect propagating component information, storing these kinds of information in said storage unit;
referring to information stored in said storage unit;
performing a total delay time calculation process of sequentially adding delay times of components along a signal path in said circuit; and
determining that a chain effect propagating component is halfway through a signal path in a total delay time calculation process, examining a connection relation between components that precede and follow said chain effect propagating component and determining a delay time of the component that follows said chain effect propagating component that corresponds to the connection relations.
2. The circuit analysis device according to claim 1, wherein:
determining that a chain effect propagating component is connected halfway through said signal path in said total delay time calculation process, said data processing unit determines whether or not a connection between components that precede and follow said chain effect propagating component is in a connection relation for generating the chain delay effect so as to replace the delay time of the component that follows said chain effect propagating component by the chain delay time in a case of being in the connection relation, and to replace the delay time of the component that follows said chain effect propagating component by the delay time of the discrete component in a case of not being in the connection relation.
3. The circuit analysis device according to claim 1, wherein said chain effect propagating component is a component for inputting and outputting signals via a bus.
4. The circuit analysis device according to claim 1, wherein:
said chain effect propagating component includes multiple paths leading from an input to an output and has a property to propagate or not to propagate the chain delay effect for each of said multiple paths; and
said chain effect propagating component information includes information about whether or not to propagate the chain delay effect for each of said multiple paths of said chain effect propagating component.
5. A circuit analysis device for acquiring a signal delay time at a Register Transfer level of a circuit including multiple components, comprising:
a storage unit for storing:
connection information including information about kinds and numbers of said multiple components and connection relations among components;
delay information including information about a delay time of a discrete component and a chain delay time which is a delay time in a case in which a chain delay effect is generated by a connection with another component about each kind of said multiple components; and
chain effect propagating component information including information about kinds of chain effect propagating components which are components for passing the chain delay effect, and
a data processing unit for:
when inputting information about behavioral description of said circuit, said delay information about each kind of said multiple components and said chain effect propagating component information, storing these kinds of information in said storage unit;
performing a synthesis process of generating said connection information from said information about behavioral description and storing said connection information in said storage unit;
referring to information stored in said storage unit;
performing a total delay time calculation process of sequentially adding delay times of components along a signal path in said circuit; and
determining that a chain effect propagating component is halfway through a signal path in said total delay time calculation process, examining a connection relation between components that precede and follow said chain effect propagating component and determining the delay time of the component that follows said chain effect propagating component that corresponds to the connection relations.
6. The circuit analysis device according to claim 5, wherein:
information about a performance specification of said circuit is stored in said storage unit; and
said data processing unit compares a result of said total delay time calculation process with said performance specification, performs said synthesis process and said total delay time calculation process again in a case in which said performance specification is not satisfied, and makes an output unit output a result of said synthesis process in a case in which the performance specification is satisfied.
7. The circuit analysis device according to claim 5, wherein:
determining that a chain effect propagating component is connected halfway through said signal path in said total delay time calculation process, said data processing unit determines whether or not a connection between components that precede and follow said chain effect propagating component is in a connection relation for generating the chain delay effect so as to replace the delay time of the component that follows said chain effect propagating component by the chain delay time in a case of being in the connection relation, and to replace the delay time of the component that follows said chain effect propagating component by the delay time of the discrete component in a case of not being in the connection relation.
8. The circuit analysis device according to claim 5, wherein said chain effect propagating component is a component for inputting and outputting signals via a bus.
9. The circuit analysis device according to claim 5, wherein:
said chain effect propagating component includes multiple paths leading from an input to an output and has a property to propagate or not to propagate the chain delay effect for each of said multiple paths; and
said chain effect propagating component information includes information about whether or not to propagate the chain delay effect for each of said multiple paths of said chain effect propagating component.
10. A circuit analysis method by a circuit analysis device for acquiring a signal delay time at a Register Transfer level of a circuit including multiple components, comprising the steps of:
storing as machine readable information in a machine storage unit, connection information including information about kinds and numbers of said multiple components and connection relations among components; delay information including information about a delay time of a discrete component and a chain delay time which is a delay time in a case in which a chain delay effect is generated by a connection with another component about each kind of said multiple components; and chain effect propagating component information including information about kinds of chain effect propagating components which are components for transmitting the chain delay effect, and
referring to information stored in said storage unit;
performing a total delay time calculation process of sequentially adding delay times of the components along a signal path in said circuit; and
determining that a chain effect propagating component is halfway through a signal path in said total delay time calculation process, examining a connection relation between components that precede and follow said chain effect propagating component and determining a delay time of the component that follows said chain effect propagating component that corresponds to the connection relations.
11. The circuit analysis method according to claim 10, wherein:
determining that a chain effect propagating component is connected halfway through the signal path in said total delay time calculation process, it is determined whether or not a connection between components that precede and follow said chain effect propagating component is in a connection relation for generating the chain delay effect so as to replace the delay time of the component that follows said chain effect propagating component by the chain delay time in a case of being in the connection relation, and to replace the delay time of the component that follows said chain effect propagating component by the delay time of the discrete component in a case of not being in the connection relation.
12. The circuit analysis method according to claim 10, wherein said chain effect propagating component is a component for inputting and outputting signals via a bus.
13. The circuit analysis method according to claim 10, wherein:
said chain effect propagating component includes multiple paths leading from an input to an output and has a property to propagate or not to propagate the chain delay effect for each of said multiple paths; and
said chain effect propagating component information includes information about whether or not to propagate the chain delay effect for each of said multiple paths of said chain effect propagating component.
14. A circuit analysis method by a circuit analysis device for acquiring a signal delay time at a Register Transfer level of a circuit including multiple components, comprising the steps of:
storing machine readable information in a machine storage unit, information about behavioral description of said circuit; delay information including information about a delay time of a discrete component and a chain delay time which is a delay time in a case in which a chain delay effect is generated by a connection with another component about each kind of said multiple components; and chain effect propagating component information including information about kinds of chain effect propagating components which are components for passing the chain delay effect, and
performing a synthesis process of generating connection information including information about kinds and numbers of said multiple components and connection relations among the components from said information about behavioral description and storing said connection information in said storage unit;
referring to information stored in said storage unit;
performing a total delay time calculation process of sequentially adding delay times of components along a signal path in said circuit; and
determining that a chain effect propagating component is halfway through a signal path in said total delay time calculation process, examining a connection relation between components that precede and follow said chain effect propagating component and determining the delay time of the component that follows said chain effect propagating component that corresponds to the connection relations.
15. The circuit analysis method according to claim 14, wherein:
information about a performance specification of said circuit is stored in said storage unit; and
a result of said total delay time calculation process is compared with said performance specification so that said synthesis process and said total delay time calculation process are performed again in a case in which said performance specification is not satisfied, and a result of said synthesis process is outputted by an output unit in a case in which said performance specification is satisfied.
16. The circuit analysis method according to claim 14, wherein:
determining that a chain effect propagating component is connected halfway through the signal path in said total delay time calculation process, it is determined whether or not a connection between components that precede and follow said chain effect propagating component is in a connection relation for generating the chain delay effect so as to replace the delay time of the component that follows said chain effect propagating component by the chain delay time in a case of being in the connection relation, and to replace the delay time of the component that follows said chain effect propagating component by the delay time of the discrete component in a case of not being in the connection relation.
17. The circuit analysis method according to claim 14, wherein said chain effect propagating component is a component for inputting and outputting signals via a bus.
18. The circuit analysis method according to claim 14, wherein:
said chain effect propagating component includes multiple paths leading from an input to an output and has a property to propagate or not to propagate the chain delay effect for each of said multiple paths; and
said chain effect propagating component information includes information about whether or not to propagate the chain delay effect for each of said multiple paths of said chain effect propagating component.
19. A recording medium including a computer-readable program recorded therein for acquiring a signal delay time at a Register Transfer level of a circuit including multiple components, the program causing the computer to execute a process comprising the steps of:
storing in a storage unit, connection information including information about kinds and numbers of said multiple components and connection relations among components; delay information including information about a delay time of a discrete component and a chain delay time which is a delay time in a case in which a chain delay effect is generated by a connection with another component about each kind of said multiple components; and chain effect propagating component information including information about kinds of chain effect propagating components which are components for transmitting the chain delay effect, and
referring to information stored in said storage unit;
performing a total delay time calculation process of sequentially adding delay times of the components along a signal path in said circuit; and
determining that a chain effect propagating component is halfway through a signal path in said total delay time calculation process, examining a connection relation between components that precede and follow said chain effect propagating component and determining a delay time of the component that follows said chain effect propagating component that corresponds to the connection relations.
20. The recording medium having a program recorded therein according to claim 19, the program causing the computer to further execute the steps of:
determining that a chain effect propagating component is connected halfway through the signal path in said total delay time calculation process, determining whether or not a connection between components that precede and follow said chain effect propagating component is in a connection relation for generating the chain delay effect; and
replacing the delay time of the component that follows said chain effect propagating component by the chain delay time in a case in which the connection is in the connection relation for generating the chain delay effect, and replacing the delay time of the component that follows said chain effect propagating component by the delay time of the discrete component in a case in which the connection is not in the connection relation for generating the chain delay effect.
21. The recording medium including a program recorded therein according to claim 19, wherein said chain effect propagating component is a component for inputting and outputting signals via a bus.
22. The recording medium including a program recorded therein according to claim 19, wherein:
said chain effect propagating component includes multiple paths leading from an input to an output and has a property to propagate or not to propagate the chain delay effect for each of said multiple paths; and
said chain effect propagating component information includes information about whether or not to propagate the chain delay effect for each of said multiple paths of said chain effect propagating component.
23. A recording medium including a computer-readable program recorded therein for acquiring a signal delay time at a Register Transfer level of a circuit including multiple components, the program causing the computer to execute a process comprising the steps of:
storing in a storage unit, information about behavioral description of said circuit; delay information including information about a delay time of a discrete component and a chain delay time which is a delay time in a case in which a chain delay effect is generated by a connection with another component about each kind of said multiple components; and chain effect propagating component information including information about kinds of chain effect propagating components which are components for passing the chain delay effect, and
performing a synthesis process of generating connection information including information about kinds and numbers of said multiple components and connection relations among the components from said information about behavioral description and storing said connection information in said storage unit;
referring to information stored in said storage unit;
performing a total delay time calculation process of sequentially adding delay times of components along a signal path in said circuit; and
determining that a chain effect propagating component is halfway through a signal path in said total delay time calculation process, examining a connection relation between components that precede and follow said chain effect propagating component and determining the delay time of the component that follows said chain effect propagating component that corresponds to the connection relations.
24. The recording medium including a program recorded therein according to claim 23, the program causing the computer to further execute the steps of:
storing information about a performance specification of said circuit in said storage unit; and
comparing a result of said total delay time calculation process with said performance specification, performing said synthesis process and said total delay time calculation process again in a case in which said performance specification is not satisfied, and making an output unit output a result of said synthesis process in a case in which said performance specification is satisfied.
25. The recording medium having a program recorded therein according to claim 23, the program causing the computer to further execute the steps of:
determining that a chain effect propagating component is connected halfway through the signal path in said total delay time calculation process, determining whether or not a connection between components that precede and follow said chain effect propagating component is in a connection relation for generating the chain delay effect; and
replacing the delay time of the component that follows said chain effect propagating component by the chain delay time in a case in which the connection is in the connection relation for generating the chain delay effect, and replacing the delay time of the component that follows said chain effect propagating component by the delay time of the discrete component in a case in which the connection is not in the connection relation for generating the chain delay effect.
26. The recording medium including a program recorded therein according to claim 23, wherein said chain effect propagating component is a component for inputting and outputting signals via a bus.
27. The recording medium including a program recorded therein according to claim 23, wherein:
said chain effect propagating component includes multiple paths leading from an input to an output and has a property to propagate or not to propagate the chain delay effect for each of said multiple paths; and
said chain effect propagating component information includes information about whether or not to propagate the chain delay effect for each of said multiple paths of said chain effect propagating component.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of producing maraging steel and controlling the growth of oxide and titanium nitride inclusions in the maraging steel by the addition of a controlled amount of Mg added to a consumable electrode which is subjected to vacuum arc remelting, the maraging steel exhibiting improved fatigue strength containing from not less than 0.3 mass % to not more than 2.0 mass % of Ti, and from more than zero to less than 15ppm of Mg, less than 10 ppm oxygen and less than 15 ppm nitrogen which method comprises:
producing a consumable electrode wherein the consumable electrode contains oxide inclusions and titanium nitride inclusions and the consumable electrode is subjected to vacuum arc remelting by casting a molten steel which has been melted under vacuum, the consumable electrode containing Mg, and non-metallic inclusions comprising oxide inclusions and titanium nitride inclusions, which titanium nitride inclusions have a nucleus of MgO, wherein the total of all Mg present is not less than 5 ppm; and
subsequently subjecting the consumable electrode to vacuum arc remelting to control the growth of the oxide inclusions and the titanium nitride inclusions, whereby the titanium nitride inclusions and the nucleus of MgO in the titanium nitride inclusions are decomposed so that the Mg content in the maraging steel which is produced by the vacuum arc remelting is reduced from the Mg content in the consumable electrode due to vaporization so that the Mg content in the maraging steel is made to be less than the Mg content in the consumable electrode, wherein the maraging steel contains the titanium nitride inclusions having a size of not more than 15 \u03bcm in maximum length and the oxide inclusions having a size of not more than 20 \u03bcm in maximum length, and wherein
the oxide inclusions comprise spinel form inclusions and alumina inclusions in which a content of the spinel form inclusions having a size of not less than 10 \u03bcm in length divided by a total content of the spinel form inclusions having a size of not less than 10 \u03bcm in length plus the alumina inclusions having a size of not less than 10 \u03bcm in length is more than 0.33.
2. A method of producing maraging steel according to claim 1, wherein the molten steel for casting has been produced by a vacuum induction melting process.
3. A method of producing maraging steel according to claim 1, wherein a maraging steel product obtained by the vacuum arc remelting is subjected to plastic working to produce a thin strip having a thickness of not more than 0.5 mm.
4. Maraging steel comprising, by mass, at least, from not less than 0.3% to not more than 2.0% Ti, from more than zero to less than 15 ppm of Mg, less than 10 ppm oxygen and less than 15 ppm nitrogen, wherein
the maraging steel contains titanium nitride inclusions having a size of not more than 15 \u03bcm in maximum length and oxide inclusions having a size of not more than 20 \u03bcm in maximum length, and wherein
the oxide inclusions comprise spinel form inclusions and alumina inclusions in which a content of the spinel form inclusions having a size of not less than 10 \u03bcm in length divided by a total content of the spinel form inclusions having a size of not less than 10 \u03bcm in length plus the alumina inclusions having a size of not less than 10 \u03bcm in length is more than 0.33.
5. Maraging steel according to claim 4, consisting essentially of, by mass, not more than 0.01% C (carbon), 8.0 to 22.0% Ni, 5.0 to 20.0% Co, 2.0 to 9.0% Mo, from not less than 0.3% to not more than 2.0% Ti, not more than 1.7% Al, from more than zero to less than 10 ppm Mg, less than 10ppm oxygen, less than 15 ppm nitrogen, and the balance of Fe and incidental impurities.
6. A thin strip which is made from maraging steel as defined in claim 4, and which has a thickness of not more than 0.5 mm.
7. A thin strip which is made from maraging steel as defined in claim 5, and which has a thickness of not more than 0.5 mm.
8. The method according to claim 1, wherein a thin strip having a thickness of not more than 0.5 mm is produced by plastic working the maraging steel after the vacuum arc remelting.
9. The method according to claim 3, wherein the thin strip having a thickness of not more than 0.5 mm is a component of a continuously variable transmission.
10. The method according to claim 8, wherein the thin strip having a thickness of not more than 0.5 mm is a component of a continuously variable transmission.
11. A component of a continuously variable transmission, which is made of the thin strip having a thickness of not more than 0.5 mm as defined in claim 6.
12. A component of continuously variable transmissions, which is made of the thin strip having a thickness of not more than 0.5 mm as defined in claim 7.
13. A method of producing maraging steel according to claim 1, wherein the amount of Mg is from more than 0 to less than 10 ppm in the maraging steel and wherein the consumable electrode contains from 10 to 150 ppm Mg.
14. A method of producing maraging steel according to claim 1, wherein the consumable electrode contains from 5 to not more than 300 ppm Mg.
15. A method of producing maraging steel according to claim 1, wherein the consumable electrode contains from 5 to not more than 250 ppm Mg.
16. A method of producing maraging steel according to claim 1, wherein the maraging steel consists essentially of, by mass, not more than 0.01% C (carbon), 8.0 to 22.0% Ni, 5.0 to 20.0% Co, 2.0 to 9.0% Mo, from not less than 0.3% to not more than 2.0% Ti, not more than 1.7% Al, from more than zero to less than 10 ppm Mg, less than 10 ppm oxygen, less than 15 ppm nitrogen, and the balance of Fe and incidental impurities.
17. A method of producing maraging steel according to claim 13, wherein the maraging steel compounds by mass from more than 0 to 5 ppm Mg.
18. Maraging steel according to claim 4, wherein the maraging steel comprises by mass, from more than 0 to 5 ppm Mg.
19. A method according to claim 13, wherein a maraging steel product obtained by the vacuum arc remelting is subjected to plastic working to produce a thin strip having a thickness of not more than 0.5 mm.
20. A method according to claim 19, wherein the thin strip having a thickness of not more than 0.5 mm is a component of a continuously variable transmission.