All The Claims

1. A method of operating a programmable device having a plurality of configuration memory cells and a processing core, the method comprising:
defining a don’t care set of configuration memory cells in the plurality of configuration memory cells; and
using the don’t care set of configuration memory cells as readwrite memory for the processing core.
2. The method of operating a programmable device of claim 1, further comprising configuring a portion of the programmable device as the processing core.
3. The method of operating a programmable device of claim 1, wherein the don’t care set of configuration memory cells includes configuration memory cells associated with an unused portion of the programmable device.
4. The method of operating a programmable device of claim 1, wherein the don’t care set of configuration memory cells includes configuration memory cells associated with a partially configured configurable logic block.
5. The method of operating a programmable device of claim 1, further comprising configuring a portion of the programmable device as a memory management unit.
6. The method of operating a programmable device of claim 1, wherein the defining the don’t care set of configuration memory cells comprises:
defining a care set of configuration memory cells; and
defining configuration memory cells not included in the care set of configuration memory cells as the don’t care set of configuration memory cells.
7. The method of operating a programmable device of claim 1, wherein the using the don’t care set of configuration memory cells as readwrite memory for the processing core further comprises:
reading a frame of data from the don’t care set of configuration memory cells;
modifying a portion of the frame of data; and
writing the frame of data to the don’t care set of configuration memory cells.
8. The method of operating a programmable device of claim 1, further comprising storing predetermined user data in a subset of the don’t care set of configuration memory cells.
9. The method of operating a programmable device of claim 8, wherein the storing predetermined user data in the subset of the don’t care set of configuration memory cells comprises writing the predetermined user data into the subset of the don’t care set of configuration memory cells from a configuration bitstream.
10. The method of operating a programmable device of claim 8, wherein the subset of the don’t care set of configuration memory cells is treated as read-only memory.
11. A method of operating a programmable device having a plurality of configuration memory cells and a processing core, the method comprising:
defining a don’t care set of configuration memory cells in the plurality of configuration memory cells; and
storing predetermined user data in a subset of the don’t care set of configuration memory cells.
12. The method of operating a programmable device of claim 11, further comprising configuring a portion of the programmable device as the processing core.
13. The method of operating a programmable device of claim 11, wherein the don’t care set of configuration memory cells includes configuration memory cells associated with an unused portion of the programmable device.
14. The method of operating a programmable device of claim 11, wherein the don’t care set of configuration memory cells includes configuration memory cells associated with a partially configured configurable logic block.
15. The method of operating a programmable device of claim 11, wherein the defining the don’t care set of configuration memory cells comprises:
defining a care set of configuration memory cells; and
defining configuration memory cells not included in the care set of configuration memory cells as the don’t care set of configuration memory cells.
16. The method of operating a programmable device of claim 11, wherein the storing predetermined user data in the subset of the don’t care set of configuration memory cells comprises writing the predetermined user data into the subset of the don’t care set of configuration memory cells from a configuration bitstream.
17. The method of operating a programmable device of claim 11, wherein the subset of the don’t care set of configuration memory cells is treated as read-only memory.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An image forming apparatus comprising:
a pattern forming unit that forms a color-misalignment detection pattern on an image carrier;
a light-intensity detecting unit that detects the color-misalignment detection pattern formed on the image carrier by irradiating the image carrier with a light and detecting light intensity of a reflected light from the image carrier; and
a color-misalignment-amount detecting unit that detects an amount of a color misalignment of an image based on the light intensity of the reflected light detected by the light-intensity detecting unit, wherein
a spot of the light on the image carrier is elongated in a main-scanning direction.
2. The image forming apparatus according to claim 1, wherein the pattern forming unit forms the color-misalignment detection pattern in a plurality of rows within a length of the spot of the light in the main-scanning direction.
3. The image forming apparatus according to claim 1, wherein
the color-misalignment detection pattern includes a main-scanning-direction misalignment detection pattern for detecting a color misalignment in the main-scanning direction,
the pattern forming unit forms the main-scanning-direction misalignment detection pattern including a first pattern for a predetermined reference color and a second pattern for a non-reference color other than the reference color arranged being overlapped with each other on the image carrier,
a plurality of the first patterns and a plurality of the second patterns are arranged in the sub-scanning direction with different amounts of the color misalignment in the main-scanning direction, and
the light-intensity detecting unit detects the amount of the color misalignment in the main-scanning direction based on a variation in the light intensity caused by shifts of the reflected lights from the first pattern and the second pattern in the main-scanning direction, and
a length of the second pattern in the sub-scanning direction is shorter than a length of the spot in the sub-scanning direction.
4. The image forming apparatus according to claim 3, wherein
the length of the second pattern in the sub-scanning direction is shorter than the length of the spot sub-scanning, and
a length of the first pattern in the sub-scanning direction is longer than the length of the spot in the sub-scanning direction.
5. The image forming apparatus according to claim 1, wherein
the color-misalignment detection pattern includes a sub-scanning-direction misalignment detection pattern for detecting a color misalignment in a sub-scanning direction,
the pattern forming unit forms the sub-scanning-direction misalignment detection pattern including a first pattern for a predetermined reference color and a second pattern for a non-reference color other than the reference color arranged being overlapped with each other on the image carrier,
a plurality of the first patterns and a plurality of the second patterns are arranged in the sub-scanning direction with different amounts of the color misalignment in the sub-scanning direction, and
line widths of the first pattern and the second pattern in the sub-scanning direction are shorter than a length of the spot in the sub-scanning direction.
6. The image forming apparatus according to claim 1, wherein
the color-misalignment detection pattern includes a main-scanning-direction misalignment detection pattern for detecting a color misalignment in the main-scanning direction or a sub-scanning-direction misalignment detection pattern for detecting a color misalignment in a sub-scanning direction,
the pattern forming unit forms one of the main-scanning-direction misalignment detection pattern and the sub-scanning-direction misalignment detection pattern including a first pattern for a predetermined reference color and a second pattern for a non-reference color other than the reference color arranged being overlapped with each other on the image carrier, and
the first pattern is formed without forming the second pattern in a specific region, and
the light-intensity detecting unit detects the amount of the color misalignment in one of the main-scanning direction and the sub-scanning direction based on a variation in the light intensity caused by shifts of the reflected lights from the first pattern and the second pattern in one of the main-scanning direction and the sub-scanning direction.
7. The image forming apparatus according to claim 6, further comprising:
a determining unit that determines that there is a large color misalignment in one of the main-scanning direction and the sub-scanning direction when a value obtained by (Vmax-VBk)VBk is smaller than a preset determination value, where Vmax is a maximum output of one of the main-scanning-direction misalignment detection pattern and the sub-scanning-direction misalignment detection pattern from the light-intensity detecting unit and VBk is an output of the first pattern from the light-intensity detecting unit.
8. The image forming apparatus according to claim 6, further comprising:
a determining unit that determines that there is a large color misalignment in one of the main-scanning direction and the sub-scanning direction when a value obtained by (Vmax-VBk)(VBk-V0) is smaller than a preset determination value, where Vmax is a maximum output of one of the main-scanning-direction misalignment detection pattern and the sub-scanning-direction misalignment detection pattern from the light-intensity detecting unit, VBk is an output of the first pattern from the light-intensity detecting unit, and V0 is an output without patterns from the light-intensity detecting unit.
9. The image forming apparatus according to claim 6, further comprising:
a determining unit that determines that there is a large color misalignment in one of the main-scanning direction and the sub-scanning direction when a value obtained by (Vmax-VBk)(Vmin-VBk) is smaller than a preset determination value, where Vmax is a maximum output of one of the main-scanning-direction misalignment detection pattern and the sub-scanning-direction misalignment detection pattern from the light-intensity detecting unit, VBk is an output of the first pattern from the light-intensity detecting unit, and Vmin is a minimum output of one of the main-scanning-direction misalignment detection pattern and the sub-scanning-direction misalignment detection pattern from the light-intensity detecting unit.
10. The image forming apparatus according to claim 6, further comprising:
a determining unit that determines that there is a large color misalignment in one of the main-scanning direction and the sub-scanning direction when a value obtained by (Vmin-VBk)VBk is larger than a preset determination value, where VBk is an output of the first pattern from the light-intensity detecting unit and Vmin is a minimum output of one of the main-scanning-direction misalignment detection pattern and the sub-scanning-direction misalignment detection pattern from the light-intensity detecting unit.
11. The image forming apparatus according to claim 6, further comprising:
a determining unit that determines that there is a large color misalignment in one of the main-scanning direction and the sub-scanning direction when a value obtained by (Vmin-VBk)(VBk-V0) is larger than a preset determination value, where VBk is an output of the first pattern from the light-intensity detecting unit, Vmin is a minimum output of one of the main-scanning-direction misalignment detection pattern and the sub-scanning-direction misalignment detection pattern from the light-intensity detecting unit, and V0 is an output without patterns from the light-intensity detecting unit.
12. The image forming apparatus according to claim 6, further comprising:
a determining unit that determines that there is a large color misalignment in one of the main-scanning direction and the sub-scanning direction when a value obtained by Vmax-Vmin is smaller than a preset determination value, where Vmax is a maximum output of one of the main-scanning-direction misalignment detection pattern and the sub-scanning-direction misalignment detection pattern from the light-intensity detecting unit and Vmin is a minimum output of one of the main-scanning-direction misalignment detection pattern and the sub-scanning-direction misalignment detection pattern from the light-intensity detecting unit.
13. The image forming apparatus according to claim 6, further comprising:
a determining unit that determines that there is a large color misalignment in one of the main-scanning direction and the sub-scanning direction when a value obtained by Vmax-VBk is smaller than a preset determination value, where Vmax is a maximum output of one of the main-scanning-direction misalignment detection pattern and the sub-scanning-direction misalignment detection pattern from the light-intensity detecting unit and VBk is an output of the first pattern from the light-intensity detecting unit.
14. The image forming apparatus according to claim 6, further comprising:
a storage unit that stores therein a plurality of determination conditions selected from
{(Vmax-VBk)VBk}<(determination value)
{(Vmax-VBk)(VBk-V0)}<(determination value)
{(Vmax-VBk)(Vmin-VBk)}<(determination value)
{(Vmin-VBk)VBk}>(determination value)
{(Vmin-VBk)(VBk-V0)}>(determination value)
(Vmax-Vmin)<(determination value)
(Vmax-VBk)<(determination value)

where Vmax is a maximum output of one of the main-scanning-direction misalignment detection pattern and the sub-scanning-direction misalignment detection pattern from the light-intensity detecting unit, Vmin is a minimum output of one of the main-scanning-direction misalignment detection pattern and the sub-scanning-direction misalignment detection pattern from the light-intensity detecting unit, VBk is an output of the first pattern from the light-intensity detecting unit, and V0 is an output without patterns from the light-intensity detecting unit; and
a determining unit that determines that there is a large color misalignment in one of the main-scanning direction and the sub-scanning direction when any one of values obtained by the determination conditions stored in the storage unit is satisfied.
15. The image forming apparatus according to claim 7, wherein a value of Vmax is an average value of the maximum output and a second maximum output from the light-intensity detecting unit.
16. The image forming apparatus according to claim 8, wherein a value of Vmax is an average value of the maximum output and a second maximum output from the light-intensity detecting unit.
17. The image forming apparatus according to claim 9, wherein a value of Vmax is an average value of the maximum output and a second maximum output from the light-intensity detecting unit.
18. The image forming apparatus according to claim 12, wherein a value of Vmax is an average value of the maximum output and a second maximum output from the light-intensity detecting unit.
19. The image forming apparatus according to claim 13, wherein a value of Vmax is an average value of the maximum output and a second maximum output from the light-intensity detecting unit.
20. The image forming apparatus according to claim 14, wherein a value of Vmax is an average value of the maximum output and a second maximum output from the light-intensity detecting unit.
21. An image forming method comprising:
forming a color-misalignment detection pattern on an image carrier;
detecting the color-misalignment detection pattern formed on the image carrier by irradiating the image carrier with a light and detecting light intensity of a reflected light from the image carrier; and
detecting an amount of a color misalignment of an image based on the light intensity of the reflected light, wherein
a spot of the light on the image carrier is elongated in a main-scanning direction.

1. A video decoding method comprising:
obtaining a quantization parameter of a slice;
generating a predicted quantization parameter of a current quantization group using the quantization parameter of the slice, wherein the current quantization group is a first quantization group in a current row included in the slice;
generating, according to an availability of a neighboring block of the second quantization group in the current row, a predicted quantization parameter of a second quantization group in the current row included in the slice using a determined quantization parameter regarding the neighboring block of the second quantization group;
generating a predicted quantization parameter of a next quantization group using the quantization parameter of the slice, wherein the next quantization group is a first quantization group in a next row included in the slice; and
performing an inverse quantization on the current quantization group, the second quantization group in the current row, and the next quantization group,
wherein each of the current row and the next row comprises a plurality of largest coding units.
2. The video decoding method of claim 1, wherein the current quantization group is a set of at least one of coding units sharing the predicted quantization parameter of the current quantization group.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A synchronous semiconductor memory device operating in synchronization with an external clock comprising:
a data output buffer circuit for performing an output operation of read data to the outside requiring a processing time corresponding to an operating condition; and
a control clock generating circuit for generating a control clock activating said output operation of said data output buffer circuit according to said external clock,
said control clock generating circuit including:
a delay circuit for delaying said external clock to generate said control clock,
a delay control section controlling a delay time in said delay circuit according to a phase difference between said external clock and a feedback clock, and
a replica delay time adjusting section, provided between said delay circuit and said delay control circuit, and for delaying said control clock by a replica delay time corresponding to said processing time to generate said feedback clock, and
said replica delay time adjusting section adjusting said replica delay time according to said operating condition.
2. The synchronous semiconductor memory device according to claim 1, wherein said operating condition sets the number of bits of data communicated in a one time data input and output operations.
3. The synchronous semiconductor memory device according to claim 1, wherein said replica delay time adjusting section comprises:
a fixed delay circuit for delaying said control clock by a fixed first delay time; and
a delay adjusting section for further delaying said control clock by a second delay time according to said operating condition.
4. The synchronous semiconductor memory device according to claim 3, wherein said operating condition sets the number of bits of data communicated in a one time data input and output operations and
said first delay time is set in correspondence to said processing time in a case where said number of bits is set to the minimum.
5. The synchronous semiconductor memory device according to claim 1, wherein said replica delay time adjusting section comprises:
a delay capacitor for delaying said control clock; and
a switch circuit electrically coupled between a node transmitting said control clock and said delay capacitor, and
said switch circuit is turned on or off according to said operating condition.
6. The synchronous semiconductor memory device according to claim 5, wherein said delay capacitor includes a capacitor formed by a field effect transistor.
7. The synchronous semiconductor memory device according to claim 5, wherein said delay capacitor comprises: a PN junction capacitor formed on a semiconductor substrate.
8. The synchronous semiconductor memory device according to claim 5, wherein said delay capacitor comprises:
a plurality of sub delay capacitors formed on a semiconductor substrate;
a plurality of first interconnects electrically coupled to said plurality of sub delay capacitors, respectively, and formed in the same interconnection layer on said semiconductor substrate;
a second interconnect formed in said same interconnection layer and coupled to said node through said switch circuit; and
a third interconnect selectively formed in at least one of a plurality of regions of said same interconnection layer, corresponding to between each of said plurality of first interconnects and said second interconnect.
9. The synchronous semiconductor memory device according to claim 5, wherein said delay capacitor comprises:
a plurality of sub delay capacitors formed on a semiconductor substrate;
a plurality of first interconnects electrically coupled to said respective plurality of sub delay capacitors;
a second interconnect coupled to said node through said switch circuit; and
a plurality of program elements electrically coupled between of said plurality of first interconnects and said second interconnect, respectively, and
selection of electrical coupling or non-coupling in said plurality of program elements between corresponding one of said plurality of first interconnects and said second interconnect is externally set in a non-volatile manner.
10. The synchronous semiconductor memory device according to claim 1, wherein said replica delay time adjusting section comprises:
a plurality of delay resistors connected in parallel between a first node to which said control clock is transmitted and a second node from which said feedback clock is generated; and
a plurality of first switch circuits provided corresponding to said plurality of delay resistors, respectively, and turned on or off according to said operating condition, and
each of said first switch circuits is electrically coupled between one of said first and second nodes and a corresponding one of said plurality of delay resistors.
11. The synchronous semiconductor memory device according to claim 10, wherein said replica delay time adjusting section further comprises: a second switch circuit coupled directly between said first node and said second node and turned on or off according to said operating condition.
12. The synchronous semiconductor memory device according to claim 10, wherein each of said plurality of delay resistors comprises:
a plurality of sub delay resistors formed on a semiconductor substrate;
a plurality of first interconnects electrically coupled to said plurality of sub delay resistors, respectively, and formed in the same interconnection layer on said semiconductor substrate;
a second interconnect formed in said same interconnection layer and coupled to said one of said first and second nodes through said first switch circuit; and
a third interconnect selectively formed in at least one of a plurality of regions of said same interconnection layer, corresponding to between each of said plurality of first interconnects and said second interconnect.
13. The synchronous semiconductor memory device according to claim 10, wherein each of said plurality of delay resistors comprises:
a plurality of sub delay resistors formed on a semiconductor substrate;
a plurality of first interconnects electrically coupled to said plurality of sub delay resistors, respectively;
a second interconnect formed in said same interconnection layer and coupled to said one of said first and second nodes through said first switch circuit; and
a plurality of program elements electrically coupled between each of said plurality of first interconnects and said second interconnect, and
selection of electrical coupling or non-coupling in said plurality of program elements between corresponding one of said plurality of first interconnects and said second interconnect is externally set in a non-volatile manner.