1. A liquid crystal display (LCD) comprising:
a display panel comprising:
a plurality of scan lines;
a plurality of data lines, substantially perpendicularly disposed with the scan lines;
a plurality of pixels arranged in an array, respectively electrically connected with corresponding data line and the corresponding scan line, each of the pixels comprising:
a common line for receiving a common voltage; and
a compensation line for receiving a stable voltage; and
a voltage supply device, coupled to the compensation line of each of the pixels, for continuously and correspondingly providing the stable voltage to the compensation line of each of the pixels.
2. The LCD according to claim 1, wherein each of the pixels of the ith pixel row further comprises:
a pixel transistor, having a gate coupled to the ith scan line and a source coupled to the ith data line, where i is a positive integer;
a first liquid crystal capacitor, having a first end coupled to a drain of the pixel transistor and a second end coupled to a common electrode; and
a storage capacitor, having a first end coupled to the drain of the pixel transistor and a second end coupled to the common line,
wherein the pixel transistor, the first liquid crystal capacitor and the storage capacitor are located in a transparent area.
3. The LCD according to claim 2, wherein each of the pixels of the ith pixel row further comprises:
a first capacitor having a first end coupled to the drain of the pixel transistor;
a second liquid crystal capacitor, having a first end coupled to a second end of the first capacitor and a second end coupled to the common electrode; and
a second capacitor, having a first end coupled to the second end of the first capacitor and a second end coupled to the compensation line,
wherein the first capacitor, the second liquid crystal capacitor and the second capacitor are located in a reflective area.
4. The LCD according to claim 3, wherein the voltage supply device comprises a plurality of voltage supply units, and the ith voltage supply unit provides the stable voltage with a positive polarity or a negative polarity to the compensation line of each of the pixels of the ith or the (i+1)th pixel row according to a corresponding scan signal and a first and a second clock signals, wherein there is a 180 degrees phase difference between the first clock signal and the second clock signal,
wherein duty cycles of the first and the second clock signals are substantially an enable period of the corresponding scan signal.
5. The LCD according to claim 4, wherein the ith voltage supply unit comprises:
a first N-type transistor, having a gate coupled to the ith scan line to receive the corresponding scan signal and a source receiving the first clock signal;
a third capacitor, having a first end coupled to a drain of the first N-type transistor and a second end coupled the common line;
a second N-type transistor, having a gate coupled to the drain of the first N-type transistor, a source receiving the stable voltage with the positive polarity and a drain coupled to the compensation line of each of the pixels of the ith or the (i+1)th pixel row;
a third N-type transistor, having a gate coupled to the ith scan line to receive the corresponding scan signal and a source receiving the second clock signal;
a fourth capacitor, having a first end coupled to a drain of the third N-type transistor and a second end coupled to the common line; and
a fourth N-type transistor having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the negative polarity and a drain coupled to the compensation line of each of the pixels of the ith or the (i+1)th pixel row.
6. The LCD according to claim 3, wherein the voltage supply device comprises a plurality of voltage supply units, and the ith voltage supply unit provides the stable voltage with a positive polarity or a negative polarity to the compensation line of each of the pixels of the ith or the (i+1)th pixel row according to a corresponding scan signal, a first clock signal and a second clock signal.
7. The LCD according to claim 6, wherein a duty cycle of the first clock signal is substantially an enable period of the corresponding scan line, while the second clock signal is maintained enabled.
8. The LCD according to claim 6, wherein the ith voltage supply unit comprises:
a first N-type transistor, having a gate and a source both coupled with each other to receive the second clock signal;
a second N-type transistor, having a gate coupled to a drain of the first N-type transistor, a source receiving the stable voltage with the positive polarity, and a drain coupled to the compensation line of each of the pixels of the it or the (i+1)th pixel row;
a third N-type transistor, having a gate coupled to the ith scan line to receive the corresponding scan signal and a source receiving the first clock signal;
a third capacitor, having a first end coupled to a drain of the third N-type transistor and a second end coupled the common line;
a fourth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the negative polarity and a drain coupled to the gate of the second N-type transistor; and
a fifth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the negative polarity, and a drain coupled to the compensation line of each of the pixels of the ith or the (i+1)th pixel row,
wherein the ith voltage supply unit further provides the stable voltage with the positive polarity or the negative polarity to the compensation line of each of the pixels of the ith or the (i+1)th pixel row according to the corresponding scan signal, the first clock signal, and the second and a third clock signals, wherein there is a 180 degrees phase difference between the second clock signal and the third clock signal.
9. The LCD according to claim 3, wherein the voltage supply device comprises:
a first sub-voltage supply device, including a plurality of first voltage supply units, wherein the ith first voltage supply unit provides the stable voltage with a positive polarity to the compensation line of all odd pixels of the ith or the (i+1)th pixel row according to a corresponding scan signal and a first and a second clock signals, wherein there is a 180 degrees phase difference between the first clock signal and the second clock signal; and
a second sub-voltage supply device, including a plurality of second voltage supply units, wherein the ith second voltage supply unit provides the stable voltage with a negative polarity to the compensation line of all even pixels of the ith or the (i+1)th pixel row according to the corresponding scan signal, and the first and the second clock signals, wherein there is a 180 degrees phase difference between the first clock signal and the second clock signal,
wherein duty cycles of the first and the second clock signals are substantially a frame period of the LCD.
10. The LCD according to claim 9, wherein the ith first voltage supply unit comprises:
a first N-type transistor, having a gate coupled to the ith scan line to receive the corresponding scan signal and a source receiving the first clock signal;
a third capacitor, having a first end coupled to a drain of the first N-type transistor and a second end coupled to the common electrode;
a second N-type transistor, having a gate coupled to the drain of the first N-type transistor, a source receiving the stable voltage with the positive polarity and a drain coupled to the compensation line of all odd pixels of the ith or the (i+1)th pixel row;
a third N-type transistor, having a gate coupled to the ith scan line to receive the corresponding scan signal and a source receiving the second clock signal;
a fourth capacitor, having a first end coupled to a drain of the third N-type transistor and a second end coupled to the common line; and
a fourth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the negative polarity and a drain coupled to the compensation line of all odd pixels of the ith or the (i+1)th pixel row.
11. The LCD according to claim 9, wherein the ith second voltage supply unit comprises:
a first N-type transistor, having a gate coupled to the ith scan line to receive the corresponding scan signal and a source receiving the first clock signal;
a third capacitor, having a first end coupled to a drain of the first N-type transistor and a second end coupled to the common line;
a second N-type transistor, having a gate coupled to the drain of the first N-type transistor, a source receiving the stable voltage with the negative polarity and a drain coupled to the compensation line of all even pixels of the ith or the (i+1)th pixel row;
a third N-type transistor, having a gate coupled to the ith scan line to receive the corresponding scan signal and a source receiving the second clock signal;
a fourth capacitor, having a first end coupled to a drain of the third N-type transistor and a second end coupled to the common line; and
a fourth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the positive polarity and a drain coupled to the compensation line of all even pixels of the ith or the (i+1)th pixel row.
12. The LCD according to claim 3, wherein the voltage supply device comprises:
a first sub-voltage supply device including a plurality of first voltage supply units, wherein the ith first voltage supply unit provides the stable voltage with a positive polarity to the compensation line of all odd pixels of the ith or the (i+1)th pixel row according to a corresponding scan signal, a first clock signal and a second clock signal; and
a second sub-voltage supply device including a plurality of second voltage supply units, wherein the ith second voltage supply unit provides the stable voltage with a negative polarity to the compensation line of all even pixels of the ith or the (i+1)th pixel row according to the corresponding scan signal, the first clock signal and the second clock signal.
13. The LCD according to claim 12, wherein a duty cycle of the first clock signal is substantially a frame period of the LCD, while the second clock signal is maintained enabled.
14. The LCD according to claim 12, wherein the ith first voltage supply unit comprises:
a first N-type transistor, having a gate and a source both coupled with each other to receive the second clock signal;
a second N-type transistor, having a gate coupled to a drain of the first N-type transistor, a source receiving the stable voltage with the positive polarity and a drain coupled to the compensation line of all odd pixels of the ith or the (i+1)th pixel row;
a third N-type transistor, having a gate coupled to the ith scan line to receive the corresponding scan signal, and a source receiving the first clock signal;
a third capacitor, having a first end coupled to a drain of the third N-type transistor and a second end coupled to the common line;
a fourth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the negative polarity and a drain coupled to the gate of the second N-type transistor; and
a fifth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the negative polarity and a drain coupled to the compensation line of all odd pixels of the ith or the (i+1)th pixel row,
wherein the ith first voltage supply unit further provides the stable voltage with the positive polarity to the compensation line of all odd pixels of the ith or the (i+1)th pixel row according to the corresponding scan signal, the first clock signal, and the second and a third clock signals, wherein there is a 180 degrees phase difference between the second clock signal and the third clock signal.
15. The LCD according to claim 12, wherein the ith second voltage supply unit comprises:
a first N-type transistor, having a gate and a source both coupled with each other to receive the second clock signal;
a second N-type transistor, having a gate coupled to a drain of the first N-type transistor, a source receiving the stable voltage with the negative polarity, and a drain coupled to the compensation line of all even pixels of the ith or the (i+1)th pixel row;
a third N-type transistor, having a gate coupled to the ith scan line to receive the corresponding scan signal and a source receiving the first clock signal;
a third capacitor, having a first end coupled to a drain of the third N-type transistor and a second end coupled to the common line;
a fourth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the negative polarity and a drain coupled to the gate of the second N-type transistor;
a fifth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the positive polarity and a drain coupled to the compensation line of all even pixels of the ith or the (i+1)th pixel row, wherein the ith second voltage supply unit further provides the stable voltage with the negative polarity to the compensation line of all even pixels of the ith or the (i+1)th pixel row according to the corresponding scan signal, the first clock signal, and the second and a third clock signals, wherein there is a 180 degrees phase difference between the second clock signal and the third clock signal, and duty cycles of the second and the third clock signals are substantially an enable period of the corresponding scan signal; and
a sixth N-type transistor, having a gate and a source both coupled with each other to receive the third clock signal and a drain coupled to the drain of the first N-type transistor.
16. The LCD according to claim 3, wherein the voltage supply device comprises:
a first sub-voltage supply device including a plurality of first voltage supply units, wherein
the ith first voltage supply unit provides the stable voltage with a positive polarity to the compensation line of all odd pixels of the ith or the (i+1)th pixel row according to a corresponding scan signal, and a first and a second clock signals, wherein there is a 180 degrees phase difference between the first clock signal and the second clock signal; and
the (i+1)th first voltage supply unit provides the stable voltage with the positive polarity to the compensation line of all even pixels of the (i+1)th or the (i+2)th pixel row according to another corresponding scan signal, and the first and the second clock signals, wherein there is a 180 degrees phase difference between the first clock signal and the second clock signal; and
a second sub-voltage supply device including a plurality of second voltage supply units, wherein
the ith second voltage supply unit provides the stable voltage with a negative polarity to the compensation line of all even pixels of the ith or the (i+1)th pixel row according to the corresponding scan signal, and the first and the second clock signals, wherein there is a 180 degrees phase difference between the first clock signal and the second clock signal; and
the (i+1)th second voltage supply unit provides the stable voltage with the negative polarity to the compensation line of all odd pixels of the (i+1)th or the (i+2)th pixel row according to the another corresponding scan signal, and the first and the second clock signals, wherein there is a 180 degrees phase difference between the first clock signal and the second clock signal,
wherein duty cycles of the first and the second clock signals are substantially a frame period of the LCD.
17. The LCD according to claim 16, wherein the ith first voltage supply unit comprises:
a first N-type transistor, having a gate coupled to the ith scan line to receive the corresponding scan signal and a source receiving the first clock signal;
a third capacitor, having a first end coupled to a drain of the first N-type transistor and a second end coupled to the common line;
a second N-type transistor, having a gate coupled to the drain of the first N-type transistor, a source receiving the stable voltage with the positive polarity, and a drain coupled to the compensation line of all odd pixels of the ith or the (i+1)th pixel row;
a third N-type transistor, having a gate coupled to the ith scan line to receive the corresponding scan signal and a source receiving the second clock signal;
a fourth capacitor, having a first end coupled to a drain of the third N-type transistor and a second end coupled to the common line; and
a fourth N-type transistor, having a gate coupled to a drain of the third N-type transistor, a source receiving the stable voltage with the negative polarity and a drain coupled to the compensation line of all odd pixels of the ith or the (i+1)th pixel row.
18. The LCD according to claim 16, wherein the (i+1)th first voltage supply unit comprises:
a first N-type transistor, having a gate coupled to the (i+1)th scan line to receive the another corresponding scan signal and a source receiving the first clock signal;
a third capacitor, having a first end coupled to a drain of the first N-type transistor and a second end coupled to the common line;
a second N-type transistor, having a gate coupled to the drain of the first N-type transistor, a source receiving the stable voltage with the positive polarity and a drain coupled to the compensation line of all even pixels of the (i+1)th or the (i+2)th pixel row;
a third N-type transistor, having a gate coupled to the (i+1)th scan line to receive the another corresponding scan signal and a source receiving the second clock signal;
a fourth capacitor, having a first end coupled to a drain of the third N-type transistor and a second end coupled to the common line; and
a fourth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the negative polarity and a drain coupled to the compensation line of all even pixels of the (i+1)th or the (i+2)th pixel row.
19. The LCD according to claim 16, wherein the ith second voltage supply unit comprises:
a first N-type transistor, having a gate coupled to the ith scan line to receive the corresponding scan signal and a source receiving the first clock signal;
a third capacitor, having a first end coupled to a drain of the first N-type transistor and a second end coupled to the common line;
a second N-type transistor, having a gate coupled to the drain of the first N-type transistor, a source receiving the stable voltage with the negative polarity and a drain coupled to the compensation line of all even pixels of the ith or the (i+1)th pixel row;
a third N-type transistor having a gate coupled to the ith scan line to receive the corresponding scan signal and a source receiving the second clock signal;
a fourth capacitor, having a first end coupled to a drain of the third N-type transistor and a second end coupled to the common line; and
a fourth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the positive polarity and a drain coupled to the compensation line of all even pixels of the ith or the (i+1)th pixel row.
20. The LCD according to claim 16, wherein the (i+1)th second voltage supply unit comprises:
a first N-type transistor, having a gate coupled to the (i+1)th scan line to receive the another corresponding scan signal and a source receiving the first clock signal;
a third capacitor, having a first end coupled to a drain of the first N-type transistor and a second end coupled to the common line;
a second N-type transistor, having a gate coupled to a drain of the first N-type transistor, a source receiving the stable voltage with the negative polarity and a drain coupled to the compensation line of all odd pixels of the (i+1)th or the (i+2)th pixel row;
a third N-type transistor, having a gate coupled to the (i+1)th scan line to receive the another corresponding scan signal and a source receiving the second clock signal;
a fourth capacitor, having a first end coupled to a drain of the third N-type transistor and a second end coupled to the common line; and
a fourth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the positive polarity and a drain coupled to the compensation line of all odd pixels of the (i+1)th or the (i+2)th pixel row.
21. The LCD according to claim 3, wherein the voltage supply device comprises:
a first sub-voltage supply device including a plurality of first voltage supply units, wherein
the ith first voltage supply unit provides the stable voltage with a positive polarity to the compensation line of all odd pixels of the ith or the (i+1)th pixel row according to a corresponding scan signal, a first clock signal and a second clock signal; and
the (i+1)th first voltage supply unit provides the stable voltage with the positive polarity to the compensation line of all even pixels of the (i+1)th or the (i+2)th pixel row according to another corresponding scan signal, the first clock signal and the second clock signal; and
a second sub-voltage supply device including a plurality of second voltage supply units, wherein
the ith second voltage supply unit provides the stable voltage with a negative polarity to the compensation line of all even pixels of the ith or the (i+1)th pixel row according to the corresponding scan signal, the first clock signal and the second clock signal; and
the (i+1)th second voltage supply unit provides the stable voltage with the negative polarity to the compensation line of all odd pixels of the (i+1)th or the (i+2)th pixel row according to the another corresponding scan signal, the first clock signal and the second clock signal.
22. The LCD according to claim 21, wherein a duty cycle of the first clock signal is substantially a frame period of the LCD, while the second clock signal is maintained enabled.
23. The LCD according to claim 21, wherein the ith first voltage supply unit comprises:
a first N-type transistor, having a gate and a source both coupled with each other to receive the second clock signal;
a second N-type transistor, having a gate coupled to a drain of the first N-type transistor, a source receiving the stable voltage with the positive polarity and a drain coupled to the compensation line of all odd pixels of the ith or the (i+1)th pixel row;
a third N-type transistor, having a gate coupled to the ith scan line to receive the corresponding scan signal and a source receiving the first clock signal;
a third capacitor, having a first end coupled to a drain of the third N-type transistor and a second end coupled to the common line;
a fourth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the negative polarity and a drain coupled to the gate of the second N-type transistor;
a fifth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the negative polarity, and a drain coupled to the compensation line of all odd pixels of the ith or the (i+1)th pixel row, wherein the ith first voltage supply unit further provides the stable voltage with the positive polarity to the compensation line of all odd pixels of the ith or the (i+1)th pixel row according to the corresponding scan signal, the first clock signal, and the second and a third clock signals, wherein there is a 180 degrees phase difference between the second clock signal and the third clock signal, and duty cycles of the second and the third clock signals are substantially an enable period of the corresponding scan signal; and
a sixth N-type transistor, having a gate and a source both coupled with each other to receive the third clock signal, and a drain coupled to the drain of the first N-type transistor.
24. The LCD according to claim 21, wherein the (i+1)th first voltage supply unit comprises:
a first N-type transistor, having a gate and a source both coupled with each other to receive the second clock signal;
a second N-type transistor, having a gate coupled to the drain of the first N-type transistor, a source receiving the stable voltage with the positive polarity, and a drain coupled to the compensation line of all even pixels of the (i+1)th or the (i+2)th pixel row;
a third N-type transistor, having a gate coupled to the (i+1)th scan line to receive the another corresponding scan signal, and a source receiving the first clock signal;
a third capacitor, having a first end coupled to a drain of the third N-type transistor, and a second end coupled to the common line;
a fourth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the negative polarity, and a drain coupled to the gate of the second N-type transistor;
a fifth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the negative polarity, and a drain coupled to the compensation line of all even pixels of the (i+1)th or the (i+2)th pixel row, wherein the (i+1)th first voltage supply unit further provides the stable voltage with the positive polarity to the compensation line of all even pixels of the (i+1)th or the (i+2)th pixel row according to the another corresponding scan signal, the first clock signal, and the second and a third clock signals, wherein there is a 180 degrees phase difference between the second clock signal and the third clock signal, and duty cycles of the second and the third clock signals are substantially an enable period of the corresponding scan signal; and
a sixth N-type transistor, having a gate and a source both coupled with each other to receive the third clock signal, and a drain coupled to the drain of the first N-type transistor.
25. The LCD according to claim 21, wherein the ith second voltage supply unit comprises:
a first N-type transistor, having a gate and a source both coupled with each other to receive the second clock signal;
a second N-type transistor, having a gate coupled to a drain of the first N-type transistor, a source receiving the stable voltage with the negative polarity, and a drain coupled to the compensation line of all even pixels of the ith or the (i+1)th pixel row;
a third N-type transistor, having a gate coupled to the ith scan line to receive the corresponding scan signal, and a source receiving the first clock signal;
a third capacitor, having a first end coupled to a drain of the third N-type transistor, and a second end coupled to the common line;
a fourth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the negative polarity, and a drain coupled to the gate of the second N-type transistor;
a fifth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the positive polarity, and a drain coupled to the compensation line of all even pixels of the ith or the (i+1)th pixel row, wherein the ith second voltage supply unit further provides the stable voltage with the negative polarity to the compensation line of all even pixels of the ith or the (i+1)th pixel row according to the corresponding scan signal, the first clock signal, and the second and a third clock signals, wherein there is a 180 degrees phase difference between the second clock signal and the third clock signal, and duty cycles of the second and the third clock signals are substantially an enable period of the corresponding scan signal; and
a sixth N-type transistor, having a gate and a source both coupled with each other to receive the third clock signal, and a drain coupled to the drain of the first N-type transistor.
26. The LCD according to claim 21, wherein the (i+1)th second voltage supply unit comprises:
a first N-type transistor, having a gate and a source both coupled with each other to receive the second clock signal;
a second N-type transistor, having a gate coupled to a drain of the first N-type transistor, a source receiving the stable voltage with the negative polarity, and a drain coupled to the compensation line of all odd pixels of the (i+1)th or the (i+2)th pixel row;
a third N-type transistor, having a gate coupled to the (i+1)th scan line to receive the another corresponding scan signal, and a source receiving the first clock signal;
a third capacitor, having a first end coupled to a drain of the third N-type transistor, and a second end coupled to the common line;
a fourth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the negative polarity, and a drain coupled to the gate of the second N-type transistor;
a fifth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the positive polarity, and a drain coupled to the compensation line of all odd pixels of the (i+1)th or the (i+2)th pixel row, wherein the (i+1)th second voltage supply unit further provides the stable voltage with the negative polarity to the compensation line of all odd pixels of the (i+1)th or the (i+2)th pixel row according to the another corresponding scan signal, the first clock signal, and the second and a third clock signals, wherein there is a 180 degrees phase difference between the second clock signal and the third clock signal, and duty cycles of the second and the third clock signals are substantially an enable period of the corresponding scan signal; and
a sixth N-type transistor, having a gate and a source both coupled with each other to receive the third clock signal, and a drain coupled to the drain of the first N-type transistor.
27. The LCD according to claim 1, wherein each of the pixels of the ith pixel row further comprises:
a pixel transistor, having a gate coupled to the ith scan line and a source coupled to the ith data line, where i is a positive integer;
a first liquid crystal capacitor, having a first end coupled to a drain of the pixel transistor and a second end coupled to a common electrode;
a first storage capacitor, having a first end coupled to the drain of the pixel transistor and a second end coupled to the common line to receive the stable voltage with a positive polarity;
an auxiliary common line; and
a second storage capacitor, having a first end coupled to the drain of the pixel transistor and a second end coupled to the auxiliary common line to receive the stable voltage with a negative polarity,
wherein the pixel transistor, the first liquid crystal capacitor and the first and the second storage capacitors are located in a transparent area.
28. The LCD according to claim 27, wherein each of the pixels of the ith pixel row further comprises:
a first capacitor having a first end coupled to the drain of the pixel transistor;
a second liquid crystal capacitor, having a first end coupled to a second end of the first capacitor, and a second end coupled to the common electrode; and
a second capacitor, having a first end coupled to the second end of the first capacitor, and a second end coupled to the compensation line,
wherein the first capacitor, the second liquid crystal capacitor and the second capacitor are located in a reflective area.
29. The LCD according to claim 28, wherein the voltage supply device comprises:
a first sub-voltage supply device including a plurality of first voltage supply units, wherein the ith first voltage supply unit provides the stable voltage with the positive polarity to the compensation line of all odd pixels of the ith or the (i+1)th pixel row and to the second end of the first storage capacitor according to a corresponding scan signal, and a first and a second clock signals, wherein there is a 180 degrees phase difference between the first clock signal and the second clock signal; and
a second sub-voltage supply device including a plurality of second voltage supply units, wherein the ith second voltage supply unit provides the stable voltage with the negative polarity to the compensation line of all even pixels of the ith or the (i+1)th pixel row and to the second end of the second storage capacitor according to the corresponding scan signal, and the first and the second clock signals, wherein there is a 180 degrees phase difference between the first clock signal and the second clock signal,
wherein duty cycles of the first and the second clock signals are substantially a frame period of the LCD.
30. The LCD according to claim 29, wherein the ith first voltage supply unit comprises:
a first N-type transistor, having a gate coupled to the ith scan line to receive the corresponding scan signal, and a source receiving the first clock signal;
a third capacitor, having a first end coupled to a drain of the first N-type transistor, and a second end coupled to the common line;
a second N-type transistor, having a gate coupled to the drain of the first N-type transistor, a source receiving the stable voltage with the positive polarity, and a drain coupled to the compensation line of all odd pixels of the ith or the (i+1)th pixel row and to the second end of the first storage capacitor;
a third N-type transistor, having a gate coupled to the ith scan line to receive the corresponding scan signal, and a source receiving the second clock signal;
a fourth capacitor, having a first end coupled to a drain of the third N-type transistor, and a second end coupled to the common line; and
a fourth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the negative polarity, and a drain coupled to the compensation line of all odd pixels of the ith or the (i+1)th pixel row and to the second end of the first storage capacitor.
31. The LCD according to claim 29, wherein the ith second voltage supply unit comprises:
a first N-type transistor, having a gate coupled to the ith scan line to receive the corresponding scan signal, and a source receiving the first clock signal;
a third capacitor, having a first end coupled to a drain of the first N-type transistor, and a second end coupled to the common line;
a second N-type transistor, having a gate coupled to the drain of the first N-type transistor, a source receiving the stable voltage with the negative polarity, and a drain coupled to the compensation line of all even pixels of the ith or the (i+1)th pixel row and to the second end of the second storage capacitor;
a third N-type transistor, having a gate coupled to the ith scan line to receive the corresponding scan signal, and a source receiving the second clock signal;
a fourth capacitor, having a first end coupled to a drain of the third N-type transistor, and a second end coupled to the common line; and
a fourth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the positive polarity, and a drain coupled to the compensation line of all even pixels of the ith or the (i+1)th pixel row and to the second end of the second storage capacitor.
32. The LCD according to claim 28, wherein the voltage supply device comprises:
a first sub-voltage supply device including a plurality of first voltage supply units, wherein the ith first voltage supply unit provides the stable voltage with the positive polarity to the compensation line of all odd pixels of the ith or the (i+1)th pixel row and to the second end of the first storage capacitor according to a corresponding scan signal, and a first and a second clock signals; and
a second sub-voltage supply device including a plurality of second voltage supply units, wherein the ith second voltage supply unit provides the stable voltage with the negative polarity to the compensation line of all even pixels of the ith or the (i+1)th pixel row and to the second end of the second storage capacitor according to the corresponding scan signal, and the first and the second clock signals.
33. The LCD according to claim 32, wherein a duty cycle of the first clock signal is substantially a frame period of the LCD, while the second clock signal is maintained enabled.
34. The LCD according to claim 32, wherein the ith first voltage supply unit comprises:
a first N-type transistor, having a gate and a source both coupled with each other to receive the second clock signal;
a second N-type transistor, having a gate coupled to a drain of the first N-type transistor, a source receiving the stable voltage with the positive polarity, and a drain coupled to the compensation line of all odd pixels of the ith or the (i+1)th pixel row and to the second end of the first storage capacitor;
a third N-type transistor, having a gate coupled to the ith scan line to receive the corresponding scan signal, and a source receiving the first clock signal;
a third capacitor, having a first end coupled to a drain of the third N-type transistor, and a second end coupled to the common line;
a fourth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the negative polarity, and a drain coupled to the gate of the second N-type transistor;
a fifth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the negative polarity, and a drain coupled to the compensation line of all odd pixels of the ith or the (i+1)th pixel row and the to second end of the first storage capacitor, wherein the ith first voltage supply unit further provides the stable voltage with the positive polarity to the compensation line of all odd pixels of the ith or the (i+1)th pixel row and to the second end of the first storage capacitor according to the corresponding scan signal, the first clock signal, and the second and a third clock signals, wherein there is a 180 degrees phase difference between the second clock signal and the third clock signal, and duty cycles of the second and the third clock signals are substantially an enable period of the corresponding scan signal; and
a sixth N-type transistor having a gate and a source both coupled with each other to receive the third clock signal, and a drain coupled to the drain of the first N-type transistor.
35. The LCD according to claim 32, wherein the ith second voltage supply unit comprises:
a first N-type transistor, having a gate and a source both coupled with each other to receive the second clock signal;
a second N-type transistor, having a gate coupled to the drain of the first N-type transistor, a source receiving the stable voltage with the negative polarity, and a drain coupled to the compensation line of all even pixels of the ith or the (i+1)th pixel row and to the second end of the second storage capacitor;
a third N-type transistor, having a gate coupled to the ith scan line to receive the corresponding scan signal, and a source receiving the first clock signal;
a third capacitor, having a first end coupled to a drain of the third N-type transistor, and a second end coupled to the common line;
a fourth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the negative polarity, and a drain coupled to the gate of the second N-type transistor;
a fifth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the positive polarity, and a drain coupled to the compensation line of all even pixels of the ith or the (i+1)th pixel row and to the second end of the second storage capacitor, wherein the ith second voltage supply unit further provides the stable voltage with the positive polarity to the compensation line of all even pixels of the ith or the (i+1)th pixel row and to the second end of the second storage capacitor according to the corresponding scan signal, the first clock signal, and the second and a third clock signals, wherein there is a 180 degrees phase difference between the second clock signal and the third clock signal, and duty cycles of the second and the third clock signals are substantially an enable period of the corresponding scan signal; and
a sixth N-type transistor, having a gate and a source both coupled with each other to receive the third clock signal, and a drain coupled to the drain of the first N-type transistor.
36. The LCD according to claim 28, wherein the voltage supply device comprises:
a first sub-voltage supply device including a plurality of first voltage supply units, wherein
the ith first voltage supply unit provides the stable voltage with the positive polarity to the compensation line of all odd pixels of the ith or the (i+1)th pixel row and to the second end of the first storage capacitor according to a corresponding scan signal, and a first and a second clock signals, wherein there is a 180 degrees phase difference between the first clock signal and the second clock signal; and
the (i+1)th first voltage supply unit provides the stable voltage with the positive polarity to the compensation line of all even pixels of the (i+1)th or the (i+2)th pixel row and to the second end of the first storage capacitor according to another corresponding scan signal, and the first and the second clock signal, wherein there is a 180 degrees phase difference between the first clock signal and the second clock signal; and
a second voltage supply device including a plurality of second voltage supply units, wherein
the ith second voltage supply unit provides the stable voltage with the negative polarity to the compensation line of all odd pixels of the ith or the (i+1)th pixel row and to the second end of the second storage capacitor according to the corresponding scan signal, and the first and the second clock signals, wherein there is a 180 degrees phase difference between the first clock signal and the second clock signal; and
the (i+1)th second voltage supply unit provides the stable voltage with the negative polarity to the compensation line of all odd pixels of the (i+1)th or the (i+2)th pixel row and to the second end of the second storage capacitor according to the another corresponding scan signal, and the first and the second clock signals, wherein there is a 180 degrees phase difference between the first clock signal and the second clock signal,
wherein duty cycles of the first and the second clock signals are substantially a frame period of the LCD.
37. The LCD according to claim 36, wherein the ith first voltage supply unit comprises:
a first N-type transistor, having a gate coupled to the ith scan line to receive the corresponding scan signal, and a source receiving the first clock signal;
a third capacitor, having a first end coupled to a drain of the first N-type transistor, and a second end coupled to the common line;
a second N-type transistor, having a gate coupled to a drain of the first N-type transistor, a source receiving the stable voltage with the positive polarity, and a drain coupled to the compensation line of all odd pixels of the ith or the (i+1)th pixel row and to the second end of the first storage capacitor;
a third N-type transistor, having a gate coupled to the ith scan line to receive the corresponding scan signal, and a source receiving the second clock signal;
a fourth capacitor, having a first end coupled to a drain of the third N-type transistor, and a second end coupled to the common line; and
a fourth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the negative polarity, and a drain coupled to the compensation line of all odd pixels of the ith or the (i+1)th pixel row and to the second end of the first storage capacitor.
38. The LCD according to claim 36, wherein the (i+1)th first voltage supply unit comprises:
a first N-type transistor, having a gate coupled to the (i+1)th scan line to receive the another corresponding scan signal, and a source receiving the first clock signal;
a third capacitor, having a first end coupled to a drain of the first N-type transistor, and a second end coupled to the common line;
a second N-type transistor, having a gate coupled to the drain of the first N-type transistor, a source receiving the stable voltage with the positive polarity, and a drain coupled to the compensation line of all even pixels of the (i+1)th or the (i+2)th pixel row and to the second end of the first storage capacitor;
a third N-type transistor, having a gate coupled to the (i+1)th scan line to receive the another corresponding scan signal, and a source receiving the second clock signal;
a fourth capacitor, having a first end coupled to a drain of the third N-type transistor, and a second end coupled to the common line; and
a fourth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the negative polarity, and a drain coupled to the compensation line of all even pixels of the (i+1)th or the (i+2)th pixel row and to the second end of the first storage capacitor.
39. The LCD according to claim 36, wherein the ith second voltage supply unit comprises:
a first N-type transistor, having a gate coupled to the ith scan line to receive the corresponding scan signal, and a source receiving the first clock signal;
a third capacitor, having a first end coupled to a drain of the first N-type transistor, and a second end coupled to the common line;
a second N-type transistor, having a gate coupled to the drain of the first N-type transistor, a source receiving the stable voltage with the negative polarity, and a drain coupled to the compensation line of all even pixels of the ith or the (i+1)th pixel row and to the second end of the second storage capacitor;
a third N-type transistor, having a gate coupled to the ith scan line to receive the corresponding scan signal, and a source receiving the second clock signal;
a fourth capacitor, having a first end coupled to a drain of the third N-type transistor, and a second end coupled to the common line; and
a fourth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the positive polarity, and a drain coupled to the compensation line of all even pixels of the ith or the (i+1)th pixel row and to the second end of the second storage capacitor.
40. The LCD according to claim 36, wherein the (i+1)th second voltage supply unit comprises:
a first N-type transistor, having a gate coupled to the (i+1)th scan line to receive the another corresponding scan signal, and a source receiving the first clock signal;
a third capacitor, having a first end coupled to a drain of the first N-type transistor, and a second end coupled to the common line;
a second N-type transistor, having a gate coupled to the drain of the first N-type transistor, a source receiving the stable voltage with the negative polarity, and a drain coupled to the compensation line of all odd pixels of the (i+1)th or the (i+2)th pixel row and to the second end of the second storage capacitor;
a third N-type transistor, having a gate coupled to the (i+1)th scan line to receive the another corresponding scan signal, and a source receiving the second clock signal;
a fourth capacitor, having a first end coupled to a drain of the third N-type transistor, and a second end coupled to the common line; and
a fourth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the positive polarity, and a drain coupled to the compensation line of all odd pixels of the (i+1)th or the (i+2)th pixel row and to the second end of the second storage capacitor.
41. The LCD according to claim 28, wherein the voltage supply device comprises:
a first sub-voltage supply device including a plurality of first voltage supply units, wherein
the ith first voltage supply unit provides the stable voltage with the positive polarity to the compensation line of all odd pixels of the ith or the (i+1)th pixel row and to the second end of the first storage capacitor according to a corresponding scan signal, and a first and a second clock signals; and
the (i+1)th first voltage supply unit provides the stable voltage with the positive polarity to the compensation line of all even pixels of the (i+1)th or the (i+2)th pixel row and to the second end of the first storage capacitor according to another corresponding scan signal, and the first and the second clock signals; and
a second sub-voltage supply device including a plurality of second voltage supply units, wherein
the ith second voltage supply unit provides the stable voltage with the negative polarity to the compensation line of all even pixels of the ith or the (i+1)th pixel row and to the second end of the second storage capacitor according to the corresponding scan signal, and the first and the second clock signals; and
the (i+1)th second voltage supply unit provides the stable voltage with the negative polarity to the compensation line of all odd pixels of the (i+1)th or the (i+2)th pixel row and to the second end of the second storage capacitor according to the another corresponding scan signal, and the first and the second clock signals.
42. The LCD according to claim 41, wherein a duty cycle of the first clock signal is substantially a frame period of the LCD, while the second clock signal is maintained enabled.
43. The LCD according to claim 41, wherein the ith first voltage supply unit comprises:
a first N-type transistor, having a gate and a source both coupled with each other to receive the second clock signal;
a second N-type transistor, having a gate coupled to a drain of the first N-type transistor, a source receiving the stable voltage with the positive polarity, and a drain coupled to the compensation line of all odd pixels of the ith or the (i+1)th pixel row and to the second end of the first storage capacitor;
a third N-type transistor, having a gate coupled to the ith scan line to receive the corresponding scan signal, and a source receiving the first clock signal;
a third capacitor, having a first end coupled to a drain of the third N-type transistor, and a second end coupled to the common line;
a fourth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the negative polarity, and a drain coupled to the gate of the second N-type transistor;
a fifth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the negative polarity, and a drain coupled to the compensation line of all odd pixels of the ith or the (i+1)th pixel row and to the second end of the first storage capacitor, wherein the ith first voltage supply unit further provides the stable voltage with the positive polarity to the compensation line of all odd pixels of the ith or the (i+1)th pixel row and to the second end of the first storage capacitor according to the corresponding scan signal, the first clock signal, and the second and a third clock signals, wherein there is a 180 degrees phase difference between the first clock signal and the second clock signal, and duty cycles of the second and the third clock signals are substantially an enable period of the corresponding scan signal; and
a sixth N-type transistor, having a gate and a source both coupled with each other to receive the third clock signal, and a drain coupled to the drain of the first N-type transistor.
44. The LCD according to claim 41, wherein the (i+1)th first voltage supply unit comprises:
a first N-type transistor, having a gate and a source both coupled with each other to receive the second clock signal;
a second N-type transistor, having a gate coupled to a drain of the first N-type transistor, a source receiving the stable voltage with the positive polarity, and a drain coupled to the compensation line of all even pixels of the (i+1)th or the (i+2)th pixel row and to the second end of the first storage capacitor;
a third N-type transistor, having a gate coupled to the (i+1)th scan line to receive the another corresponding scan signal, and a source receiving the first clock signal;
a third capacitor, having a first end coupled to a drain of the third N-type transistor, and a second end coupled to the common line;
a fourth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the negative polarity, and a drain coupled to the gate of the second N-type transistor;
a fifth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the negative polarity, and a drain coupled to the compensation line of all even pixels of the (i+1)th or the (i+2)th pixel row and the second end of the first storage capacitor, wherein the (i+1)th first voltage supply unit further provides the stable voltage with the positive polarity to the compensation line of all even pixels of the (i+1)th or the (i+2)th pixel row and to the second end of the first storage capacitor according to the other corresponding scan signal, the first clock signal, and the second and a third clock signals, wherein there is a 180 degrees phase difference between the second clock signal and the third clock signal, and duty cycles of the second and the third clock signals are substantially an enable period of the corresponding scan signal; and
a sixth N-type transistor, having a gate and a source both coupled with each other to receive the third clock signal, and a drain coupled to the drain of the first N-type transistor.
45. The LCD according to claim 41, wherein the ith second voltage supply unit comprises:
a first N-type transistor, having a gate and a source both coupled with each other to receive the second clock signal;
a second N-type transistor, having a gate coupled to the drain of the first N-type transistor, a source receiving the stable voltage with the negative polarity, and a drain coupled to the compensation line of all even pixels of the ith or the (i+1)th pixel row and to the second end of the second storage capacitor;
a third N-type transistor, having a gate coupled to the ith scan line to receive the corresponding scan signal, and a source receiving the first clock signal;
a third capacitor, having a first end coupled to a drain of the third N-type transistor, and a second end coupled to the common line;
a fourth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the negative polarity, and a drain coupled to the gate of the second N-type transistor;
a fifth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the positive polarity, and a drain coupled to the compensation line of all even pixels of the ith or the (i+1)th pixel row and to the second end of the second storage capacitor, wherein the ith second voltage supply unit further provides the stable voltage with the negative polarity to the compensation line of all even pixels of the ith or the (i+1)th pixel row and to the second end of the second storage capacitor according to the corresponding scan signal, the first clock signal, and the second and a third clock signals, wherein there is a 180 degrees phase difference between the second clock signal and the third clock signal, and duty cycles of the second and the third clock signals are substantially an enable period of the corresponding scan signal; and
a sixth N-type transistor, having a gate and a source both coupled with each other to receive the third clock signal, and a drain is coupled to the drain of the first N-type transistor.
46. The LCD according to claim 41, wherein the (i+1)th second voltage supply unit comprises:
a first N-type transistor, having a gate and a source both coupled with each other to receive the second clock signal;
a second N-type transistor, having a gate coupled to a drain of the first N-type transistor, a source receiving the stable voltage with the negative polarity, and a drain coupled to the compensation line of all odd pixels of the (i+1)th or the (i+2)th pixel row and to the second end of the second storage capacitor;
a third N-type transistor, having a gate coupled to the (i+1)th scan line to receive the another corresponding scan signal, and a source receiving the first clock signal;
a third capacitor, having a first end coupled to a drain of the third N-type transistor, and a second end coupled to the common line;
a fourth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the negative polarity, and a drain coupled to the gate of the second N-type transistor;
a fifth N-type transistor, having a gate coupled to the drain of the third N-type transistor, a source receiving the stable voltage with the positive polarity, and a drain coupled to the compensation line of all odd pixels of the (i+1)th or the (i+2)th pixel row and to the second end of the second storage capacitor, wherein the (i+1)th second voltage supply unit further provides the stable voltage with the negative polarity to the compensation line of all odd pixels of the (i+1)th or the (i+2)th pixel row and to the second end of the second storage capacitor according to the other corresponding scan signal, the first clock signal, and the second and a third clock signals, wherein there is a 180 degrees phase difference between the second clock signal and the third clock signal, and duty cycles of the second and the third clock signals are substantially an enable period of the corresponding scan signal; and
a sixth N-type transistor, having a gate and a source both coupled with each other to receive the third clock signal, and a drain coupled to the drain of the first N-type transistor.
47. The LCD according to claim 1, wherein the display panel is a single cell gap liquid crystal display panel.
48. A liquid crystal display, comprising:
a display panel, comprising:
a plurality of scan lines;
a plurality of data lines substantially perpendicularly disposed with the scan lines;
a plurality of pixels respectively electrically connected with corresponding data line and corresponding scan line and arranged in an array, each of the pixels comprising:
a common line receiving a common voltage; and
a compensation line;
a pixel transistor, having a gate coupled to the ith scan line and a source coupled to the ith data line, where i is a positive integer;
a first liquid crystal capacitor, having a first end coupled to a drain of the pixel transistor and a second end coupled to a common electrode; and
a first storage capacitor, having a first end coupled to the drain of the pixel transistor and a second end coupled to the common line;
an auxiliary common line;
a second storage capacitor, having a first end coupled to the drain of the pixel transistor and a second end coupled to the auxiliary common line;
a first capacitor, having a first end coupled to the drain of the pixel transistor;
a second liquid crystal capacitor, having a first end coupled to a second end of the first capacitor and a second end coupled to the common electrode; and
a second capacitor, having a first end coupled to the second end of the first capacitor and a second end coupled to the compensation line; and
a voltage supply device, coupled to the compensation line of each of the pixels, comprising:
a first sub-voltage supply device including a plurality of a first voltage supply units, wherein the ith first voltage supply unit is coupled to the compensation line of all odd pixels of the ith or the (i+1)th pixel row and to the second end of the first storage capacitor; and
a second sub-voltage supply device including a plurality of a second voltage supply units, wherein the ith second voltage supply unit is coupled to the compensation line of all even pixels of the ith or the (i+1)th pixel row and to the second end of the second storage capacitor.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. In a device for cleaning an ink jet print head having a nozzle exit surface with nozzle openings therein of a printing device in which the ink jet print head is mounted stationary but pivotable in a print window of a guide plate for items to be printed that are directed by the guide plate along the ink jet print head, and having a cleaning and sealing device behind the guide plate and below the ink jet print head that is movable toward and away from the ink jet print head by a displacement device and that contains a receptacle with a wiping device, a spray duct and a sealing cap in sequence behind the guide plate, the improvement comprising:
said wiping device being formed as an actuated, elastic wiping roller that is transversely freely rotatably directed along the nozzle exit surface in a cleaning operation implemented by said cleaning and sealing device, and that continuously rests without constraint on a cleaning element of the cleaning and sealing device.
2. The improvement of claim 1 wherein said wiping roller comprises a rigid core surrounded an elastic jacket, said rigid core being connected to an axle, said core having an outer surface and said jacket having an inner surface conforming to said outer surface of said core, with said jacket being held on said core by a friction fit.
3. The improvement of claim 2 wherein said elastic jacket is a hollow cylinder comprised of a resilient, absorbent material.
4. The improvement of claim 2 wherein said jacket is a hollow cylinder comprised of a rubber resilient material having a plurality of blades on an outer circumference of said hollow cylinder.
5. The improvement of claim 4 wherein said blades are oriented parallel to a rotational axis of said axle.
6. The improvement of claim 4 wherein said blades proceed helically relative to a rotational axis of said axle.
7. The improvement of claim 2 wherein said jacket is a hollow cylinder comprised of a rubber resilient material having a helically rotating, semi-circular bead on an outer circumference thereof.
8. The improvement of claim 2 comprising a pinion connected to said core that mechanically couples said wiping roller with said displacement device of said cleaning and sealing device.
9. The improvement of claim 2 comprising an autonomously operating actuator connected to said wiping roller.
10. The improvement of claim 9 wherein said actuator comprises a pair of gears driven by a motor, with one of said gears being directly connected to said wiping roller.
11. The improvement of claim 1 comprising a blade-shaped stripper forming said cleaning element, that interacts with said wiping roller to clean said wiping roller.
12. The improvement of claim 11 wherein said receptacle of said cleaning and sealing device comprises a U-shaped elastic retaining clip having a free end supported on a drive axle and having a transverse web that supports said winding roller and said stripper parallel to each other and positively resting on each other.
13. The improvement of claim 12 wherein said stripper is supported by said retaining clip allowing said stripper to be exchanged.
14. The improvement of claim 12 wherein said retaining clip comprises free legs, and wherein said receptacle comprises stops respectively for said free legs and compression springs supporting said free legs at an opposite side of said drive axle, said compression springs being disposed on respective pins attached to said receptacle.