All The Claims

1. An on-line system for printing a value-bearing item (VBI) comprising:
a plurality of user terminals coupled to a computer network;
a digitally signed advertisement graphics to be printed next to the VBI; and
a plurality of stateless cryptographic devices remote from the plurality of user terminals and coupled to the computer network, wherein the cryptographic devices include a computer executable code for verifying that the advertisement graphics is authorized to be printed next to the VBI, and wherein any one or more of the plurality of cryptographic devices may be used for verifying the advertising graphics for any one or more of the plurality of user terminals.
2. The system of claim 1, wherein the cryptographic devices include a computer executable code for verifying the advertisement graphics using a DSA algorithm, a public key, and a previously assigned digital signature.
3. The system of claim 2, wherein the computer executable code verifies if the digitally signed advertisement graphics has a correct digital signature file.
4. The system of claim 1, further comprising computer executable code for tracking a usage of the VBI.
5. The system of claim 4, wherein the usage of the VBI includes one or more of number of users signed up for the on-line system, number of users who have purchased at least a predetermined amount of VBI, number of users who have printed at least a predetermined amount of VBI, and number of users who have maintained an account for a minimum number of predetermined period.
6. The system of claim 1, wherein one or more of the cryptographic devices includes a computer executable code for preventing unauthorized modification of data.
7. The system of claim 1, wherein one or more of the cryptographic devices includes a computer executable code for ensuring proper operation of cryptographic security and VBI related meter functions.
8. The system of claim 1, wherein one or more of the cryptographic devices includes a computer executable code for supporting multiple concurrent users.
9. The system of claim 1, further comprising a database remote from the plurality of user terminals including information about the users.
10. The system of claim 9, further comprising a plurality of security device transaction data stored in the database for ensuring authenticity of the one or more users, wherein each security device transaction data can be processed in the server system in a stateless manner.
11. The system of claim 10, wherein each security device transaction data is related to a user.
12. The system of claim 11, wherein the security device transaction data related to a user is loaded into one or more of the cryptographic devices when the user requests to operate on a value bearing item.
13. The system of claim 12, wherein the security device transaction data related to a user is updated and returned to the database.
14. The system of claim 1, wherein one or more of the cryptographic devices performs cryptographic function on a transaction related to the database.
15. The system of claim 1, further comprising computer executable code for password authentication to prevent unauthorized access to the database.
16. The system of claim 9, wherein the database includes one or more indicium data elements, data for account maintenance, and data for revenue protection.
17. The system of claim 9, wherein the database includes virtual meter information.
18. The system of claim 9, wherein the database includes descending register data.
19. The system of claim 1, wherein the value bearing item is a mail piece.
20. The system of claim 19, wherein the postal indicium comprises a digital signature.
21. The system of claim 1, wherein the value bearing item is a ticket.
22. The system of claim 1, wherein a bar code is printed on the value bearing item.
23. The system of claim 1, wherein the value bearing item is a coupon.
24. The system of claim 1, wherein the value bearing item is currency.
25. The system of claim 1, wherein the value bearing item is a voucher.
26. A method for printing an advertisement next to a value-bearing item (VBI) via a communication network including a client system, and a server system, the method comprising the steps of:
interfacing with one or more users via the client system;
communicating with the client system over the communication network;
digitally signing an advertisement graphics to be printed next to the VBI; and
verifying the digitally signed advertisement graphics using any of a plurality of stateless cryptographic modules, wherein any of the plurality of cryptographic modules may be used for verifying the digitally signed advertisement graphics for any one or more of the users.
27. The method of claim 26, wherein the verifying step comprises the step of verifying the advertisement graphics using a DSA algorithm, a public key, and a previously assigned digital signature.
28. The method of claim 26, wherein the verifying step comprises the step of verifying if the digitally signed advertisement graphics has a correct digital signature file.
29. The method of claim 26, further comprising the step of tracking a usage of the VBI.
30. The method of claim 29, wherein the step of tracking comprises the step of tracking a VBI usage including one or more of number of users signed up for the on-line system, number of users who have purchased at least a predetermined amount of VBI, number of users who have printed at least a predetermined amount of VBI, and number of users who have maintained an account for a minimum number of predetermined period.
31. The method of claim 26, further comprising the step of preventing unauthorized modification of data.
32. The method of claim 26, further comprising the step of ensuring the proper operation of cryptographic security and VBI related meter functions.
33. The method of claim 26, further comprising the step of supporting multiple concurrent users.
34. The method of claim 26, further comprising the step of including information about the users in a database remote from the plurality of user terminals.
35. The method of claim 26, further comprising the step of storing in the database a plurality of security device transaction data for ensuring authenticity of the one or more users, wherein each security device transaction data is processed in the server system in a stateless manner.
36. The method of claim 35, wherein each security device transaction data is related to a user.
37. The method of claim 36, further comprising the step of loading the security device transaction data related to a user into the cryptographic module when the user requests to operate on a value bearing item.
38. The method of claim 26, further comprising the steps of preventing unauthorized modification of data using the cryptographic module.
39. The method of claim 26, further comprising the step of storing data for creating one or more indicium, account maintenance, and revenue protection.
40. The method of claim 26, further comprising the step of printing a mail piece.
41. The method of claim 40, wherein the mail piece includes a digital signature.
42. The method of claim 40, wherein the mail piece includes a postage amount.
43. The method of claim 40, wherein the mail piece includes an ascending register of used postage and descending register of available postage.
44. The method of claim 26, further comprising the step of printing a ticket.
45. The method of claim 26, further comprising the step of printing a bar code.
46. The method of claim 26, further comprising the step of printing a coupon.
47. The method of claim 26, further comprising the step of printing currency.
48. The method of claim 26, further comprising the step of printing a voucher.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor structure comprising:
a semiconductor crystalline substrate;
an insulator having an opening to the substrate;
a semiconductor crystalline material within the opening in the insulator, the crystalline material being lattice-mismatched with the substrate and having a planarized top surface with a root mean square surface roughness of 15 nm or less for the semiconductor crystalline material.
2. The structure of claim 1, wherein the substrate is configured with depressions in the substrate, and wherein the insulator overlies sides of the depression to form said opening.
3. The structure of claim 1, wherein the insulator is formed over the substrate, and wherein portions of the insulator over a top surface of the substrate are removed to form said opening.
4. The structure of claim 1, wherein the planarized top surface is polished by a slurry comprising an abrasive, less than 0.3% H2O2 30% solution and water.
5. The structure of claim 4, wherein the abrasive is suspended silica sub-micron particles, suspended ceria sub-micron particles or suspended alumina sub-micron particles, wherein the particles are between 20-90 nm in size, between 50-70 nm in size or spherical and approximately 60 nm in size.
6. The structure of claim 4, wherein the slurry mix is between 0.1% and 0.2% H2O2 30% solution or about 0.15% H2O2.30% solution.
7. The structure of claim 4, wherein polish selectivity of the crystalline material:the insulator is greater than 1:1, 3:1 or 5:1.
8. The structure of claim 1, wherein the opening is a trench, recess or hole.
9. The structure of claim 1, wherein the crystalline material is epitaxially grown.
10. The structure of claim 1, wherein the crystalline material is a group Ill-V compound or germanium.
11. The structure of claim 1, wherein the substrate comprises a single crystal substrate, a polycrystalline substrate or an amorphous substrate.
12. The structure of claim 11, wherein a surface of the substrate exposed in the insulator opening is a (001) surface of the silicon substrate, and wherein the substrate is a single crystal substrate.
13. The structure of claim 1, wherein dishing is below 50 nm, 20 nm or 10 nm.
14. The structure of claim 1, wherein the planarized surface of the crystalline material has a surface roughness RMS of 15 nm or less, about 10 nm or less, about 5 nm or less, about 1 nm or less, about 0.5 nm or less, or no greater than 0.2 nm.
15. A method of manufacturing a semiconductor structure comprising:
providing a semiconductor crystalline substrate;
providing an insulator having an opening to the substrate;
forming a semiconductor crystalline material within the opening in the insulator, the crystalline material being lattice-mismatched with the substrate; and
planarizing top surfaces of the insulator and crystalline material to be coplanar within 20 nm.
16. The method of claim 15, wherein the surface roughness is 20 nm or less, 10 nm or less, 5 nm or less, 1 nm or less, 0.5 nm or less, or 0.2 nm or less.
17. The method of claim 15, wherein forming the crystalline material comprises trapping defects of the crystalline material (arising from the lattice mismatch) at sidewalls of openings of the insulator.
18. The method of claim 15, further comprising:
etching the substrate to create depressions in the crystalline substrate; and
forming the insulator over the etched substrate in conformance to the substrate surface to create said sidewalls from an outer surface of the formed insulator.
19. The method of claim 15, wherein said planarizing comprises a ramp-up, polishing, ramp-down and rinse.
20. A semiconductor device comprising:
a substrate;
a first material having a plurality of openings in a surface;
a semiconductor crystalline material within the openings in the first material wherein the openings has an aspect ratio sufficient to trap defects in the crystalline material; and
a substantially planar top surface of a composite structure of the first and the crystalline material, wherein the semiconductor crystalline material has a submicron dimension.

1. A method for exposing an edge of a wafer in a photolithographic process, comprising the steps of:
(a) aligning a notch of the wafer disposed on a wafer chuck of an orientation flatness (OF) detecting system using a wafer notch-detecting sensor;
(b) performing a wafer edge exposure (WEE) process on the notch-aligned wafer;
(c) carrying the wafer to a wafer stage and then performing a wafer EGA alignment; and
(d) exposing the EGA aligned wafer.
2. The method of claim 1, further comprising disposing the wafer on the wafer chuck such that a center of the wafer is aligned with a center of the wafer chuck.
3. The method of claim 1, wherein step (a) comprises detecting the center of the wafer by a wafer center position detecting sensor unit, before disposing the wafer on the wafer chuck.
4. The method of claim 1, wherein step (c) is performed while exposing a preceding wafer.
5. An orientation flatness (OF) detecting system, comprising:
(a) a wafer loader arm able to carry a wafer;
(b) a wafer center position detecting sensor unit adapted to detect a center of the wafer;
(c) a rotatable wafer chuck on which the wafer is to be disposed;
(d) a wafer notch detecting sensor unit adapted to detect a notch of the wafer; and
(e) a wafer edge exposure (WEE) apparatus including a WEE unit adapted to expose an edge of the wafer disposed on the wafer chuck, and a WEE driving unit able to move the WEE unit.
6. The OF detecting system of claim 4, wherein the WEE driving unit is configured to move the WEE unit in a radial direction of the wafer.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A resonant clock system comprising:
a driver component configured to generate a driven input signal, wherein the driver component includes a plurality of drivers having varied sizes;
a clock load capacitor configured to receive the driven input signal;
an inductor array configured to have an effective inductance according to a selected frequency and to generate a resonant clock output signal at the selected frequency; and
a configuration controller configured to provide inductor configuration information to the inductor array and provide driver configuration information to the driver component, wherein the driver configuration information is configured to continuously enable a first power level from a first driver while continuously disabling power from a second driver throughout provision of a first selected frequency.
2. The system of claim 1, wherein the selected frequency is one of a plurality of available frequencies.
3. The system of claim 2, wherein the effective inductance is one of a plurality of available effective inductances.
4. The system of claim 1, wherein the driver component includes a plurality of drivers of varied sizes and the driver component is configured to utilize one of the plurality of drivers according to the selected frequency.
5. The system of claim 1, wherein the driver component is configured to receive a phase locked loop (PLL) signal as an input signal.
6. The system of claim 1, wherein the effective inductance has an inductive reactance equal to a capacitive reactance of the clock capacitor at the selected frequency.
7. The system of claim 1, wherein the inductor configuration information corresponding to a new selected frequency.
8. The system of claim 1, wherein the inductor array includes a plurality of inductors.
9. The system of claim 8, wherein the inductor array further includes switches coupled to the inductors, the switched configured to operate according to inductor configuration information.
10. The system of claim 8, wherein the plurality of inductors are connected in series.
11. The system of claim 8, wherein the plurality of inductors are connected in parallel.
12. The system of claim 1, wherein the driver configuration information is further configured to continuously enable a second power level from the second driver while continuously disabling the first driver throughout provision of a second selected frequency.
13. The system of claim 12, wherein the first driver has a first size that is greater than a second size of the second driver, the first power level is greater than the second power level, and the first frequency is greater than the second frequency.
14. A resonant clock system comprising:
a driver component configured to generate a driven input signal;
a clock load capacitor configured to receive the driven input signal;
an inductor array configured to have an effective inductance according to a selected frequency and to generate a resonant signal at the selected frequency; and
an inductor configuration component configured to automatically generate and provide inductor configuration information to the inductor array, the inductor configuration information generated according to the resonant signal and a PLL signal.
15. The system of claim 14, wherein the inductor configuration component includes a frequency comparator configured to receive the PLL signal and the resonant signal and a state machine configured to generate the inductor configuration information according to an output signal of the frequency comparator.
16. A resonant clock system comprising:
a PLL configured to generate a PLL signal;
a driver component configured to receive the PLL signal and to provide a driven signal;
an inductor array configured to receive the driven signal and to provide a resonant signal; and
an inductor configuration component configured to provide inductor configuration information to the inductor array according to the PLL signal;
wherein the inductor configuration component includes a frequency detector to detect frequencies of the PLL signal and the resonant signal.
17. A resonant clock system comprising:
a PLL configured to generate a PLL signal;
a driver component configured to receive the PLL signal and to provide a driven signal;
an inductor array configured to receive the driven signal and to provide a resonant signal; and
an inductor configuration component configured to provide inductor configuration information to the inductor array according to the PLL signal;
wherein the inductor configuration component includes a PLL counter and a resonant signal counter, wherein the PLL counter counts cycles of the PLL signal and the resonant signal counter counts cycles of the resonant signal in a selected time interval.