All The Claims

1. A display device comprising:
a substrate;
a plurality of pixel electrodes arranged in a matrix in a plane parallel with said substrate;
a display functional layer that exhibits an image display function on a basis of an image signal supplied to said plurality of pixel electrodes;
a driving electrode opposed to said plurality of pixel electrodes; and
a plurality of detecting electrodes (a) arranged in a plane opposed to said driving electrode, (b) separated and arranged at a pitch of a natural number multiple of an arrangement pitch of said pixel electrodes in one direction in the arrangement plane, and (c) with each capacitively coupled to said driving electrode,
wherein,
floating electrodes are arranged between the detecting electrodes in an arrangement of the detecting electrodes and an arrangement pitch of the detecting electrodes,
an arrangement pitch of the floating electrodes and an arrangement pitch of the detecting electrodes and the floating electrodes are each a natural number multiple of the arrangement pitch of said pixel electrodes,
a color filter layer colored in a different color in each pixel is disposed between then plane of said plurality of driving electrodes and the plane of said plurality of detecting electrodes,
in said color filter layer, a plurality of color regions including three color regions for RGB display are regularly arranged,
said detecting electrodes and said floating electrodes are each arranged at a natural number multiple of an arrangement pitch of said color regions in at least said one direction,
the display device has inter-electrode separation regions between said detecting electrodes, between said floating electrodes, and between said detecting electrodes and said floating electrodes, and
said inter-electrode separation regions are arranged so as to be superimposed on color regions of an identical color of said color filter layer in a view of a display surface of the display device in at least one of another direction orthogonal to said one direction and said one direction.
2. A display device comprising:
a substrate;
a plurality of pixel electrodes arranged in a matrix in a plane parallel with said substrate;
a display functional layer that exhibits an image display function on a basis of an image signal supplied to said plurality of pixel electrodes;
a plurality of detecting electrodes (a) arranged in a plane opposed to said driving electrode, (b) separated and arranged at a pitch of a natural number multiple of an arrangement pitch of said pixel electrodes in one direction in the arrangement plane, and (c) with each capacitively coupled to said driving electrode;
a plurality of driving electrodes arranged in a plane opposed to said plurality of pixel electrodes and separated and arranged at a pitch of a natural number multiple of the arrangement pitch of said pixel electrodes in another direction orthogonal to said one direction; and
a driving circuit for supplying said plurality of driving electrodes with a voltage serving as a reference for a voltage applied to said display functional layer and a driving voltage for detecting that magnitude of capacitances coupled to said plurality of detecting electrodes changes at a part of the detecting electrodes by selectively applying the driving voltage to each unit of a predetermined number of said driving electrodes among said plurality of driving electrodes and shifting selected and driven objects of the driving electrodes in said other direction,
wherein
floating electrodes are arranged between the detecting electrodes in an arrangement of the detecting electrodes and an arrangement pitch of the detecting electrodes,
an arrangement pitch of the floating electrodes and an arrangement pitch of the detecting electrodes and the floating electrodes are each a natural number multiple of the arrangement pitch of said pixel electrodes,
a color filter layer colored in a different color in each pixel is disposed between the plane of said plurality of driving electrodes and the plane of said plurality of detecting electrodes,
in said color filter layer, a plurality of color regions including three color regions for RGB display are regularly arranged,
said detecting electrodes and said floating electrodes are each arranged at a natural number multiple of an arrangement pitch of said color regions in at least said one direction,
the display device has inter-electrode separation regions between said detecting electrodes, between said floating electrodes, and between said detecting electrodes and said floating electrodes, and
said inter-electrode separation regions are arranged so as to be superimposed on color regions of an identical color of said color filter layer in a view of a display surface of the display device in at least one of another direction orthogonal to said one direction and said one direction.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of inter-channel bias (ICB) calibration in a global navigation system (GNSS) receiver, comprising:
receiving a plurality of GNSS radio-frequency (RF) signals;
converting the plurality of GNSS RF signals into a plurality of GNSS baseband signals utilizing an RF front-end processing unit;
generating a measurement result according to the plurality of GNSS baseband signals utilizing a baseband processing unit; and
calibrating the measurement result utilizing a plurality of pre-determined inter-channel biases.
2. The method of claim 1, wherein converting the plurality of GNSS RF signals into the plurality of GNSS baseband signals utilizing an RF front-end processing unit comprises:
converting the plurality of GNSS RF signals into a plurality of digital GNSS IF signals utilizing an analog front-end circuit; and
converting the plurality of digital GNSS IF signals into the plurality of GNSS baseband signals utilizing a digital front-end circuit.
3. The method of claim 2, wherein converting the plurality of GNSS RF signals into a plurality of digital GNSS IF signals utilizing an analog front-end circuit comprises:
amplifying the plurality of GNSS RF signals utilizing a low-noise amplifier;
converting the plurality of GNSS RF signals into a plurality of analog GNSS IF signals utilizing a first frequency-down converter;
filtering the plurality of analog GNSS IF signals utilizing a wideband complex band-pass filter; and
converting the plurality of analog GNSS IF signals into the plurality of digital GNSS IF signals utilizing an analog-to-digital signal converter.
4. The method of claim 2, wherein converting the plurality of digital GNSS IF signals into the plurality of GNSS baseband signals utilizing a digital front-end circuit comprises:
converting the plurality of digital GNSS IF signals into the plurality of GNSS baseband signals utilizing a plurality of second frequency-down converters; and
filtering the plurality of GNSS baseband signals utilizing a plurality of narrowband complex low-pass filters.
5. The method of claim 1, wherein the plurality of pre-determined inter-channel biases is obtained according to a plurality of theoretical or simulated inter-channel biases.
6. The method of claim 1, wherein the plurality of pre-determined inter-channel biases is obtained according to a result from at least a GNSS RF-signal receiving simulation.
7. The method of claim 1, wherein the plurality of pre-determined inter-channel biases is obtained according to the following steps:
generating a plurality of reference GNSS codes utilizing a reference GNSS code generator;
generating a plurality of reference GNSS RF signals utilizing a radio processing unit according to the plurality of reference GNSS codes;
emitting the plurality of reference GNSS RF signals;
receiving the plurality of reference GNSS RF signals via air transmission;
generating a reference measurement result via the RF front-end processing unit and the baseband processing unit according to the plurality of reference GNSS RF signals; and
comparing a difference in transmission latencies between the reference measurement result and the reference GNSS RF signals utilizing a pre-determined ICB generator.
8. The method of claim 1, wherein the plurality of pre-determined inter-channel biases is obtained by configuring a calibration channel from the RF front-end processing unit and comparing a difference in transmission latencies between the plurality of GNSS RF signals through the calibration channel and the plurality of GNSS RF signals through a normal channel of the RF front-end processing unit.
9. The method of claim 1, wherein the plurality of pre-determined inter-channel biases corresponds to at least a temperature value.
10. The method of claim 9, wherein the at least a temperature value is obtained utilizing a thermal sensor.
11. The method of claim 1, wherein the plurality of pre-determined inter-channel biases is stored in a pre-determined ICB table, wherein the pre-determined ICB calibration table is stored in a non-volatile memory.
12. The method of claim 1, wherein the plurality of GNSS RF signals comprises a plurality of global positioning system (GPS) RF signals.
13. The method of claim 1, wherein the plurality of GNSS RF signals comprises a plurality of European satellite navigation system (GALILEO) RF signals.
14. The method of claim 1, wherein the plurality of GNSS RF signals comprises a plurality of Global Orbiting Navigation Satellite System (GLONASS) RF signals.
15. The method of claim 1, wherein the plurality of GNSS RF signals comprises a plurality of Beidou navigation satellite system (COMPASS) RF signals.
16. A global navigation satellite system (GNSS) receiver, comprising:
a GNSS antenna, for receiving a plurality of GNSS RF signals;
an RF front-end processing unit, coupled to the GNSS antenna, for converting the plurality of GNSS RF signals into a plurality of GNSS baseband signals;
a baseband processing unit, coupled to the baseband processing unit, for generating a measurement result according to the plurality of GNSS baseband signals; and
an inter-channel bias (ICB) calibration unit, coupled to the baseband processing unit, for calibrating the measurement result utilizing a plurality of pre-determined inter-channel biases.
17. The GNSS receiver of claim 16, wherein the RF front-end processing unit comprises:
an analog front-end circuit, for converting the plurality of GNSS RF signals into a plurality of digital GNSS IF signals; and
a digital front-end circuit, coupled to the analog front-end circuit, for converting the plurality of digital GNSS IF signals into the plurality of GNSS baseband signals.
18. The GNSS receiver of claim 17, wherein the analog front-end circuit comprises:
a low-noise amplifier, for amplifying the plurality of GNSS RF signals;
a first frequency-down converter, coupled to the low-noise amplifier, for converting the plurality of GNSS RF signals into a plurality of analog GNSS IF signals;
a wideband complex band-pass filter, coupled to the first frequency down-converter, for filtering the plurality of analog GNSS IF signals; and
an analog-to-digital signal converter, coupled to the wideband complex band-pass filter, for converting the plurality of analog GNSS IF signals into the plurality of digital GNSS IF signals.
19. The GNSS receiver of claim 17, wherein the digital front-end circuit comprises:
a plurality of second frequency-down converters, for converting the plurality of digital GNSS IF signals into the plurality of GNSS baseband signals; and
a plurality of narrowband complex low-pass filters, each coupled to one of the plurality of second frequency-down converters, for filtering the plurality of GNSS baseband signals.
20. The GNSS receiver of claim 16, wherein the plurality of pre-determined inter-channel biases is obtained according to a plurality of theoretical or simulated inter-channel biases.
21. The GNSS receiver of claim 16, wherein the plurality of pre-determined inter-channel biases is obtained according to a result from at least a GNSS RF-signal receiving simulation.
22. The GNSS receiver of claim 16, further comprising:
a reference GNSS RF signals generator, comprising:
a reference GNSS code generator, for generating a plurality of reference GNSS codes;
a radio processing unit, coupled to the reference GNSS code generator, for generating a plurality of reference GNSS RF signals according to the plurality of GNSS codes; and
a radio antenna, coupled to the radio processing unit, for emitting the plurality of reference GNSS RF signals; and

a pre-determined ICB generator, coupled to the baseband processing unit, for comparing a difference in transmission latencies between a reference measurement result and the plurality of reference GNSS RF signals, and obtaining the plurality of pre-determined inter-channel biases accordingly;
wherein the reference measurement result is generated according to the plurality of reference GNSS RF signals received by the GNSS antenna via air transmission and converted by the RF front-end processing unit and the baseband processing unit.
23. The GNSS receiver of claim 16, wherein the plurality of pre-determined inter-channel biases is obtained by configuring a calibration channel from the RF front-end processing unit and comparing a difference in transmission latencies between the plurality of GNSS RF signals through the calibration channel and the plurality of GNSS RF signals through a normal channel of the RF front-end processing unit.
24. The GNSS receiver of claim 16, wherein the plurality of pre-determined inter-channel biases corresponds to at least a temperature value.
25. The GNSS receiver of claim 24, further comprising:
a thermal sensor, coupled to the ICB calibration unit, for obtaining the at lease a temperature value.
26. The GNSS receiver of claim 16, further comprising:
a pre-determined ICB calibration table, for storing the pre-determined inter-channel biases; and
a non-volatile memory, for storing the pre-determined ICB calibration table.
27. The GNSS receiver of claim 16, wherein the plurality of GNSS RF signals comprises a plurality of global positioning system (GPS) RF signals.
28. The GNSS receiver of claim 16, wherein the plurality of GNSS RF signals comprises a plurality of European satellite navigation system (GALILEO) RF signals.
29. The GNSS receiver of claim 16, wherein the plurality of GNSS RF signals comprises a plurality of Global Orbiting Navigation Satellite System (GLONASS) RF signals.
30. The GNSS receiver of claim 16, wherein the plurality of GNSS RF signals comprises a plurality of Beidou navigation satellite system (COMPASS) RF signals.

1. A parallax barrier for a three-dimensional (3D) image display, comprising:
a first substrate;
a second substrate opposite to the first substrate;
a first gap control electrode disposed on the first substrate;
a first passivation layer disposed on the first gap control electrode;
a liquid crystal control electrode disposed on the first passivation layer;
an opposing electrode disposed on the second substrate; and
a liquid crystal layer interposed between the first substrate and the second substrate,
wherein the liquid crystal control electrode includes a plurality of unit liquid crystal control electrodes,
wherein two neighboring unit liquid crystal control electrodes are spaced apart with a gap, and
wherein the first gap control electrode overlaps the gap between the unit liquid crystal control electrodes.
2. The parallax barrier for the 3D image display of claim 1, wherein
at least a portion of the first gap control electrode and at least a portion of the opposing electrode are applied with different voltages such that a block portion is formed in the liquid crystal layer corresponding to the gap between the unit liquid crystal control electrodes.
3. The parallax barrier for the 3D image display of claim 2, wherein
the first gap control electrode includes a plurality of unit gap control electrodes,
two neighboring unit gap control electrodes are spaced apart from each other, and
each of the unit gap control electrodes overlaps the gap between two corresponding unit liquid crystal control electrodes.
4. The parallax barrier for the 3D image display of claim 3, wherein
a voltage applied to a portion of the unit gap control electrodes is substantially the same as a voltage applied to the opposing electrode.
5. The parallax barrier for the 3D image display of claim 4, wherein
the opposing electrode includes a plurality of unit opposing electrodes,
two neighboring unit opposing electrodes are spaced apart from each other with a gap, and
each of the unit opposing electrodes overlaps both of two corresponding unit liquid crystal control electrodes.
6. The parallax barrier for the 3D image display of claim 5, further comprising:
a second gap control electrode disposed between the second substrate and the opposing electrode.
7. The parallax barrier for the 3D image display of claim 6, wherein
at least a portion of second gap control electrode and at least a portion of the unit liquid crystal control electrodes are applied with different voltages such that the block portion is formed in the liquid crystal layer corresponding to the gap between the unit opposing electrodes.
8. The parallax barrier for the 3D image display of claim 2, wherein
two neighboring unit liquid crystal control electrodes are applied with different voltages such that the liquid crystal layer corresponding to one of the two neighboring unit liquid crystal control electrodes forms the block portion or an opening portion.
9. The parallax barrier for the 3D image display of claim 2, wherein
at least two neighboring unit liquid crystal control electrodes are applied with a same voltage such that the liquid crystal layer corresponding to the at least two neighboring unit liquid crystal control electrodes forms the block portion or an opening portion.
10. The parallax barrier for the 3D image display of claim 9, further comprising:
a sensing unit which senses a position of an observer,
wherein a position of the block portion or a position of the opening portion corresponding to the unit liquid crystal control electrodes is changed based on the position of the observer sensed by the sensing unit.
11. The parallax barrier for the 3D image display of claim 10, wherein
the first gap control electrode includes a plurality of unit gap control electrodes,
two neighboring unit gap control electrodes are spaced apart from each other, and
each of the unit gap control electrodes overlaps the gap between two corresponding unit liquid crystal control electrodes.
12. The parallax barrier for the 3D image display of claim 11, wherein
a voltage applied to a portion of the unit gap control electrodes is substantially the same as a voltage applied to the opposing electrode.
13. The parallax barrier for the 3D image display of claim 10, wherein
the opposing electrode includes a plurality of unit opposing electrodes,
two neighboring unit opposing electrodes are spaced apart from each other with a gap, and
each of the opposing electrodes overlaps both of two corresponding neighboring unit liquid crystal control electrodes.
14. The parallax barrier for the 3D image display of claim 13, further comprising:
a second gap control electrode disposed between the second substrate and the opposing electrode.
15. The parallax barrier for the 3D image display of claim 14, wherein
at least a portion of the second gap control electrode and at least portion of the unit liquid crystal control electrodes are applied with different voltages such that the block portion is formed in the liquid crystal layer corresponding to the gap between the unit opposing electrodes.
16. A display device comprising:
a parallax barrier; and
a display panel,
wherein the parallax barrier comprises:
a first substrate;
a second substrate opposite to the first substrate;
a first gap control electrode disposed on the first substrate;
a first passivation layer disposed on the first the gap control electrode;
a liquid crystal control electrode disposed on the first passivation layer;
an opposing electrode disposed on the second substrate; and
a liquid crystal layer interposed between the first substrate and the second substrate,

wherein the liquid crystal control electrode includes a plurality of unit liquid crystal control electrodes,
wherein two neighboring unit liquid crystal control electrodes are spaced apart with a gap, and
wherein the first gap control electrode overlaps the gap between the unit liquid crystal control electrodes.
17. The display device of claim 16, wherein
at least a portion of first gap control electrodes and at least a portion of opposing electrodes are applied with different voltages to form a block portion in the liquid crystal layer corresponding to the gap between the unit liquid crystal control electrodes.
18. The display device of claim 17, wherein
the first gap control electrode includes a plurality of unit gap control electrodes,
two neighboring unit gap control electrodes are spaced apart from each other, and
each of the plurality of unit gap control electrodes overlaps the gap between two corresponding unit liquid crystal control electrodes.
19. The display device of claim 18, wherein
a voltage applied to a portion of the unit gap control electrodes is substantially the same as a voltage applied to the opposing electrode.
20. The display device of claim 19, wherein
the opposing electrode includes a plurality of unit opposing electrodes,
two neighboring unit opposing electrodes are spaced apart from each other, and
each of the unit opposing electrodes overlaps both of two corresponding unit liquid crystal control electrodes.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A package comprising:
a substrate configured to support a flip chip die, the flip chip die including a first surface mounted on the substrate and a second surface; and
a thermal collection layer formed on the second surface of the flip chip die, the thermal collection layer configured to dissipate heat generated by the flip chip die.
2. The package of claim 1 further comprising a plurality of bump connections interposed between the substrate and the first surface of the flip chip die.
3. The package of claim 2 wherein the plurality of bump connections include copper.
4. The package of claim 1 wherein the second surface of the flip chip die is opposite the first surface of the flip chip die.
5. The package of claim 1 further comprising a second die interposed between the flip chip die and the substrate.
6. The package of claim 1 further comprising a mold configured to protect the flip chip die and enclose a plurality of exposed surfaces of the flip chip die.
7. The package of claim 1 wherein the thermal collection layer includes copper.
8. A multi-chip package comprising:
a substrate configured to support a plurality of flip chip dies, each flip chip die from the plurality of flip chip dies including a first surface mounted on the substrate and a second surface; and
a thermal collection layer formed on the second surface of each flip chip die from the plurality of flip chip dies, the thermal collection layer configured to dissipate heat generated by the plurality of flip chip dies.
9. The package of claim 8 further comprising a plurality of bump connections interposed between the substrate and the first surface of each flip chip die from the plurality of flip chip dies.
10. The package of claim 9 wherein the plurality of bump connections include copper.
11. The package of claim 8 further comprising a mold configured to protect the package and enclose a plurality of exposed surfaces of the plurality of flip chip dies.
12. The package of claim 8 wherein the thermal collection layer includes copper.
13. The package of claim 8 wherein the plurality of flip chip dies comprises a power amplifier die, a controller die, and a switch die.
14. A method of manufacturing a package including a flip chip die including a plurality of surfaces, the method comprising:
mounting a first surface of the plurality of surfaces of the flip chip die on a substrate;
enclosing exposed surfaces of the plurality of surfaces of the flip chip die with a mold;
removing a portion of the mold to expose a second surface of the plurality of surfaces of the flip chip die, the second surface of the plurality of surfaces of the flip chip die opposite the first surface of the plurality of surfaces of the flip chip die; and
forming a thermal collection layer on the second surface of the plurality of surfaces of the flip chip die, the thermal collection layer configured to dissipate heat generated by the flip chip die.
15. The method of claim 14 further comprising interposing a plurality of bump connections between the substrate and the first surface of the plurality of surfaces of the flip chip die.
16. The method of claim 15 wherein the plurality of bump connections include copper.
17. The method of claim 15 wherein the thermal collection layer includes copper.
18. The method of claim 15 further comprising:
mounting on a substrate a first surface of a plurality of surfaces of a second flip chip die;
enclosing exposed surfaces of the plurality of surfaces of the second flip chip die with the mold;
removing a portion of the mold to expose a second surface of the plurality of surfaces of the second flip chip die, the second surface of the plurality of surfaces of the second flip chip die opposite the first surface of the plurality of surfaces of the second flip chip die; and
forming a thermal collection layer on the second surface of the plurality of surfaces of the second flip chip die, the thermal collection layer further configured to dissipate heat generated by the second flip chip die.
19. A wireless device comprising:
an antenna configured to transmit and receive signals;
a battery configured to power the wireless device; and
a circuit board including a flip chip package having a flip chip die, a substrate mounted on the circuit board and configured to support the flip chip die, and a thermal collection layer configured to dissipate heat generated by the flip chip die.
20. The device of claim 19 wherein the flip chip die includes a first surface mounted on the substrate and a second surface on which the thermal collection layer is formed.
21. The device of claim 20 wherein the flip chip package includes a second flip chip die having a first surface mounted on the substrate and second surface on which the thermal collection layer is formed.