All The Claims

1. A flash-spun plexifilamentary fiber strand having a surface area of less than 10 m2g and a crush value of at least 1 mmg.
2. The flash-spun plexifilamentary fiber strand of claim 1, wherein the surface area is less than 8 m2g.
3. The flash-spun plexifilamentary fiber strand of claim 1, wherein the surface area is less than 5 m2g.
4. The flash-spun plexifilamentary fiber strand of claim 1, wherein the crush value is at least 1.5 mmg.
5. A nonwoven sheet comprising substantially continuous, flash-spun plexifilamentary fiber strands, the strands having surface areas of less than 10 m2g and crush values of at least 1 mmg.
6. The nonwoven sheet of claim 5 having a Frazier Permeability, normalized to 1.0 ozyd2 basis weight, of at least 2 cfmft2.
7. The nonwoven sheet of claim 5 having a Gurley Hill Porosity of less than 6 seconds.
8. The nonwoven sheet of claim 6 having a hydrostatic head of at least 30 cm.
9. The nonwoven sheet of claim 6 having a hydrostatic head of at least 75 cm.
10. The nonwoven sheet of claim 6 having a hydrostatic head of at least 100 cm.
11. The nonwoven sheet of claim 6 having a hydrostatic head of at least 130 cm.
12. The nonwoven sheet of claim 5 having a Frazier Permeability, normalized to 1.0 ozyd2 basis weight, of at least 4 cfmft2.
13. The nonwoven sheet of claim 5 having a Frazier Permeability, normalized to 1.0 ozyd2 basis weight, of at least 10 cfmft2.
14. The nonwoven sheet of claim 5 having a Frazier Permeability, normalized to 1.0 ozyd2 basis weight, of at least 20 cfmft2.
15. The nonwoven sheet of claim 5 having a Frazier Permeability, normalized to 1.0 ozyd2 basis weight, of at least 25 cfmft2.
16. The nonwoven sheet of claim 5, wherein the sheet has a whole surface bonded portion of a first side of the sheet and a point bonded portion on the second side of the sheet, the point bonded portion of the sheet comprising at least 50% by weight of the nonwoven sheet.
17. The nonwoven sheet of claim 16, wherein the point bonded portion of the sheet comprises at least 60% by weight of the nonwoven sheet.
18. The nonwoven sheet of claim 17, wherein the point bonded portion to the sheet is bonded with a ribbed bonding pattern and the whole surface bonded portion of the sheet is bonded with a linen pattern.
19. A nonwoven sheet comprising substantially continuous, flash-spun plexifilamentary fiber strands and having a Frazier Permeability, normalized to 1.0 ozyd2 basis weight, of at least 2 cfmft2.
20. The nonwoven sheet of claim 19 having a Frazier Permeability, normalized to 1.0 ozyd2 basis weight, of at least 4 cfmft2.
21. The nonwoven sheet of claim 19 having a Frazier Permeability, normalized to 1.0 ozyd2 basis weight, of at least 10 cfmft2.
22. The nonwoven sheet of claim 19 having a Frazier Permeability, normalized to 1.0 ozyd2 basis weight, of at least 20 cfmft2.
23. The nonwoven sheet of claim 19 having a Frazier Permeability, normalized to 1.0 ozyd2 basis weight, of at least 25 cfmft2.
24. The nonwoven sheet of claim 19 having a hydrostatic head of at least 30 cm.
25. The nonwoven sheet of claim 19 having a hydrostatic head of at least 85 cm.
26. The nonwoven sheet of claim 19 having a hydrostatic head of at least 130 cm.
27. The nonwoven sheet of claim 19 having a Gurley Hill Porosity of less than 6 seconds.
28. A garment comprised of the nonwoven sheet of claim 5 or 19.
29. A flash-spun plexifilamentary fiber strand having a surface area of less than 10 m2g.
30. The flash-spun plexifilamentary fiber strand of claim 29, wherein the surface area is less than 8 m2g.
31. The flash-spun plexifilamentary fiber strand of claim 29, wherein the surface area is less than 5 m2g.
32. A nonwoven sheet comprising substantially continuous, flash-spun plexifilamentary fiber strands, the strands having surface areas of less than 10 m2g.
33. The nonwoven sheet of claim 32 having a Frazier Permeability, normalized to 1.0 ozyd2 basis weight, of at least 2 cfmft2.
34. The nonwoven sheet of claim 32 having a Gurley Hill Porosity of less than 6 seconds.
35. The nonwoven sheet of claim 33 having a hydrostatic head of at least 30 cm.
36. The nonwoven sheet of claim 33 having a hydrostatic head of at least 75 cm.
37. The nonwoven sheet of claim 33 having a hydrostatic head of at least 100 cm.
38. The nonwoven sheet of claim 33 having a hydrostatic head of at least 130 cm.
39. The nonwoven sheet of claim 32 having a Frazier Permeability, normalized to 1.0 ozyd2 basis weight, of at least 4 cfmft2.
40. The nonwoven sheet of claim 32 having a Frazier Permeability, normalized to 1.0 ozyd2 basis weight, of at least 10 cfmft2.
41. The nonwoven sheet of claim 32 having a Frazier Permeability, normalized to 1.0 ozyd2 basis weight, of at least 20 cfmft2.
42. The nonwoven sheet of claim 32 having a Frazier Permeability, normalized to 1.0 ozyd2 basis weight, of at least 25 cfmft2.
43. The nonwoven sheet of claim 32, wherein the sheet has a whole surface bonded portion of a first side of the sheet and a point bonded portion on the second side of the sheet, the point bonded portion of the sheet comprising at least 50% by weight of the nonwoven sheet.
44. The nonwoven sheet of claim 43, wherein the point bonded portion of the sheet comprises at least 60% by weight of the nonwoven sheet.
45. The nonwoven sheet of claim 44, wherein the point bonded portion to the sheet is bonded with a ribbed bonding pattern and the whole surface bonded portion of the sheet is bonded with a linen pattern.
46. A garment comprised of the nonwoven sheet of claim 32.
47. A flash-spun plexifilamentary fiber strand having a crush value of at least 1 mmg.
48. The flash-spun plexifilamentary fiber strand of claim 47, wherein the crush value is at least 1.5 mmg.
49. A nonwoven sheet comprising substantially continuous, flash-spun plexifilamentary fiber strands, the strands having crush value of at least 1 mmg.
50. The nonwoven sheet of claim 49, the strands having crush value of at least 1.5 mmg.
51. The nonwoven sheet of claim 49 having a Frazier Permeability, normalized to 1.0 ozyd2 basis weight, of at least 2 cfmft2.
52. The nonwoven sheet of claim 49 having a Gurley Hill Porosity of less than 6 seconds.
53. The nonwoven sheet of claim 51 having a hydrostatic head of at least 30 cm.
54. The nonwoven sheet of claim 51 having a hydrostatic head of at least 75 cm.
55. The nonwoven sheet of claim 51 having a hydrostatic head of at least 100 cm.
56. The nonwoven sheet of claim 51 having a hydrostatic head of at least 130 cm.
57. The nonwoven sheet of claim 49 having a Frazier Permeability, normalized to 1.0 ozyd2 basis weight, of at least 4 cfmft2.
58. The nonwoven sheet of claim 49 having a Frazier Permeability, normalized to 1.0 ozyd2 basis weight, of at least 10 cfmft2.
59. The nonwoven sheet of claim 49 having a Frazier Permeability, normalized to 1.0 ozyd2 basis weight, of at least 20 cfmft2.
60. The nonwoven sheet of claim 49 having a Frazier Permeability, normalized to 1.0 ozyd2 basis weight, of at least 25 cfmft2.
61. The nonwoven sheet of claim 49, wherein the sheet has a whole surface bonded portion of a first side of the sheet and a point bonded portion on the second side of the sheet, the point bonded portion of the sheet comprising at least 50% by weight of the nonwoven sheet.
62. The nonwoven sheet of claim 61, wherein the point bonded portion of the sheet comprises at least 60% by weight of the nonwoven sheet.
63. The nonwoven sheet of claim 62, wherein the point bonded portion to the sheet is bonded with a ribbed bonding pattern and the whole surface bonded portion of the sheet is bonded with a linen pattern.
64. A garment comprised of the nonwoven sheet of claim 47.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An electrical nonlinear pulse oscillator, comprising:
a nonlinear transmission line; and
a nonlinear amplifier having an input to accept a first signal and an output to provide a second signal, the nonlinear amplifier coupled to the nonlinear transmission line in a closed loop arrangement,
wherein the oscillator is configured to propagate along the nonlinear transmission line at least one nonlinear pulse having a target amplitude,
and wherein the nonlinear amplifier automatically amplifies or attenuates the first signal based at least in part on an average voltage of the first signal andor the second signal.
2. The oscillator of claim 1, wherein the at least one nonlinear pulse significantly resembles a soliton waveform.
3. The oscillator of claim 1, wherein the at least one nonlinear pulse includes a cnoidal wave.
4. The oscillator of claim 1, wherein the nonlinear amplifier includes at least one high pass filter.
5. The oscillator of claim 4, wherein the at least one high pass filter is configured so as to facilitate propagation along the nonlinear transmission line of only nonlinear pulses having essentially the target amplitude.
6. The oscillator of claim 4, wherein a cutoff frequency of the at least one high pass filter is selected so as to significantly impede soliton collisions along the nonlinear transmission line.
7. The oscillator of claim 4, wherein the nonlinear amplifier is configured to be spectrum preserving for nonlinear pulses having an essentially soliton waveform.
8. The oscillator of claim 4, wherein the nonlinear amplifier is configured to have an automatically adjustable nonlinear gain.
9. The oscillator of claim 8, wherein the nonlinear amplifier is configured to have a first gain greater than unity when the at least one nonlinear pulse has an amplitude less than the target amplitude and a second gain less than unity when the at least one nonlinear pulse has an amplitude greater than the target amplitude.
10. The oscillator of claim 9, wherein the nonlinear amplifier is configured to be spectrum preserving for nonlinear pulses having an essentially soliton waveform.
11. The oscillator of claim 4, wherein the nonlinear amplifier is configured to implement an adaptive bias control technique.
12. The oscillator of claim 11, wherein the nonlinear amplifier is configured to have at least one automatically adjustable bias point.
13. The oscillator of claim 4, wherein the nonlinear amplifier is configured to facilitate single mode operation of the oscillator.
14. The oscillator of claim 4, wherein the nonlinear amplifier comprises a first stage and a second stage.
15. The oscillator of claim 14, wherein the nonlinear amplifier includes complimentary NMOS and PMOS components.
16. The oscillator of claim 14, wherein the first stage includes a first high pass filter and the second stage includes a second high pass filter.
17. The oscillator of claim 14, wherein each of the first stage and the second stage includes feedback circuitry to facilitate an automatic adjustment of a bias voltage for the stage.
18. The oscillator of claim 17, wherein the feedback circuitry includes a low pass filter.
19. A method for generating periodic electrical nonlinear pulses, comprising acts of:
A) amplifying or attenuating a first signal in a nonlinear manner to provide a second signal;
B) applying the second signal to a nonlinear transmission line for propagation along the nonlinear transmission line to generate a third signal;
C) repeating the acts A) and B) using the third signal as the first signal; and

D) repeating the acts A), B) and C) such that the third signal develops the periodic nonlinear pulses having a target amplitude,
wherein the act A) includes an act of automatically amplifying or attenuating the first signal based at least in part on an average voltage of the first signal andor the second signal.
20. The method of claim 19, wherein the act A) includes an act of conditioning the first signal such that the periodic nonlinear pulses significantly resemble soliton waveforms.
21. The method of claim 19, wherein the act A) includes an act of high pass filtering the first signal to provide the second signal.
22. The method of claim 21, wherein the act of high pass flltering includes an act of high pass filtering to facilitate propagation along the nonlinear transmission line of only nonlinear pulses having essentially the target amplitude.
23. The method of claim 21, wherein the act of high pass filtering includes an act of attenuating frequencies below a selected cutoff frequency so as to significantly impede soliton collisions along the nonlinear transmission line.
24. The method of claim 21, wherein the act of high pass filtering includes an act of preserving a spectrum of nonlinear pulses having an essentially soliton waveform.
25. The method of claim 19, wherein the act A) includes acts of amplifying the first signal when the first signal andor the second signal has an average voltage less than a value representing the target amplitude, and attenuating the first signal when the first signal andor the second signal has an average voltage greater than the value representing the target amplitude.
26. A nonlinear amplifier for generating periodic electrical nonlinear pulses having an essentially soliton waveform, the amplifier comprising:
a first stage to receive an amplifier input signal and provide a first stage output signal, the first stage including at least one first semiconductor amplifying component and first feedback circuitry to facilitate a variable adjustment of a first bias voltage associated with the at least one first semiconductor amplifying component, wherein the first bias voltage is adjusted based at least in part on an average voltage of the first stage output signal; and
a second stage to receive the first stage output signal and provide an amplifier output signal, the second stage including at least one second semiconductor amplifying component and second feedback circuitry to facilitate a variable adjustment of a second bias voltage associated with the at least one second semiconductor amplifying component, wherein the second bias voltage is adjusted based at least in part on an average voltage of the amplifier output signal.
27. The amplifier of claim 26, wherein the first stage and the second stage are configured to be spectrum preserving for the nonlinear pulses having the essentially soliton waveform.
28. The amplifier of claim 26, wherein the first feedback circuitry and the second feedback circuitry are configured such that the amplifier has an automatically adjustable nonlinear gain.
29. The amplifier of claim 28, wherein the first feedback circuitry includes at least one first low pass filter and wherein the second feedback circuitry includes at least one second low pass filter to facilitate a gradual adjustment of the automatically adjustable nonlinear gain.
30. The amplifier of claim 26, wherein the at least one first semiconductor amplifying component and the at least one second semiconductor amplifying component are complementary components.
31. The amplifier of claim 30, wherein the at least one first semiconductor amplifying component includes at least one NMOS component, and wherein the at least one second semiconductor amplifying component includes at least one PMOS component.
32. The amplifier of claim 26, wherein the first stage includes a first high pass filter and the second stage includes a second high pass filter.
33. The amplifier of claim 32, wherein at least one of the first high pass filter and the second high pass filter is configured so as to facilitate propagation of only nonlinear pulses having a target amplitude.
34. The amplifier of claim 33, wherein a cutoff frequency of at least one of the first high pass filter and the second high pass filter is selected so as to significantly impede soliton collisions.
35. The amplifier of claim 33, wherein the first stage and the second stage are configured to be spectrum preserving for the nonlinear pulses having the essentially soliton waveform.

1. An interactive system for live streaming of data to and from a moving vehicle, comprising:
a plurality of data collection devices disposed in said vehicle;
a main control processing unit disposed in said vehicle and operationally connected to said plurality of data collection devices for receiving and processing data collected from said plurality of data collection devices; and
a communications means for transmitting and uploading a continuous stream of said collected data in real-time from said plurality of data collection devices via the main control processing unit to a remote control location.
2. The interactive system of claim 1, wherein said plurality of data collection devices comprises a plurality of digital video cameras.
3. The interactive system of claim 1, further comprising a means for a connecting said main control processing unit to a location identifying communication database.
4. The interactive system of claim 3, wherein said location identifying communication database comprises a GPS database.
5. The interactive system of claim 1, wherein said communications means comprises cellular communications.
6. The interactive system of claim 1, wherein said communications means comprises networked communications.
7. The interactive system of claim 1, further comprising a second control processing unit mounted in the remote control location suitably configured to receive and analyze data received from the main control processing unit.
8. The interactive system of claim 7, wherein said second central processing unit is configured as an authorized control processing unit for receiving and displaying data received from the main control processing unit over a networked connection.
9. The interactive system of claim 1, further comprising a means for connecting said main control processing unit to an audio communication device of said vehicle.
10. The interactive system of claim 6, wherein said main control processing unit is configured to receive, store and display data retrieved through the networked communications upon demand from an occupant of the vehicle.
11. The interactive system of claim 1, wherein said system is powered by a direct current battery of said vehicle.
12. The interactive system of claim 6, wherein said main control processing unit is configured for access by authorized communication via the networked communications.
13. The interactive system of claim 1, wherein said main control processing unit comprises a mini-ITX system.
14. The interactive system of claim 1, wherein said communication means comprises a wireless air card.
15. An interactive system for live streaming of data to and from a moving vehicle, comprising:
a plurality of data collection devices disposed in said vehicle;
a main control processing unit comprising a mini-ITX system disposed in said vehicle and operationally connected to said plurality of data collection devices for receiving, storing and processing data collected from said plurality of data collection devices, said main control processing unit being configured for access by authorized communication via networked communications;
a communications means for transmitting and uploading a continuous stream of said collected data in real-time from said plurality of data collection devices via the main control processing unit to a remote control location; and
a means for a connecting said main control processing unit to a location identifying communication database.
16. The interactive system of claim 15, further comprising a second control processing unit mounted in the remote control location suitably configured to receive and analyze data received from the main control processing unit.
17. The interactive system of claim 15, wherein said plurality of data collection devices comprises a plurality of digital video cameras.
18. The interactive system of claim 15, wherein said location identifying communication database comprises a GPS database.
19. The interactive system of claim 15, wherein said communications means comprises cellular communications.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for controlling programming voltage levels of non-volatile memory cells, the method comprising:
providing a resistive divider connected to a programming voltage reference and effective to generate at least one programming voltage level;
providing a reference cell crossed by a cell current; and
wherein cell current is applied to the resistive divider to correlate the programming voltage level to intrinsic features of the reference cell.
2. A control method according to claim 1 wherein the cell current is applied to the resistive divider in shunt configuration.
3. A control method according to claim 2 wherein the cell current is applied to an end of a resistive element comprised in the resistive divider and having a further end connected to the programming voltage reference.
4. A control method according to claim 1 wherein the reference cell is identical to the non-volatile memory cells to be programmed.
5. A control method according to claim 1, further comprising generating the programming voltage level with a high, respectively low, value for a low, respectively high, value of the cell current.
6. A control method according to claim 1, further comprising the resistive divider generating a plurality of programming voltage levels, wherein the programming voltage levels are obtained with a centering and separation correlated to intrinsic features of the non-volatile memory cells to be programmed.
7. A control method according to claim 5 wherein the voltage levels are moved closer, respectively away, in the case of fast, respectively slow, memory cells to be programmed.
8. A control method according to claim 5 wherein the voltage levels have reciprocal distances being lower, respectively higher, in the case of fast, respectively slow, non-volatile memory cells to be programmed.
9. A control method according to claim 1, further comprising providing a feedback of a current flowing in the resistive divider to correlate the programming voltage level to variations of the programming voltage reference.
10. A control method according to claim 1 wherein the feedback increases, respectively decreases, the cell current value applied to the divider in case of decrease, respectively increase, of the programming voltage reference.
11. A programming voltage regulator of non-volatile memory cells comprising at least an input stage inserted between a first and a second voltage reference and connected to a reference memory cell, as well as, in correspondence with an output terminal of the input stage, to a resistive divider, in turn inserted between a programming voltage reference and the second voltage reference and connected to at least an output terminal of the regulator, effective to supply a programming voltage to the non-volatile memory cells, wherein the output terminal of the input stage is connected to a first circuit node of the resistive divider in correspondence with an end of a resistive element included in the resistive divider and having a further end connected to the programming voltage reference, a voltage value on the first circuit node being thus obtained by shunting the programming voltage reference.
12. A voltage regulator according to claim 11 wherein the reference memory cell is identical to the non-volatile memory cells to be programmed.
13. A voltage regulator according to claim 11 wherein the reference memory cell has a control terminal connected to a band-gap voltage reference.
14. A voltage regulator according to claim 11 wherein the reference memory cell has a control terminal connected to a self-biasing network inserted between the first and second voltage reference and including a first transistor inserted between the first and second voltage reference and having a control terminal connected to a second circuit node, a second transistor inserted between the control terminal of the reference memory cell and the second voltage reference and a third transistor connected to the second voltage reference and to the output terminal of the input stage, the second and third transistor having control terminals connected to each other and to the second circuit node.
15. A voltage regulator according to claim 14 wherein the self-biasing network further comprises a capacitor inserted in parallel to the second transistor between the control terminal of the reference memory cell and the second voltage reference.
16. A voltage regulator according to claim 15 wherein the self-biasing network further comprises a fourth transistor inserted between the first voltage reference and the control terminal of the reference memory cell and having a control terminal connected to the second circuit node.
17. A voltage regulator according to claim 15 wherein the self-biasing network further comprises a fourth transistor inserted between the output terminal of the input stage and the control terminal of the reference memory cell and having a control terminal connected to the second circuit node.
18. A voltage regulator according to claim 11 wherein the input stage comprises a cascode block inserted between a biasing block and the reference memory cell, the biasing block comprising a first transistor being diode-connected and inserted between the first voltage reference and the cascode block, and a second transistor connected to the first voltage reference and having a control terminal connected to a control terminal of the first transistor.
19. A voltage regulator according to claim 18 wherein the cascode block comprises a cascode transistor inserted between the biasing block and the reference memory cell and having a control terminal connected through a buffer to the reference memory cell.
20. A voltage regulator according to claim 18 wherein the cascode block comprises a cascode transistor inserted between the biasing block and the reference memory cell and having a control terminal connected to a third circuit node of a second resistive divider included in a self-biasing network.
21. A voltage regulator according to claim 20 wherein the second resistive divider is inserted between a second circuit node and a third transistor of the self-biasing network and includes a first and a second resistive element interconnected in correspondence with the third circuit node.
22. A voltage regulator according to claim 11, further comprising an output stage inserted between the programming voltage reference and the output terminal of the regulator and connected to the first circuit node of the resistive divider, the output stage including an amplifier powered by the programming voltage reference and having a first input terminal connected to the first circuit node and a second input terminal connected to the output terminal, as well as a transistor inserted between the programming voltage reference and the output terminal and having a control terminal connected to an output terminal of the amplifier.
23. A programming voltage regulator of non-volatile multilevel memory cells comprising at least an input stage inserted between a first and a second voltage reference and connected to a reference memory cell, as well as, in correspondence with an output terminal of the input stage, to a resistive divider, in turn inserted between a programming voltage reference and the second voltage reference and having a plurality of circuit nodes connected to a plurality of output terminals of the regulator, effective to supply a plurality of programming voltage values for different levels of multilevel non-volatile memory cells, wherein the output terminal of the input stage is connected to a first circuit node of the resistive divider in correspondence with an end of a resistive element included in the resistive divider and having a further end connected to the programming voltage reference, a voltage value on the first circuit node being thus obtained by shunting the programming voltage reference.
24. A voltage regulator according to claim 23, further comprising a plurality of output stages, input-connected to the plurality of circuit nodes of the resistive divider, as well as to a plurality of output terminals to provide the plurality of programming voltage values for different levels of multilevel non-volatile memory cells.
25. A voltage regulator according to claim 23 wherein the reference memory cell is identical to the non-volatile memory cells to be programmed.
26. A voltage regulator according to claim 23 wherein the reference memory cell has a control terminal connected to a band-gap voltage reference.
27. A voltage regulator according to claim 23 wherein the reference memory cell has a control terminal connected to a self-biasing network inserted between the first and second voltage reference and including a first transistor inserted between the first and second voltage reference and having a control terminal connected to a second circuit node, a second transistor inserted between the control terminal of the reference memory cell and the second voltage reference and a third transistor connected to the second voltage reference and to the output terminal of the input stage, the second and third transistor having control terminals connected to each other and to the second circuit node.
28. A voltage regulator according to claim 27 wherein the self-biasing network further comprises a capacitor inserted in parallel to the second transistor between the control terminal of the reference memory cell and the second voltage reference.
29. A voltage regulator according to claim 28 wherein the self-biasing network further comprises a fourth transistor inserted between the first voltage reference and the control terminal of the reference memory cell and having a control terminal connected to the second circuit node.
30. A voltage regulator according to claim 28 wherein the self-biasing network further comprises a fourth transistor inserted between the output terminal of the input stage and the control terminal of the reference memory cell and having a control terminal connected to the second circuit node.
31. A voltage regulator according to claim 23 wherein the input stage comprises a cascode block inserted between a biasing block and the reference memory cell, the biasing block comprising a first transistor being diode-connected and inserted between the first voltage reference and the cascode block, and a second transistor connected to the first voltage reference and having a control terminal connected to a control terminal of the first transistor.
32. A voltage regulator according to claim 31 wherein the cascode block comprises a cascode transistor inserted between the biasing block and the reference memory cell and having a control terminal connected through a buffer to the reference memory cell.
33. A voltage regulator according to claim 31 wherein the cascode block comprises a cascode transistor inserted between the biasing block and the reference memory cell and having a control terminal connected to a third circuit node of a second resistive divider included in a self-biasing network.
34. A voltage regulator according to claim 33 wherein the second resistive divider is inserted between a second circuit node and a third transistor of the self-biasing network and includes a first and a second resistive element interconnected in correspondence with the third circuit node.
35. An apparatus to control programming voltage levels of non-volatile memory cells, the apparatus comprising:
a reference cell to generate a cell current representative of intrinsic features of the reference cell;
a circuit block having an input terminal coupled to the reference cell to receive the cell current and having an output terminal to provide an output voltage that can change in response to a change in the cell current; and
a resistive divider, coupled to the output terminal of the circuit block, to receive the output voltage and to generate at least one programming voltage level value therefrom that is correlated to the intrinsic features of the reference cell.
36. The apparatus of claim 35 wherein the output voltage provided by the circuit block is a shunt of a programming voltage reference.
37. The apparatus of claim 37 wherein the circuit block includes:
a biasing block;
a cascode block coupled between the biasing block and the reference cell; and
a self-biasing network coupled to the biasing block and to the resistive divider.
38. The apparatus of claim 1 wherein the resistive divider includes a plurality of nodes, each of the plurality of nodes being coupled to respectively provide a different programming voltage level value for different levels of the non-volatile memory cells.
39. A system for controlling programming voltage levels of non-volatile memory cells, the system comprising:
a means for providing a cell current representative of intrinsic features of a reference cell;
a means for applying the cell current to a resistive divider; and
a means for generating at least one programming voltage level value from the resistive divider based on the applied cell current, the programming voltage level value being responsive to a change in the cell current and being correlated to the intrinsic features of the reference cell.
40. The system of claim 39 wherein the means for applying the cell current to the resistive divider includes at least one of a bias network, cascode network, and self-biasing network.